Pramod Kumar is a back-end developer with over 8 months of experience working at Glitterbug Technologies. He received his M.Tech. in Electrical Engineering from IIT Bombay in 2015, specializing in electronic systems. His skills include Python, Django, PostgreSQL, HTML, CSS, and more. For his M.Tech. project, he implemented digital predistortion techniques on an FPGA board to reduce power amplifier distortions.

1. Pramod Kumar Back-End Developer
Electrical Engineering M.Tech.
Indian Institute of Technology Bombay Male
Specialization: Electronic Systems DOB: 04/02/1991
Email ID: pramodku.026@gmail.com Mob.: 7506134455
Examination University Institute Year CPI/%
Post Graduation IIT Bombay IIT Bombay 2015 8.25
Undergraduate Specialization: Electronics and Communication
Graduation UPTU Raj Kumar Goel Engg. College Ghaziabad 2012 72.25
Intermediate/+2 UP Board Sri Ram Pratap Inter College, Allahabad 2007 78.40
Matriculation UP Board Sri Ram Pratap Inter College, Allahabad 2005 63.83
SCHOLASTIC ACHIEVEMENTS
• Secured All India Rank(AIR) 20 in GATE-2013, Among 256000 students in Electronics & Com-
munication.
WORK EXPERIENCE
Glitterbug Technologies Pvt. Ltd. 8 Months [July 2015 to present]
• Working as Back-End Developer.
• HRMS: A Human Resource Development System application have been developed by team of
two. This app have features of managing holidays, employee’s project review and many more.
• I have been responsible for holidays part from scratch.
• Writing views for already developed models.
• Colaborating with HR personnel to ensure the working of API.
• Technologies used: Django, Python, Postgresql, Django Form, Django Template, HTML, CSS.
• OPS: We a team of two developed an Application to avoid the clashes during deployment which
uses celery task to run the task asynchronously.
• I have been responsible for writing celery task methods making logs of all deployments with time
and operations.
• Intracting with deployment engineer to implement the requirements precisely.
• Technologies used: Django, Python, Postgresql, Celery, HTML
TECHNICAL SKILLS
• Web Framework: Django
• Front-End: XML, AJAX, JSON, SOAP, CSS, HTML, jQuery, javascript
• Data Base Management System Software: Mysql, Postgresql
• Virsion Control Sytem: Git
• Programming Languages: Python, C/C++ & 8085 (Assembly level)
• Hardware description Languages: VHDL, Verilog
• EDA tools: Cadence, MAGIC, Ngspice, Xilinx ISE, ModelSim, ChipScopePro
M. TECH. PROJECT
FPGA based Implementation of Wideband Linearization of Power Amplifier
Guide: Prof. Shalabh Gupta
• Objective: To implement techniques to remove the distortions generated by power amplifiers
which otherwise lead to growth of spectral components in adjacent channel. Specifically, digital
pre-distorter are to be implemented on Xilinx Vitex-6 FPGA board.
• Achieved: Interfaced Xilinx Virtex-6 FPGA board, along with high-speed Texas Instruments (TI)
ADC (12 bit, 550 MSPS) and TI DAC (16 bit, 1.5 GSPS) boards and giving the input to the
ADC and analyzing the output of the DAC on the spectrum analyzer.
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2. • Learned generation of sine wave of variable frequency using Xillinx Virtex - 6 FPGA board and
sent it to high-speed Texas Instruments (TI) DAC (16 bit, 1.5GSPS) boards and seen output on
CRO.
• Generated QPSK signal in FPGA and implemented a pulse saping filter to avoid intersymbol
interference (ISI).
• Implemented a memory polynomial based digital predistortion at baseband level with the help of
indirect learning algorithm.
POSITIONS OF RESPONSIBILITY
• Teaching Assistantship
Communication lab (UG): Delivered pre-lab lectures every week. Also designed and
demonstrated experiments which were based on hardware as well as software like software
defined radios.
◦ Assisted students in performing experiments, evaluated them by taking viva - voce.
Digital circuit design lab (UG): Assisted students in performing experiments, evaluated
them by taking viva - voce.
PC lab: Responsible for maintenance of servers powered by Linux and PCs with Windows
as well as Linux .
• Class Representative
◦ Delivered an orientational lecture to the freshers regarding the curriculum of our stream.
◦ Arranged three meetings with one month of interval with freshers to help them in academic
problems and project selection.
◦ Arranged two meetings of our batch with seniors to have insight of future opportunities.
◦ Organised a welcome party for the freshers and farewell party for passing out janata both
having strength of more than 75 people.
MINOR PROJECTS/SEMINAR
• Design of a single lift controller (Course: VLSI Design Lab)[Feb. 2014]
◦ Implemented the controller for a single lift of 6 floors in VHDL . Designed for saving the Power
consumed by lift motor.
◦ Synthesized the design and performed the post synthesis simulation.
• Design of Lift Group Control System (Course: VLSI Design Lab)[March 2014]
◦ Implemented the controller system for 3 lifts in 6 floors in VHDL. Designed for minimizing the
average waiting time of passengers.
◦ Synthesized the design and performed the post synthesis simulation.
• Design of Pipeline version of ARM7 ISA equivalent Processor [March 2014]
(Course: Processor Design)
◦ Designed a 5-stage pipeline version of ARM7 ISA equivalent processor and simulated the design
in Verilog.
◦ Implemented data forwarding to prevent data hazards and stalls to prevent control hazards.
• Design of Virtual Channel Router for 4x4 NoC. (Course: VLSI Design Lab)[April 2014]
◦ Implemented in Verilog a router that uses Dimension Order routing, has 32-bit flits of specific
format and uses round-robin policy for switch allotment
◦ Synthesized the design and performed post synthesis simulation.
OTHER ACTIVITIES
◦ Regular swimming, playing volleyball and badminton and Enjoys cooking occasionally.
◦ Active in initiating talks with strangers and adept in building long-term interpersonal rela-
tionship.
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