1. Measurement of the hot carrier damage profile in LDMOS
devices stressed at high drain voltage
D. Corso a,*, S. Aurite a
, E. Sciacca a
, D. Naso a
, S. Lombardo a
, A. Santangelo b
,
M.C. Nicotra b
, S. Cascino b
a
CNR-IMM, Stradale Primosole, 50, 95121 Catania, Italy
b
STMicroelectronics, Stradale Primosole, 50, 95121 Catania, Italy
Available online 15 February 2007
Abstract
In this paper, the hot carrier degradation of laterally diffused nMOSFETs is investigated in detail by the analysis of the fundamental
device parameters and charge pumping measurements. Starting from this experimental characterization a new approach based on charge
pumping technique is developed to estimate the spatial distribution of the hot carrier damage. This methodology has been applied on test
structures, obtaining good results in the prediction of both the interface states and the trapped charges profiling. The supporting assump-
tions have been verified by fitting to the electrical data and by means of a two-dimensional device simulation.
Ó 2007 Elsevier Ltd. All rights reserved.
1. Introduction
The increasing need to achieve RF products suitable for
high power applications has found in the LDMOS (Later-
ally Diffused MOS) transistor one of the most important
devices, particularly in terms of high gain and high linearity
[1]. These performance requirements are achieved by means
of the introduction of a lightly doped drain (LDD) exten-
sion able to reduce the electric field between the drain
and the edge of the channel. Thanks to this, LDMOS tran-
sistors are widely used in power amplifiers at microwave
frequencies in commercial applications such as base-station
transmitters [2] and every time power handling is required.
Nevertheless, since their applications occur at high drain
voltages, effects of gate dielectric degradation due to hot
carrier damage are involved [3]. Therefore, a detailed
understanding of the damage build-up under operation is
necessary to allow accurate evaluation of long-term reli-
ability and to improve the device structure design [4]. This
paper provides a contribution in this direction, since it
reports a new methodology based on charge pumping
(CP) technique [5,6], able to discriminate the effects of
interface states and trapped charge to quantify the damage
under hot carrier stress.
2. Experimental
LDMOS structures with small areas (W · L = 132 ·
0.8 lm2
) and with non-nitrided gate oxides (thickness
about 62 nm) together with non-optimized LDD dose,
were prepared to test our methodology. Fig. 1 shows a
sketch of LDMOS test structure used in this work. As it
is possible to observe, it is basically a nMOSFET with
laterally diffused body and LDD structure at the drain.
The laterally diffused p+
implant enhances the RF gain
and prevents punch-through at high drain-source voltage
Vds, while the lightly doped drain extension controls the
drain-source breakdown voltage BVDSS. The length and
doping of the drain extension, together with the epitaxial-
layer resistivity and thickness, determine BVDSS. This
breakdown voltage can therefore be tuned for a specific
application. In our case the devices are designed to work
at Vds = 32 V. In this operational condition electrons and
holes in the channel and in the pinch-off region can gain
sufficient energy to overcome the energy barrier or tunnel
0026-2714/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2007.01.011
*
Corresponding author.
E-mail address: domenico.corso@imm.cnr.it (D. Corso).
www.elsevier.com/locate/microrel
Microelectronics Reliability 47 (2007) 806–809

2. into the oxide. Moreover, the impact of the hot carriers at
the oxide/Si interface under the gate, along the channel
and/or within the overlapped LDD region, can produce
both additional interface traps and oxide trapped charges,
leading to a degradation of the device performances.
Exploration of the mechanisms by which this degrada-
tion occurs is of critical importance to obtain reliable
devices. So, to study this effects we have chosen to perform
several stress conditions of drain voltages and times. In
particular, the devices were stressed at room temperature
in on condition at constant gate voltage of 3.9 V, which
is the typical gate bias for the applications of this family
of devices. Drain voltages ranging from 10 V to 40 V for
times ranging from seconds to days have been chosen to
explore different damage cases. In fact, in this conditions
the applied voltage stress monitors the degradation of some
fundamental device parameters, such as transconductance,
on-resistance RDS(on) or threshold voltage. Fig. 2 shows
the drain current curves versus time, i.e. injected charge
Qinj ¼
R
IDðtÞdt, when several constant drain voltages are
applied. As it is clearly visible, the current decreases and
so the RDS(on) increases. This worsening can be reasonably
attributed to a local degradation near the drain, where the
carriers have higher energy.
To improve the understanding of the damage profiling,
charge pumping measurements were performed maintain-
ing constant both the base level and the voltage slew rate.
A typical example of charge pumping curves taken on our
devices in fresh conditions and after stresses at constant
drain voltage with increasing stress time is reported in
Fig. 3.
It is well known that charge pumping curves evolve as a
consequence of two effects: hole or electron trapping in the
gate dielectric and interface states density build-up [7]. The
leading idea of our work is to extract the contributions of
the two effects by means of simple assumptions regarding
the damage profile before and after stress. In the following
section we describe this assumptions and a quantitative
model based on these concepts will be given.
3. Results and discussion
By assuming that the interface states of the fresh test
devices are uniformly distributed along the device interface
under the gate electrode, we can write the charge pumping
current as
Ifresh
cp ðXÞ ¼ qfWXNfresh
it ð1Þ
where q is the elementary charge, f is the frequency of the
gate pulse, W is the channel width, X is the channel
position, and Nfresh
it is the initial interface state density.
Therefore, the charge pumping curve of the fresh device
represents the lateral profile of the threshold voltage (posi-
tion dependent since the local channel doping concentra-
tion varies with the position) [8]
V fresh
th ðXÞ ¼ f À1
ðIfresh
cp ðxÞÞ ð2Þ
Fig. 2. Drain current curves versus injected charge (Qinj), at different
constant drain voltages.
Fig. 3. Charge pumping curves taken on a fresh device (dashed line) and
after stresses (continuous line) at constant drain voltage with increasing
stress time. The curves evolve as a consequence of two effects: hole or
electron trapping in the gate dielectric and interface states density (Nit)
build-up.
n+n-n+
p+ channel
poly-Si
oxide
p- epitaxy
p++ substrate
D SLDD
G
Fig. 1. Schematic cross section of the LDMOS structure used in this
study.
D. Corso et al. / Microelectronics Reliability 47 (2007) 806–809 807

3. From Silvaco ATLAS simulations, solving the
Boltzmann–Poisson equations in the hydrodynamic
approximation, a good exponential behaviour peaked at
the channel-LDD interface with an extinction length of
about 100 nm has been found in the impact ionization rate
profile. A typical example of these simulations, performed
in the same bias conditions of our experiments (Vds % 26 V
and Vgs–Vth of a few hundreds mV), is reported in Fig. 4. It
is then reasonable to expect that the lateral profile of the
damage in the gate dielectric under stress should mirror
the exponential profile of the impact ionization rate under
the channel. So, we assume that the oxide trapped charge
after stress, i.e. the threshold voltage shift ðDV postÀstress
th Þ,
and the additional density of interface states ðDNpostÀstress
it Þ
should follow a similar exponential behaviour:
DNpostÀstress
it ðXÞ ¼ DNpostÀstress
itmax
exp À
X
kNit
ð3Þ
DV postÀstress
th ðXÞ ¼ DV postÀstress
thmax
exp À
X
kV th
ð4Þ
where DNpostÀstress
itmax
and DV postÀstress
thmax
are the maximum values
of the damage profile directly extracted by the experimental
CP curves, and kNit
and kV th
are two free parameters. There-
fore, the charge pumping curve should evolve according to
the following equations:
IpostÀstress
cp ðXÞ ¼ Ifresh
cp ðXÞ þ qfW
Z X
0
DNpostÀstress
it ðX0
ÞdX0
ð5Þ
V postÀstress
th ðXÞ ¼ V fresh
th ðXÞ þ DV postÀstress
th ðXÞ ð6Þ
Now, by using an iterative method we fit the experimen-
tal charge pumping curves with the calculated ones. The
iterative method consists of varying independently the
two free parameters kNit
and kV th
until the best fit, evaluated
using the v2
method, is reached.
The proposed methodology produces an excellent agree-
ment with the experimental data, in a very large range of
drain stress and gate voltages, times, injected charge and
different technologies and device designs. Fig. 5 shows an
example of such agreement: in a log scale plot the charge
pumping curve calculated assuming the combined effect
of interface state and oxide trapped charge shows a very
good fit with the data in the whole investigated range.
This approach has been systematically applied varying
the drain voltage stress and, consequently, the injected
charge: Fig. 6 shows an example of charge pumping curves
taken on the same type of devices stressed at various levels
of injected charge and drain voltage together with the fit
curves.
As the injected charge increases, the calculated gate
dielectric damage profile evolves (Fig. 7) according to
Eqs. (3) and (4) and a typical example of the evolution of
the parameters involved is reported in Fig. 8. Note that
Fig. 4. Simulation of electron-hole impact ionization rate versus position
and extinction length of the damage. Note that a behaviour quite well
represented by a single exponential tail peaked at the channel-LDD
position and with an extinction length of about 100 nm has been obtained.
Fig. 5. Charge pumping curve (continuous line) calculated assuming the
combined effect of interface state (dashed line) and oxide trapped charge
(dash-dot line). Experimental data for fresh (triangles) and for stressed
(circles) device are also reported.
Fig. 6. Experimental charge pumping curves (circles) of devices stressed at
various levels of injected charge and drain voltage together with the fit
curves (dashed line).
808 D. Corso et al. / Microelectronics Reliability 47 (2007) 806–809

4. the best fit extinction lengths kNit
and kV th
are of the order
of 100 nm, i.e., very close to the values expected on the
basis of the calculation of the impact ionization rate
(Fig. 4).
In summary, using an iterative method, the simple
assumptions described in the Eqs. (1)–(4) consent to predict
the stress-induced CP current as a combined effect of inter-
face traps (Eq. (5)) and trapped charge (Eq. (6)). The dam-
age distributions (Fig. 7) are obtained after fitting the CP
curves produced by the model with the experimental ones.
4. Conclusions
In this paper, we have reported on a new method for the
quantitative evaluation of the damage profile in LDMOS
devices stressed at high voltages. We have found that the
hot-carrier mechanisms taking place at high drain voltages
lead to exponential distribution of the damage. Verification
of this result was also supported using Silvaco ATLAS sim-
ulations. With this new method, the spatial distributions of
both interface traps and trapped charge can be easily
extracted from the experimental charge pumping measure-
ments. This allows one to improve the understanding of the
degradation mechanisms taking place when the devices
work at high voltages.
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Fig. 7. Evolution of the gate dielectric damage profile with increasing
charge injected to the drain as calculated by Eqs. (3) and (4) to fit charge
pumping curves when devices are stressed at Vds = 30 V and Vgs = 3.9 V.
Fig. 8. Evolution of the parameters involved in Eqs. (3) and (4) as a
function of the injected charge at Vds = 30 V. DV thmax and DNitmax are the
maximum values of the damage profiles reported in Fig. 7, while kV th
and
kNit
are the extinction lengths of the same curves.
D. Corso et al. / Microelectronics Reliability 47 (2007) 806–809 809