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MODELING THE DEPOSIT THICKNESS DISTRIBUTION IN COPPER
ELECTROPLATING OF SEMICONDUTOR WAFER INTERCONNECTS
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2. MODELING THE DEPOSIT THICKNESS DISTRIBUTION IN COPPER
ELECTROPLATING OF SEMICONDUTOR WAFER INTERCONNECTS
Eugene Malyshev1
, Uziel Landau2
, and Sergey Chivilikhin1
1
L-Chem, Inc
Beachwood, OH 44122
and
2
Department of Chemical Engineering
Case Western Reserve University
Cleveland, OH 44106
Key words: Wafer plating; current distribution; metallization; electrodeposition; deposit thickness;
rotating electrode; impinging flow; Fluid-flow; boundary layer
©2003, Uziel Landau and L-Chem, Inc.
Prepared for Presentation at the Metallization Symposium, AIChE Annual Meeting, Nov. 17-18, 2003,
Unpublished
AIChE Shall Not Be Responsible For Statements or Opinions Contained in Papers or Printed in its
Publications

3. Abstract
The thickness uniformity of electrodeposited copper in interconnect metallization of semiconductor
wafers is critically important. Variations must be typically kept below ~ 3%, with only a few mm edge
exclusion. A number of process parameters, including the resistive copper seed and the wafer and anode
configurations that are controlled by practical design considerations, adversely affect the current
distribution. The complex system, which incorporates also non-linear electrode kinetics and fluid-flow
due to both forced convection and wafer rotation, cannot be modeled analytically and must be simulated
numerically. A comprehensive electrochemical computer aided-design software (“Cell-Design”) has
been used to simulate the system. Effects due to different cell configurations, seed thickness, different
electrolyte properties, and various flow conditions and current densities are presented and critically
discussed.
Introduction and background
Copper electroplating has recently become the standard technique for metallizing interconnects in high-
end microprocessors [1-3]. The requirements imposed on the copper metallization process are quite
severe. A copper layer with extreme thickness uniformity (less than 2-3% thickness variation across 200
mm wafers) must be plated onto a thin (500-2000 Å) copper seed through contacts along the
circumference of the wafer. Due to the scarcity of wafer area, the deposit uniformity must extend to the
wafer circumference, with only a few mm edge exclusion. Severe requirements are imposed on the
properties of the plated copper including electromigration performance, conductivity, adhesion,
mechanical properties (e.g., stress), grain size, reflectivity, and chemical purity. Maintaining those
within a narrow tolerance requires a uniform deposition rate. Excellent gap-fill capabilities are also
required; however, this paper does not address the micro-scale fill and focuses on issues related to the
macroscale current distribution uniformity.
The deposit thickness distribution across the wafer, which is directly proportional to the current density,
depends on numerous parameters, e.g., cell configuration including the side gap and shields, initial
thickness of the resistive seed layer, electrolyte conductivity, the average current density, the convective
flow, and the plating additives which affect the electrode kinetics. Because of the large number of
parameters, optimizing the process and the cell configuration empirically is quite tedious. We
demonstrate here the application of a commercial computer aided design software (Cell-Design) [4] to
rapidly, conveniently, and inexpensively study the multi-parameter space, and provide guidelines for
effective design. The software is based on numerically solving Laplace’s equation for the potential
within the electrochemical cell, using the boundary element method. The software provides, among
other parameters, the current and current density, deposit thickness, and potential distribution on axi-
symmetric bodies (i.e., the plated wafer) under primary (electrolyte ohmic resistance controlling),
secondary (mixed ohmic and electrode kinetics control) and tertiary (mixed ohmic, kinetics, and mass
transport control) current distributions. The software can also account for the resistive substrate and flow
effects. A moving boundaries capability can be used to simulate the profile of the growing deposit, by
time-stepping through the deposition process. The software is also capable of modeling the complete
fluid flow distribution in the cell; under the combined rotational and impinging ‘fountain’ flow.
Cell Configuration and typical process parameters
Most commercial plating cells for copper metallization of wafer interconnects consist of a cylindrical
enclosure, somewhat wider than the wafer diameter, with a dissolving copper anode at its bottom, as
shown schematically in Fig. 1. The wafer is dipped inverted (face down) into the electrolyte, and is
rotated at about 60 RPM during the plating. Typically, the electrolyte circulation is augmented by

4. superimposing impinging ‘fountain’ flow (at about 3-6 Gal/min), directed from the cell bottom towards
the wafer. The electrolyte egresses through a gap between the wafer circumference and the cell wall. The
current is fed through a continuous contact ring or multiple individual contacts surrounding the wafer
circumference [5].
Fig. 1: Cell “Generic” (or ‘base’) configuration: wafer radius = 100 mm, distance between wafer and anode =
150 mm, rotation = 60 rpm, flow from bottom = 4 GPM, gap between the wafer’s edge and cell’s wall = 10 mm, i
average = 20 mA/cm2
, κ = 0.55 S/cm, seed thickness = 1000 Å. Unless otherwise stated, those base conditions apply
to all subsequent simulations.
The wafer is usually plated under controlled current, typically in the range of 10 – 40 mA/cm2
. Often the
initial current density is low, e.g., 10 mA/cm2
, and once the vias and trenches are filled and a thicker
conductive layer has been deposited on the wafer, the current density is increased, to e.g., 20 or even 40
mA/cm2
. Initially, the electrolytes employed in wafer metallization were similar to those used in plating
of printed circuit boards: 0.24 M CuSO4 acidified by excess (e.g., 1M) sulfuric acid to a pH of about
zero, with an electrolyte conductivity of ~ 0.55 S/cm. More recently the trend has been towards more
concentrated electrolytes, in the range of 0.5 – 0.7 M CuSO4. To provide an improved deposit thickness
distribution and improved stability of the seed, less acidic electrolytes (pH ~ 1-3) have been introduced
[6,7].
Flow Effects
As stated above, and shown in Fig.1, the plated wafer is subject to a mixed flow: rotation (at about 60
RPM) and impinging flow (at about 4 GPM). Although the copper plates far below its limiting current
and therefore the flow effect on the plating is secondary, it is not negligible. First, the flow affects the
distribution of the plating additives that are present in trace amounts. The surface concentration of those
additives controls the deposition kinetics and hence the current distribution. Also, the copper
concentration at the plated surface is affected by the flow even below the limiting current, and therefore
the electrode kinetics are also affected. Consequently, for a uniform current density it is essential that the
equivalent boundary layer thickness will also be quite uniform over the wafer. Lastly, the via-fill
parameters are affected by flow, and in order to maintain uniform fill of all features distributed across
the wafer, it is essential to have uniform flow across the wafer.
The combined flow has been modeled using the fluid-flow simulation module of ‘Cell Design’. We
assume that the incoming flow is uniformly distributed at the anode plane which is located far below the
wafer. This is justified by the membrane that is typically placed above the anode and provides a high
resistance to flow. Typical simulation results are shown in Figs. 2 and 3. Fig. 2 shows the flow maps and
DISTRIBUTED FLOW = 4 gpm
10 mm
100 mm
ANODE
WAFERHOLDER
150mm
60 rpm
GAP
Applied Voltage
WAFERHOLDER
Seed thickness
1 cm
GAP
DISTRIBUTED FLOW = 4 gpm
10 mm
100 mm
ANODE
WAFERHOLDER
150mm
60 rpm
GAP
Applied Voltage
WAFERHOLDER
Seed thickness
1 cm
GAP

5. the equivalent Nernst-type mass transport boundary layer for the ‘base’ configuration and for a slightly
modified configuration where a barrier has been introduced near the wafer edge. In both configurations
the wafer is rotating at 60 RPM and is subject to 4 GPM impinging flow. As noted, the macro-scale flow
map indicates that the velocity within much of the cell is low and about uniform with some color
variation next to the electrode, indicating a velocity gradient next to the electrode. However, the
corresponding boundary layer thicknesses graphed below the color maps, indicate uniformity across the
wafer almost all the way (~90%) to the wafer circumference. The wafer exhibits about 18% thicker
boundary layer than the ideal rotating disk electrode (note comparison to Levich’s eqn.), because of
edge effects. Fig. 3 shows the boundary layer thickness as a function of the radial position for different
rotation speeds in combination with 4 GPM impinging flow. As noted, particularly at higher rotation
rates, the agreement between the simulated results and the Levich eqn. for the ‘ideal’ rotating disk is
excellent, indicating that the contribution of the impinging flow at 4 GPM is small.
0.0045
0.0055
0.0065
0.0075
0.0085
0.0095
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
r/R
Delta,cm
Levich eqn.
modified base case
FLOW MAP:
MODIFIED DESIGN
FLOW MAP:
BASE CASE
Fig. 2: Simulated fluid flow (60 RPM + 4 GPM impinging flow) in the plating cell. Right, Top: Flow map in
the ‘base’ cell as shown in Fig.1. As noted, the flow throughout most of the cell is low and about uniform. Only
at the wafer edge next to the gap through which the flow exits, the local velocity is higher. Left Top: A modified
edge configuration, where a barrier leads to a more uniform boundary layer thickness. Lower chart: mass
transport boundary layer as a function of the radial position. As noted the boundary layer is very uniform up to
about 80% of the wafer radius. The modified design with the barrier extends this uniform region almost all the
way to the wafer rim. Comparison with Levich’s eqn. for the rotating disk indicates that the boundary layer for
the rotating wafer is about 18% higher. Wafer radius = 100 mm, distance between wafer and anode = 15 cm, gap
= 1.5 cm for the “modified” barrier design and 1 cm for “base” setting.

6. Fig. 4 shows the effect of the width of the gap between the wafer edge and the cell wall. Shown is the
mass transport limiting current as a function of the radial position for different gap widths. Interestingly,
the limiting current decreases near the edge for larger gaps, however, for narrower gaps (e.g., 0.5 cm),
the boundary layer becomes thicker near the edge.
Fig. 4: Effect of edge-gap on the limiting current. Wafer radius = 100 mm, simulated gaps: 0.5 cm, 5
cm, 10 cm and 15 cm. Rotation = 60 rpm. Impinging flow = 4 GPM. Cb = 0.28 mol / L, D = 6.7*10-6
cm2
/s. ‘Cell-Design’ simulations.
0.03
0.05
0.07
0.09
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
ilim,A/cm
2
0.5 cm
5 cm
10 cm
15 cm
Cb = 0.28 [mol / L], D = 6.7*10-6 [cm2/s]
0.00
0.01
0.02
0.03
0 2 4 6 8 10 12
ω
1/2
δ,cm Cell-Design: rotating disk+4 GPM impinging
Rotating disk electrode (Levich eqn.)
[rad/sec]1/2
Fig. 3: The average mass transport boundary layer thickness along the wafer under combined flow
due to different rotation rates and impinging (fountain) flow of 4 GPM. The open circles indicate
the simulation results. The solid red line corresponds to the Levich equation for the rotating disk.
As noted, except for very low rotation speeds (the leftmost side), close agreement is noted between
the line (rotation) and the simulated values (rotation + impinging flow), indicating that under the
simulated conditions, the convective conditions are dominated by the rotation and not by the
impinging flow. The red dot corresponds to the simulated ‘base’ case (60 RPM + 4 GPM).
flow

7. Effects due to the resistive seed
The copper seed layer deposited by PVD is typically quite thin. Nominal values are around 1500 – 2000
Å, however, thinner seed (500-1000 Å) is sometimes encountered. Although the copper is highly
conductive (with resistivity, ρ = 1.67x10-6
Ω-1
cm-1
), because of its thinness, the film resistance, typically
measured in ohms/square, (film resistance = [ρ / (seed thickness)] = 0.167 Ω/□ for a 1000 Å seed) may
be comparable to, or exceed the activation overpotential and the ohmic drop in the electrolyte. Since the
plating current is fed from contacts on the circumference of the wafer, and must pass through the
resistive film, the current aggregates close to the edge, leading to non-uniformities. Analytical and
numerical modeling of this problem have been presented [8-11] for different assumed electrode kinetics
and different configurations. All the presented models invoke approximations that detract from the
accuracy of the solution. Using ‘Cell-Design’ software, we modeled the effects of the resistive substrate
in conjunction with the other process parameters, without invoking critical simplifying assumptions.
Fig. 5: Modeling the resistive substrate effect: Seed thicknesses = 500 Å, 1000 Å and 2000 Å. Current densities:
10 and 40 mA/cm2
. Base configuration includes: Wafer radius = 100 mm. Rotation = 60 rpm. Flow from the
bottom = 4 gpm. Cb = 0.28 mol/L, κ = 0.55 S/cm, D = 6.7*10-6
cm2
/s, and a 1 cm side-gap. ‘Cell-Design’
simulations.
Fig. 5 shows the current density profiles as a function of the radial position for seed thicknesses of 500
Å, 1000 Å, and 2000 Å, and two (average) current densities: 10 and 20 mA/cm2
. As expected, the
current density is higher near the circumference, with the effect more pronounced at the higher current
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
Current,A/cm
2
DISTRIBUTED FLOW = 4 gpm
60 rpm
10 mm
100 mm
ANODE
VAFER
HOLDER
150mm
DISTRIBUTED FLOW = 4 gpm
60 rpm
10 mm
100 mm
ANODE
VAFER
HOLDER
150mm
Applied Voltage
WAFERHOLDER
iaverage = 10 mA/cm2
iaverage = 40 mA/cm2
Seed thickness
500 A
1000 A
2000 A
500 A
1000 A
2000 A
1 cm
GAP
no seed
no seed
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
Current,A/cm
2
DISTRIBUTED FLOW = 4 gpm
60 rpm
10 mm
100 mm
ANODE
VAFER
HOLDER
150mm
DISTRIBUTED FLOW = 4 gpm
60 rpm
10 mm
100 mm
ANODE
VAFER
HOLDER
150mm
Applied Voltage
WAFERHOLDER
iaverage = 10 mA/cm2
iaverage = 40 mA/cm2
Seed thickness
500 A
1000 A
2000 A
500 A
1000 A
2000 A
1 cm
GAP
no seed
no seed
resistance
resistance

8. density of 40 mA/cm2
, and with the thinner seed. Obviously, as the copper deposit is being built, the
substrate resistance decreases and the current density becomes more uniform. However, this initial non-
uniformity is still apparent in the final deposit, as shown, e.g. in Fig. 6 below.
Effects due to Cell Configuration
The cell configuration affects, as expected, the current and deposit thickness distribution. A major
parameter that affects the current distribution is the edge gap that is required for the electrolyte egress
from the cell. If the cell could have been designed as a perfect cylindrical enclosure with no gap at the
edge, the current distribution, excluding the resistive substrate effect and the flow effects, would have
been perfectly uniform. Fig. 6 demonstrates the effects of the edge-gap size on the deposit thickness
distribution. It accounts for the combined effects due to current distribution at the edge, the resistive
substrate effect, and the fluid flow. The deposit thickness has been simulated by time-stepping the
deposition, allowing the copper layer to build-up, recalculating the distribution at every time step. The
profiles are not completely parallel due to the diminishing substrate resistance as the deposit builds-up.
Fig. 6: Effect of edge-gap variation. Wafer radius = 100 mm, gap variation: 0 cm, 1 cm and 5 cm. Seed
thickness = 1000 Ǻ. Rotation = 60 rpm. Flow from the bottom = 4 gpm. i average = 20 mA/cm2
, Cb = 0.28
mol/L, κ = 0.55 S/cm, D = 6.7*10-6
cm2
/s. ‘Cell-Design’ simulations.
Fig. 7 illustrates effects due to shield design at the wafer edge on the current distribution. Three
configurations are compared: Left, no shield, where a significant increase in the current density at the
edge is noticed; center, with a shield parallel to the wafer, showing only marginal improvement; right,
an optimized shield designed using an iterative application of ‘Cell-Design’, producing, as noted, quite a
uniform current density distribution.
0.0
0.5
1.0
1.5
2.0
2.5
0 1 2 3 4 5 6 7 8 9 10
r, cm
Deposit,micron
0.0
0.5
1.0
1.5
2.0
2.5
0 1 2 3 4 5 6 7 8 9 10
r, cm
Deposit,micron
0.0
0.5
1.0
1.5
2.0
2.5
0 1 2 3 4 5 6 7 8 9 10
r, cm
Deposit,micron
I = 20 mA/cm2
Gap = variable
Seed = 1000 A
60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
Gap
Gap = 0 cm Gap = 1 cm Gap = 5 cm
1-3 time steps = 20 sec, 4-7 time steps = 30 sec
150 sec 150 sec 180 sec

9. Fig. 7: Effect of shield design on the current distribution. To minimize the peak in the current density at the
wafer rim, a shield has been introduced. Three designs are compared: Left: No shield. Center: Edge shield parallel
to the wafer. Right: A slanted wedge. As noted, the slanted wedge provides an almost uniform distribution, all the
way to the wafer circumference. Conditions: Wafer radius = 100 mm, gap variation: 1 cm. (left) and 1.5 cm.
(center and right) Rotation = 60 rpm. Flow from the bottom = 4 gpm. i average = 20 mA/cm2
, Cb = 0.28 mol/L, κ =
0.55 S/cm, D = 6.7*10-6
cm2
/s, seed = 1000 Ǻ. ‘Cell-Design’ simulations.
Scale-up to 300 mm wafers.
The challenges of scaling the plating process from 200 mm (diameter) wafers to 300 mm involve
countering the increased resistive substrate effect, properly scaling the velocity field to assure uniform
mass transport properties over a significantly larger surface, and adjusting the edge gap design. This
process is significantly eased by software simulations. Fig. 8 compares the simulated deposit thickness
distribution on 200 and 300 mm wafers, both plated under the ‘base’ process conditions listed above,
with the exception that the impinging flow rate was increased in the 300 mm wafer from 4 to 9 GPM to
maintain about the same average linear flow velocity. The edge side gap was however, maintained the
same, at 10 mm. As noted, the deposit thickness ratio of edge to center is 1.65 for the 200 mm wafer and
1.85 for the 300 mm wafer. No edge shields were employed in these simulations.
Effects of process chemistry - electrolyte conductivity and plating additives:
The effects of two process parameters were explored through simulations: the electrolyte conductivity
and the effects of a common combination of plating additives. The effect of the copper concentration
was not explored here, because its major effect is on the gap-fill, as discussed in other papers in this
symposium e.g., ref. [12, 13], or elsewhere [7, 14]. It is recognized, however, that as the copper
60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
60 rpm60 rpm
DISTRIBUTED FLOW = 4 gpm
ANODE
WAFER
HOLDER
0.00
0.01
0.02
0.03
0.04
0.05
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
Current,A/cm2
0.00
0.01
0.02
0.03
0.04
0.05
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate
Current,A/cm2
0.00
0.01
0.02
0.03
0.04
0.05
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
Current,A/cm2

10. concentration changes, the deposition kinetics (mainly the exchange current density) will vary, and the
mass transport (which is proportional to the copper concentration), will change as well.
The conductivity affects mostly the ohmic resistance within the electrolyte, and consequently the
Wagner number that is a measure of the macroscopic current distribution (in the absence of a significant
substrate resistance) [15]:
⎟
⎠
⎞
⎜
⎝
⎛
∂
∂
==
Ω ilR
R
Wa aa ηκ
~
il
bκ
[1]
This dimensionless parameter represents the ratio of the activation resistance (Ra =
i
a
∂
∂η
), associated
with the electrodeposition reaction, which typically enhances uniformity, to the ohmic resistance of the
electrolyte (RΩ = κ/l). The latter is geometry dependent and usually causes non-uniformities. κ is the
electrolyte conductivity; l is the characteristic length (wafer scale) and ∂ηa/∂i is the slope of the
polarization curve (i vs. ηa) for the deposition reaction. The latter is controlled by the additives
composition. The approximation on the right of Eq. 1 pertains to the ‘Tafel regime’ where most copper
deposition takes place. Here, b is the ‘Tafel slope’ (= RT/αF) of the polarization curve. For uniform
distribution, a high Wagner number is desired, corresponding to high electrolyte conductivity, low
current density, and a high slope of the polarization curve.
Fig. 8: Comparison of the deposit thickness distribution on 200 mm wafer (top) vs. 300 mm wafer
(bottom). In both cases: Copper concentration = 0.28 mol/L, edge gap = 1 cm, impinging flow from the
bottom = 4 gpm for the 200 mm wafer and 9 gpm for the 300 mm wafer. Rotation speed of both wafers
was 60 rpm. Seed thickness was 1000 Å ‘Cell-Design’ simulations.
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
r/R
Depositthickness,micron
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
r/R
Depositthickness,micron
DISTRIBUTED FLOW = 4 gpm
10 mm
100 mm
ANODE
WAFERHOLDER
150mm
60 rpm
DISTRIBUTED FLOW = 9 gpm
10 mm
150 mm
150mm
60 rpm
GAP
200 mm wafer
300 mm wafer
20 sec
40 sec
60 sec
90 sec
120 sec
150 sec
180 sec
20 sec
40 sec
60 sec
90 sec
120 sec
150 sec
180 sec
d.th(r/R=1)/d.th(r/R=0)= 1.954/1.187 = 1.646
d.th(r/R=1)/d.th(r/R=0)= 2.043/1.106 = 1.847

11. In general plating applications where the same cell is often utilized to plate different objects, often of
complex geometry, the common approach is to employ a high conductivity electrolyte that brings about
a high Wa number. This is the rationale for the highly acidified copper sulfate electrolyte in common
plating applications, since the acid greatly enhances the conductivity [14]. However, in the present,
wafer plating application, it can be shown [7,14] that the deleterious resistive seed effect is enhanced by
a highly conductive electrolyte, and a more resistive, or less acidic electrolyte can be of benefit,
particularly when scaling to 300 mm wafers.
Fig. 9. compares the simulated deposit thickness distribution on 200 and 300 mm wafers for regular
acidity copper plating solution (κ ~ 0.55 S/cm) and a low acidity copper electrolyte (κ ~ 0.05 S/cm).
Although at first glance it might appear that the high acidity electrolyte produces a more uniform
distribution, a more careful inspection indicates that the low acidity copper produces a much more
uniform deposit over 90% of the wafer with the exception of the 10% region near the edge, where the
edge-gap effect produces, as expected a more pronounced deviation for the more resistive electrolyte.
With a proper shield design, such as indicated in Fig. 7, the extra uniformity of the low acidity copper
will extend just about all the way to the wafer circumference.
Fig. 9 Modeling the effects of conductivity and wafer diameter. Except as noted, the ‘base’
configuration was employed. ‘Cell-Design’ simulations.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Radial coordinate, cm
Totaldepositthickness,micron
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
Totaldepositthickness,micron
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 1 2 3 4 5 6 7 8 9 10
Radial coordinate, cm
Totaldepositthickness,micron
20 sec
40 sec
60 sec
90 sec
120 sec
150 sec
20 sec
40 sec
60 sec
90 sec
120 sec
150 sec
Disk - 200 mm
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Radial coordinate, cm
Totaldepositthickness,micron
iaverage = 20 mA/cm2
Seed size = 1000A
20 sec
40 sec
60 sec
90 sec
120 sec
150 sec
20 sec
40 sec
60 sec
90 sec
120 sec
150 sec
κ = 0.55 S/cm
κ = 0.55 S/cm
κ = 0.05 S/cm
κ = 0.05 S/cm
iaverage = 20 mA/cm2
Seed size = 1000A
iaverage = 20 mA/cm2
Seed size = 1000A
iaverage = 20 mA/cm2
Seed size = 1000A
Disk - 200 mm
Disk - 300 mm
κ = 0.55 S/cm κ = 0.05 S/cm
300 mm wafer:
200 mm wafer:
Low acidityHigh (normal) acidity
Seed thickness – 1000 Å
Seed thickness – 1000 Å Seed thickness – 1000 Å
Seed thickness – 1000 Å

12. Additives, whose presence is essential for obtaining the ‘bottom-up’ fill, are incorporated in the plating
electrolytes. The presence of the additives affects the deposition kinetics, and therefore also the
macroscopic current distribution. Since the additives are present in minute amounts, their distribution
across the wafer is likely to be flow-dependent. However, as discussed above, the boundary layer
thickness and the associated limiting current in typical wafer plating applications are essentially uniform
over the wafer area with deviations only at the very edge, leading to a uniform additives distribution.
The effects of a typical additives combination on the macroscopic current distribution is depicted in Fig.
10. Polarization curve that has been obtained on a disk electrode rotated at 60 RPM has been imported
into ‘Cell-Design’ and applied to the ‘base’ configuration. As expected, the current distribution in the
presence of the additives (blue line) exhibits a somewhat higher uniformity than the comparable
distribution of copper plating with no additives. Obviously, the current distribution in the presence of
additives will depend on the additives composition, as well as on the other process parameters and the
cell configuration.
Fig. 10: Additives effects on the macroscopic current distribution. The red line corresponds to pure
copper sulfate (0.5 M, pH =2); the blue line represents simulation of plating from the same electrolyte in
the presence of 70 ppm Cl-
, 50 ppm SPS and 200 ppm Polyethylene glycol [‘PEG’] (molecular wt. =
4000). ‘Cell-Design’ simulations.
Summary
The design of a process for copper electroplating of wafer interconnects involve numerous parameters
including the fluid-flow, average current density, initial seed thickness, cell configuration, and process
chemistry, among many others. Testing empirically the effects of those parameters, including their
interactions, is very labor intensive. Instead, we demonstrate the efficacy of an electrochemical
computer aided design software (‘Cell-Design’) to rapidly, conveniently, and inexpensively model,
optimize, and scale-up the process.
0.013
0.018
0.023
0.028
0.033
0.038
0.043
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
r/R
Currentdensity,A/cm
2
With additives
No additives

13. REFERENCES
1. P.C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans and H. Deligianni, IBM J. of Res. and Dev.
42(5), pp. 567-574, September, 1998
2. D. C. Edelstein, in Advanced Metallization Conference Proceedings in 1998, pp. 669-671, Mat. Res.
Soc. 1999.
3. J. Dahm and K. Monnig, Ibid. pp. 3-15.
4. ‘CELL-DESIGN’
®
, Computer Aided Design and Simulation software for Electrochemical Cells,
L-Chem, Inc. 13909 Larchmere Blvd. Shaker Heights, OH 44120
5. Yezdi Dordi, Uziel Landau, Jayant Lakshminkanthan, Joe Stevens, Peter Hey and Andrew Lipin,
“Contact Resistance in Copper Plating of Wafers – Analysis and Design Criteria,” Abstract # 365,
The Electrochemical Society Meeting, Toronto, Canada, May 2000
6. U. Landau et. al., Abstract No 263, 195th
Meeting of the Electrochem. Soc., Seattle, WA. May 2-6,
1999.
7. Uziel Landau, John J. D’Urso, and David R. Rear, “Electroplating Chemistry”, US Patent #
6,113,771. Sept. 5, 2000
8. C. W. Tobias and R. Wijsman, J. Electrochem. Soc. 100, 450 (1953).
9. O. Lanzi and U. Landau, ibid., 137, 1139-1143 (1990).
10. K. M. Takahasi, J. Electrochem. Soc. 147(4), 1414-1417 (2000).
11. Sergey Chivilikhin, Uziel Landau, and Eugene Malyshev, “Current Distribution On A Resistive
Wafer Under Copper Deposition Kinetics”, Paper # 190 b, (this symposium); Proceedings of the
AICHE Annual Meeting, , San-Francisco, CA Nov. 2003.
12. Rohan Akolkar and Uziel Landau, “Additives Interactions During Copper Interconnect
Metallization”, Paper # 189 c, (this symposium); Proceedings of the AICHE Annual Meeting, , San-
Francisco, CA Nov. 2003.
13. Uziel Landau, Eugene Malyshev, Rohan Akolkar, and Sergey Chivilikhin, “Simulations Of ‘Bottom-
Up’ Fill In Via Plating Of Semiconductor Interconnects”, Paper # 189 d, (this symposium);
Proceedings of the AICHE Annual Meeting, , San-Francisco, CA Nov. 2003.
14. Uziel Landau, “Copper metallization of semiconductor interconnects – Issues and Prospects”
Proceedings of the Electrochemical Soc., PV 2000-26, pp. 231-253. R. Opila et. al., Eds. (2000).
15. Uziel Landau, Proceedings of the D. N. Bennion Mem. Symp., R. E. White and J. Newman, Eds.,
The Electrochemical Society Proceedings Volume 94-9, 1994.
LIST OF SYMBOLS
b Tafel slope, RT/αF, Ω
C concentration, mole/cm3
D diffusivity, cm2
/sec
F Faraday’s constant, 96487 C/equiv
i current density, A/cm2
i0 exchange current density, A/cm2
iL limiting (diffusion) current, A/cm2
l characteristic length, cm
n number of electrons transferred in electrode reaction per mole reactant
r radius, cm

14. R universal gas constant, 8.3143 J/mole-deg
R resistance, ohm
T absolute temperature, deg K
Wa Wagner number, (ratio of activation to ohmic resistance), dimensionless
αa,αc, transfer coefficients, anodic and cathodic, respectively, dimensionless
δc equivalent mass transfer boundary layer thickness (Nernst-type), cm
η overpotential, V
ρ Resistivity, S-1
cm-1
κ conductivity, S/cm
Subscripts
a activation (kinetics)
avg average
B bulk
C mass transport
Ω ohmic
ACKNOWLEDGMENT
Rohan Akolkar (CWRU) carried polarization experiments in the presence of additives that provided the
kinetics parameters.
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