The document discusses a planar MEMS bio-chip developed for recording ion-channel currents in biological cells, aiming to replace conventional patch-clamping techniques that involve noisy glass micropipettes. The new design significantly reduces pipette resistance, enhances signal resolution, and facilitates integration with CMOS instrumentation amplifiers, leading to better noise performance and faster data collection. It details the design, fabrication, and circuit considerations necessary for implementing this technology in biochemical measurements.

1. See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/253216508
Planar MEMS bio-chip for recording ion-channel currents in biological cells
Article in Proceedings of SPIE - The International Society for Optical Engineering · January 2002
DOI: 10.1117/12.514745
CITATIONS
3
READS
36
3 authors, including:
Some of the authors of this publication are also working on these related projects:
Modeling Ion Channels View project
NSF Project View project
Santosh Pandey
Iowa State University
58 PUBLICATIONS 644 CITATIONS
SEE PROFILE
Marvin White
The Ohio State University
217 PUBLICATIONS 4,517 CITATIONS
SEE PROFILE
All content following this page was uploaded by Santosh Pandey on 04 September 2018.
The user has requested enhancement of the downloaded file.

2. PROCEEDINGS OF SPIE
SPIEDigitalLibrary.org/conference-proceedings-of-spie
Planar MEMS bio-chip for recording
ion-channel currents in biological
cells
Santosh Pandey, Zannatul Ferdous, Marvin H. White
Santosh Pandey, Zannatul Ferdous, Marvin H. White, "Planar MEMS bio-
chip for recording ion-channel currents in biological cells," Proc. SPIE 5062,
Smart Materials, Structures, and Systems, (14 October 2003); doi:
10.1117/12.514745
Event: Smart Materials, Structures, and Systems, 2002, Bangalore, India
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

3. A Planar MEMS Blo-Chip for Recording
Ion-Channel Currents in Biological Cells
Santosh Pandey1, Zannatul Ferdous2 and Marvin H. White3
1,3
Sherman Fairchild Center, Lehigh University, PA- 1 80 1 5, USA.
2
Kansas State University, Manhattan, KS-66506, USA.
ABSTRACT
We describe a planar MEMS silicon structure to record ion-channel currents in biological cells. The
conventional method of performing an electrophysiological experiment, 'patch-clamping', employs a glass
micropipette. Despite careful treatments of the micropipette tip, such as fire polishing and surface coating,
the latter is a source of thermal noise because of its inherent, tapered, conical structure, which gives rise to
a large pipette resistance. This pipette resistance, when coupled with the self-capacitance of the biological
cell, limits the available bandwidth and processing of fast transient, ion channel current pulses. In this
work, we reduce considerably the pipette resistance with a planar micropipette on a silicon chip to permit
the resolution of sub-millisecond, ion-channel pulses. We discuss the design topology of the device,
describe the fabrication sequence, and highlight important critical issues. The design of an integrated on-
chip CMOS instrumentation amplifier is described, which has a low-noise front-end, input-offset
cancellation, correlated double sampling (CDS), and an ultra-high gain in the order of 1O'2V/A.
1. INTRODUCTION
Miniaturized bio-chemical measurement systems will have a large impact on the way medical
diagnostics will be performed in the future, particularly in clinical diagnostics and pharmacology where the
use of living cells for fast specific and non-specific chemical sensing is an area of increasing importance
[1]. A cell or cell layer is a complex system with appropriate response to a variety of external physical and
chemical excitations. Experiments on such living biological systems can lead to the study of diffusion and
transport of biological or pharmacological molecules through the cell or cell layer. The ion-transport
mechanisms in living cells are governed by the opening and closing of microvalves in the cell membrane
called 'ion channels'. These ion channels use the energy stored in chemical concentration gradients to
produce small electrical signals during the movement of charged ions.
The patch-clamp technique is a method for studying the ion-channel behavior where a small
'patch' of the cell membrane is isolated for localized electrical measurement by placing a glass
micropipette onto the surface of a voltage-clamped cell. The patch-clamp setup and the electrical model of
the cell are shown in Figure 1. A biological cell has ion channels, each type of ion channel being
represented by a conductance GK and a resting potential VK. The cell membrane contributes a capacitance
CM and the seal formed between the patch and the glass pipette is represented by a conductance G5. The
glass pipette has a resistance R and a capacitance Cp associated with it. The electrical parameters of the
cell are not constant but may vary during the course of any patch-clamping experiment. Typical values for
a 1Otm cell are: GK = io9ci1, VK = 56mV, G = 1-2x1O'11, CM = 1O-2OpF, R = iO), C =O.OlpF.
Further author information (Send correspondence to S. Pandey)
Pandey: E-mail: skp31ehgh.edu, Tel.: 1 610 758 4518, Address: 16 A Memorial Drive East, Bethlehem, PA-18015.
White: Email: nihw0iehigh.edu, Tel.: 1 610 758 4421, Address: same as above.
Smart Materials, Structures, and Systems, S. Mohan, B. Dattaguru,
S. Gopalakrishnan, Editors, Proceedings of SPIE Vol. 5062 (2003)
© 2003 SPIE · 0277-786X/03/$15.00
814
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

4. In present-day patch-clamp circuitry, as shown in Figure 1 , the headstage is a transimpedance
amplifier (with a feedback resistor RF 5OG) forwhole-cell recording (Iwc'4nA) while it is a capacitive-
feedback integrator for single-channel recording (I5c'5pA). In addition to the basic amplifying-filtering
circuitry, there are also circuits for series-resistance compensation, high-frequency compensation and
capacitive-transients compensation [1]. This makes the entire patch-clamp electronics complicated, costly
and inappropriate for integration on a chip. One of the main sources of error in patch-clamp experiments is
the series resistance R associated with the micropipette. Besides the voltage drop across R, there is a time
constant for charging the cell ('rceij 'Rp.CM), which determines how soon the clamp-voltage may be applied
across the cell as well as the response of the particular ion-channel under study. This pipette resistance R
(because of the inherent conical shape of the pipette) can be a major source of noise at higher frequencies.
Compartmental models [2] are often used to exemplify the behavior of ion-channels and the overall cell
system, which in turn, help to analysis the signal characteristics.
In this work, we explore the possibility of performing patch-clamping on a planar MEMS
structure. The construction of a planar micropipettes in silicon would reduce this series resistance by orders
of magnitude (Re' 1O5Ok)), thereby giving improved noise performance. A planar, patch-clamp MEMS
structure has other advantages, such as integration-on-a-chip, cost-effectiveness and high-throughput-
screening (HTS), which is important in the study of pharmacological drugs. A noise analysis at the front-
end of the instrumentation amplifier shows a significant reduction in noise-current with the use of a planar
micropipette, instead of a conventional conical glass pipette. In this paper we discuss the device topology,
fabrication sequence, and circuit design of a patch-clamp, instrumentation amplifier. The low-power, low-
noise, transimpedance CMOS instrumentation amplifier is integrated on-chip with a ultra-high gain in the
order of lO'2V/A for amplifying the single, ion-channel currents.
Figure 1. This figure shows the conventional method ofdoing patch-clamp experiments. A glass pipette, which has the
testing medium, is placed on the cell and a gentle suction is applied to form a Gigaohm seal between the pipette tip and
the cell membrane {lJ. The electrical model of the cell and the pipette is also shown in the figure. A command voltage
vc is applied to the cell through the feedback action of the input operational amplifier. The measured signal goes to a
transimpedance amplifier, where it is amplified and fed to an A/D converter. The inset shows a magnified image of the
seal formation, with ions being exchanged through an ion-channel in the cell membrane.
2. DEVICE DESIGN AND FABRICATION
Recently, attempts have been made to replace the patch-clamp pipette with a planar chip-based
sensor [3,4]. Such an arrangement could facilitate automation and parallelization of ion-channel recording.
A miniaturization of the system on a silicon chip would also improve the sensitivity of the measurements,
by reducing the electrical capacitance and the pipette resistance.
To illustrate the detrimental noise contribution of the pipette resistance, a noise model has been
developed [3] for a capacitive-headstage of a patch-clamp system. The noise parameters of the low-noise
JFET-input opamp (LF155) are 'N= lOfAfHz"2 and EN = l5nVfHz"2 (for P1kHz). Figure 2 shows the
input-noise current for various values of the pipette resistance, R, with an opamp noise-current of
lOfAIHz"2. At frequencies below 700Hz, the total noise-current is dominated by the noise-current of the
Proc. of SPIE Vol. 5062 815
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

5. opamp. However, at higher frequencies, the noise associated with the pipette resistance, R, becomes
dominant. The introduction of a planar pipette on a silicon chip would reduce this intrinsic resistance,
thereby opening the possibility of recording faster switching ion-channel currents. The values of
components chosen for the simulation were R=1k, CF=O.25pF, BW=lOkHz, I,th=O.lpA, C=1OpF,
TrecordinglOms, ENl5nVfHz"2, INIOfAIHZ.
Figure 3 shows the topology of the planar patch-clamp structure fabricated in silicon. It consists of
a pore (O.5-ltm) in a thin nitride membrane (1000A° thick) resting on an ultra-deep well (325j.tm deep).
Applying standard lithography techniques, an etch mask was defined initially at the backside of the silicon
wafer. Subsequent anisotropic etching of silicon in aqueous KOH solution resulted in a V-shaped groove,
where the upper silicon nitride membrane served as an etch-stop. Thereafter, a focused-ion-beam system
was used to define an orifice in the nitride membrane. As the CHO cells [5] being used for our experiments
have a cell diameter of around lOtm, the size of the orifice was kept in the range of O.5-1tm. Figure 3
shows the silicon wells with the exposed nitride membrane on the other side. The inset shows the SEM
picture of a pore drilled in the nitride membrane using the Focused-Ion-Beam system. The front and back
microelectrodes for probing the ion currents, with the fluid chambers, are fabricated on separate Teflon
substrates and bonded to the silicon substrate.
Some of the challenges involved in performing a successful patch-clamp experiment on-chip are
the automated positioning of cells on the orifices, the biocompatibility of the chip surface, the formation of
a gigaohm seal between the cell membrane and the orifice, and the reduction of noise during the
measurements. The most crucial part of the experiment is, obviously, the formation of a high-resistance
seal in order to minimize the leakage current flowing around the cell. For this, the shape, the size and the
surface chemistry of the orifice are of utmost importance. We have been able to fabricate structures with
nice and smooth orifices, as seen from Figure 2. At present, we are in the process of culturing cells in the
silicon wells and studying the method of seal formation.
V,11.
V,12
Figure 2: The figure on the left shows the noise model of an integrating-differentiating headstage used in patch-clamp
amplifiers. The noise sources in the operational amplifier, the pipette resistance and the reset action of the switch are
taken into account. The figure on the right shows a plot of the input-referred noise current with varying frequency for
this noise model. The resistance in glass pipettes is of the order of 1OM, while that in planar topology is less than
5Ok. From the plot it is observed that as this resistance is decreased, the input-noise current becomes independent of
the thermal noise in the resistance and it is the noise ofthe operational amplifier that is dominant [31.
816 Proc. of SPIE Vol. 5062
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

6. BATH .. . .
NUrOR
OLJ 1 ' TH
*4LE PCDE
4—... FLUD
CHAMFR5
CoDLrD
FRONT
ELECTFXF
Figure 3: The figure on the left shows the topology of the device fabricated for planar patch-clamping. The figure on
the left is a SEM picture of the suspended nitride membrane in an anisotropically-etched, silicon well. The inset shows
a nanopore drilled in the membrane.
3. CIRCUIT DESIGN AND SIMULATION RESULTS
The conventional patch-clamp or voltage-clamp amplifier is basically a sensitive 'current to
voltage' (I-V) converter, which converts small (5-lOOpA) currents into voltage signals [1,6]. These voltage
signals can be subsequently displayed on an oscilloscope or A/D converted for storage in a computer. The
single-channel currents are random pulses with a frequency in the range of 1-2.5kHz. One traditional type
of amplifier design (Figure 1) utilizes an operational amplifier configured as a transimpedance amplifier, to
measure ion currents in response to an applied 'clamp' potential. The commercial input stage is generally a
low noise (<2 nV/Hz"2) Junction Field Effect Transistor (JFET), which draws very little current (<1 pA DC
current) at its gate. Thus, any current entering this node is forced to flow through the feedback resistor, RF,
and the amplifier develops an output voltage proportional to the input current. This technique is useful in
whole cell measurements, where the total ion current is large, but it is not a good approach for single ion
channel measurements, where the ion channel current is typically less than 2OpA. Large values of resistors
are difficult to employ because of limited time resolution and noise bandwidth, excessive 1/f noise, inherent
nonlinearity, and long-term instability.
For the above reasons, instrument manufacturers, such as Axon Instruments Inc. [7], have adopted
a design based upon an integrating front-end amplifier or 'headstage', where the noise is significantly lower
and the linearity is greatly improved over the transimpedance approach. The basic idea is to integrate the
ion current to create a 'slew rate' at the output of the integrator of I/CF (V/sec). This is followed by a
differentiator with a time constant of RCd, which yields an output voltage of IRCd/CF proportional to the
input current. The signal is amplified and passed through a low-pass filter, where the high frequency
components are band-limited. The resultant output is amplified, filtered, A/D converted, and stored in a
computer. These amplifiers are limited by head-stage noise, noise-pickup and vibrations associated with
long leads, restricted bandwidth, single-cell diagnostics, and high system cost.
The instrumentation amplifiers available today, like the electrometers or the patch-clamp
amplifiers, are constructed with discrete components for the most part. The basic reason for this
construction is the circuit-design techniques for the amplification of low-level signals requires very large
values of electrical components, which are unobtainable in the fabrication of integrated circuits. The
transimpedance method employs a gigaohm feedback resistance and the integrating-differentiating
amplifier approach requires differentiators with very large time-constants, which necessitates both large
resistances and capacitances. The integration of these electronics into a microelectronics chip requires a
redesign and careful consideration to the signal processing of high-speed, low-level currents. In a patch-
clamp experiment, having the entire electronics very close to the signal-recording site (e.g. electronics and
biological cell on the same microelectronic chip) would reduce the noise by several orders of magnitude
and increase the bandwidth permitting fast ion-channel current pulses to be observed.
.4-
Proc. of SPIE Vol. 5062 817
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

7. The circuit diagram in Figure 4 shows the CMOS operational amplifier used in the design. The
circuit consists of three stages: (1) a differential input stage consisting of PMOS transistors with large
width-to-length ratios to minimize the 1/fnoise at the input, (2) a single-ended gain stage, and (3) an output
buffer stage. Frequency compensation is accomplished with a capacitor and a "nulling" resistor between
the output and the input of the second stage. The overall gain and bandwidth of the circuit can be
programmed by varying the voltage Vbja. to the current sources. The sizes of the MOS transistors are shown
in the figure. The overall performance of the operational amplifier was simulated with XSPICE. The
figures of merit for the circuit are unity-gain 3dB frequency =2.5MHz, power dissipation at zero-input =
4.4mW, Output offset voltage at zero-input =O.98mV, Slew rate =O.35V/p.s.
The design requirements for the instrumentation amplifier are on-chip integration, low-noise front-
end, input-offset cancellation, an ultra-high gain in the order of 1O'2V/A, fast-transient signal processing,
and CMOS compatibility. Figure 5 shows the circuit design of the instrumentation amplifier. It consists of
an integrator stage, a differential stage, a clamp capacitor stage, a differentiator stage, and a low-pass
filtering stage. The instrumentation amplifier utilizes correlated double sampling (CDS) [8] to remove the
offset-voltages and the noise during reset. The CDS method is widely used in continuous-time and
switched-capacitor circuits [9] and was developed originally to suppress kTC noise, filter 1/f noise, and
remove offsets in advanced image sensors [8]. The CDS signal processing technique is employed in our
CMOS instrumentation amplifier for the processing oflow-level ion-channel current pulses.
The CMOS instrumentation amplifier circuit is designed to operate in three modes: the reset mode,
the clamp mode and the normal signal-handling mode. Initially, all the switches are open and there is no
input-signal. During the reset mode, the reset switch "phiR" is closed and the integrator has near unity gain
such that the integrator output voltage is equal to the opamp input-offset voltage. Subsequently, the clamp
mode starts wherein the clamp switch "phiC" is closed and the reset level, as well as the offset voltage of
the integrator, is stored on the clamp-capacitor CC. During the reset-and-clamp operations, the remaining
amplifiers in the chain are disabled to prevent switching transients from propagating to the output. After
this reset-and-clamp operation, the switches "phiR" and "phiC" are opened. Then, the normal signal-
handling mode begins where the command potential "Vcomm" is applied on the cell and the signal "Isig" is
allowed to pass through. The integrator integrates the incoming pulses, followed by the differential
amplifier stage. The noise and offset stored in the clamp-capacitor CC is subtracted from the signal. During
this time, the two sampling switches, "phiSi" and "phiS2", are operating through non-overlapping clocks
with a clock frequency around 100kHz. At the sampling stage, the signal is sampled and its value is stored
on the sampling-capacitors CS. Next, the differential amplifier subtracts the delayed version of the previous
sampled signal from the instantaneous sampled signal. This is similar to discrete-time differentiation. The
output is passed through a low-pass filter, which removes the high-frequency components in the amplified
signal. This circuit was simulated on XSPICE and the results at different stages are shown in Figure 6.
.rdw4
Figure 4: This figure shows the transistor-
level design of the operational amplifier,
along with the sizes of the components. The
voltage and current-levels in the figure
correspond to the case of zero-input voltage.
i 40V
818 Proc. of SPIE Vol. 5062
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

8. Figure 5: A block diagram of the CMOS instrumentation amplifier designed for measuring very low-level signals, as
those encountered in single, ion-channel patch-clamp recording. Shown are an integrator stage, a differential stage, a
clamp capacitor stage, a differentiator stage, and a low-pass filtering stage. The circuit employs correlated double
sampling (CDS) in three modes: the reset mode, the clamp mode and the normal signal-handling mode.
_________I
Figure 6: XSPICE simulation results ofthe CMOS instrumentation amplifier. The first plot (1) shows a representation
ofthe input current signal into the front-end, integration amplifier. The second plot (2) shows how the integrated signal
is clamped/sampled and stored in the two sampling-capacitors CS. The third plot (3) shows the signal after it has passed
through the discrete-time differentiator. The last plot (4) shows the amplified signal after the low-pass filter with a 1V
output for a 5pA input - responding to 8kHz input current pulses. A high degree of amplification is achieved for low-
level signals with good offset/noise cancellation and minimum clock feedthroughs ofthe switches.
— i(v31)
it
MS time
— %/(55)
— vd) —
50
rV
40
:: ..
.
1?
0
-10 . . . . .
0.0 0.1 0.2
S tire
mY
— v(62)
2
V
:_'
o: 0.2
mS time
mS time
Proc. of SPIE Vol. 5062 819
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use

9. 4. CONCLUSION
In this work, we present the design of an integrated patch-clamp system (MEMS 'nanowells' and
CMOS instrumentation amplifier) on a silicon chip for on-site measurement of ion-channel currents
through biological cells. This integrated system has advantages over the conventional method ofusing glass
micropipettes such as, High Throughput Screening (HTS), increased sensitivity and dynamic range, and
cost effectiveness. The MEMS 'nanowells' are fabricated with silicon micromachining to create apertures
of nano/microscale dimensions in thin membranes ('—4000A°) suspended in ultra-deep wells. A Focused-
Ion-Beam (FIB) provides flexibility to drill apertures of varying sizes and shapes with smooth curvatures in
thin membranes, as seen with SEM pictures. The circuit design of a low-power, low-noise, CMOS patch-
clamp instrumentation amplifier is discussed and verified with computer simulations. This instrumentation
amplifier boosts low-level currents ('5pA) to voltage signals (1V) at input-frequencies in the range of 1-
8kHz. Offset cancellation and noise suppression is performed with Correlated Double Sampling (CDS).
Clock feed-through in switches is minimized using CMOS transmission-gate switches with small overlap
capacitance. The integrated CMOS patch-clamp amplifier permits the recording of low-level, single-
channel, fast transient ion-channel currents over a wide dynamic range.
The integration of 'nanowells', to hold biological species, with instrumentation amplifiers, which
can sense small surges/fluctuations in ion-channel currents, will be extremely beneficial to numerous fields
in biotechnology. At the basic level, a 'planar' integrated patch-clamp system provides experimental results
on fast-transient ion-channel currents, to enable researchers to understand the effects of pharmacological
drugs on cellular behavior. Ion channel research plays an increasingly important role in understanding
numerous diseases and processes in the cardiovascular system and the central nervous system. An
understanding of ion-channel behavior will provide valuable insight into diseases and disorders, such as
migraine, epilepsy, Alzheimer's, cardiac arrhythmias, cystic fibrosis, and hypertension. As an example of
an exciting area of research, in the field of DNA sequencing, there is a need for a better and faster
alternative to the existing chemical methods of DNA sequencing (gel electrophoresis, dideoxy method,
Polymerase Chain Reaction (PCR)). A successful integrated patch-clamp system can be modified to
electronically sequencing single-stranded DNA by electrophoretically trapping and passing it through an
aperture, where the current changes can be identified with the different nucleotide base diameters of the
strand. In this instance, the current fluctuations would be around the same order in magnitude as those in
single-channel recording. A highly sensitive, integrated amplifier near the aperture on the same chip would
provide an added advantage to electronically sequence DNA.
ACKNOWLEDGEMENT
The National Science Foundation, under grants ECS-8886178 and ECS-0225436, has provided funding for
this research and a Sherman Fairchild Fellowship has been provided for the first author, Pandey.
REFERENCES
1. Bert Sakmann and Erwin Neher, "Single Channel Recording 'PlenumPress, 1995.
2. S. Pandey and M. H. White, "Parameter-Extraction of a Two-Compartment Model for Whole-Cell
Data Analysis", accepted for publication in Journal ofNeuroscience Methods (2002).
3. S. Pandey and M. H. White, "An Integrated Planar Patch-Clamp System", ISDRS Proc., pp.l7O-'73,
2001.
4. N. Fertig et al, "Microstructured glass chip for ion-channel electrophysiology", Phys. Rev. E, 64,
pp.040901-3, 2001.
5. http://www.atcc.org/SearchCatalogs/CellBiology.cfm
6. F.J. Sigworth, "Design ofthe EPC-9, a computer-controlled patch-clamp amplifier. 1.Hardware,"
Journal of Neuroscience Methods, 56, pp.195-202, 1995.
7. AxonInstruments, "Axopatch 200B Manual' 2000.
8. M. H. White et al, "Characterization of Surface Channel CCD Image Arrays at Low Light Levels",
IEEEJ. Solid-State Circuits, SC-9, pp.1-13, 1974.
9. P. Allen et al, "Switched Capacitor Circuits 'Van Nostrand Reinhold Company, 1984.
820 Proc. of SPIE Vol. 5062
Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 9/4/2018
Terms of Use: https://www.spiedigitallibrary.org/terms-of-use
View publication stats
View publication stats