Ramesh P.E and Parthasarathy Raju of Tektronix discuss the three high-speed serial standards - MIPI D-PHY, MIPI M-PHY and MIPI C-PHY, which although having similarities in terms of target segment and application use cases, do have wide contrasts with respect to electrical specifications. Inevitably, engineers will encounter varied issue/challenges while debugging or testing these designs. This presentation shall provide real-world problems faced and the process of uncovering them early on using the test and measurement equipment and solutions.
Manoj Sharma Tanikella and Amitkumar Shrichand Gound of Synopsy describe various training sequences used in MIPI PHYs to reduce inter-symbol interference.The latest MIPI PHY specifications (M-PHY, D-PHY and C-PHY) introduce training sequences for the equalizer settings to reduce inter-symbol interference: adapt sequence in M-PHY, alternate sequence in D-PHY and C-PHY. In addition, C-PHY uses preamble and user-define sequences.
MIPI DevCon Bangalore 2017: Next generation MIPI Physical Layer Design and Ev...MIPI Alliance
SK Choi of Keysight Technologies covers the new technology innovation brought by MIPI PHY specifications and the new challenges to design or evaluation engineering. In this presentation, he examines the key changes in the specification and CTS (conformance test suite) and addresses the challenges to support the new PHY layer.
MIPI DevCon 2020 | Snapshot of MIPI RFFE v3.0 from a System-Architecture Per...MIPI Alliance
Lalan Mishra, vice-chair of the MIPI RFFE Working Group, presents the new features of MIPI RFFE v3.0 to help architecture and design engineers understand how the triggering features in the latest version work together to improve performance and to switch quickly among the various bands and band combinations in a 5G system.
MIPI DevCon 2020 | Interoperability Challenges and Solutions for MIPI I3CMIPI Alliance
This presentation from Geoffrey Duerden of Introspect Technology features a case study of several specific interoperability challenges and solutions in terms of circuit and layout guidelines, protocol implementations and target applications.
MIPI DevCon Taipei 2019: Addressing 5G RFFE Control Challenges with MIPI RFFE...MIPI Alliance
Andrew Scott-Mackie, RF control systems engineer at Intel Corporation, discusses how MIPI RFFE℠ 3.0 aims to meet the new 5G control timing requirements and adds several enhancements to the RFFE-Trigger specification to meet 5G use cases.
MIPI DevCon 2021: Meeting the Needs of Next-Generation Displays with a High-P...MIPI Alliance
Presented by Alain Legault, Hardent Inc.; Joe Rodriguez, Rambus Inc.; and Justin Endo, Mixel, Inc.
Next-generation display applications have an insatiable appetite for bandwidth. Using a combination of VESA Display Stream Compression (DSC) and MIPI DSI-2℠ technology, designers can achieve display resolutions up to 8K without compromise to video quality, battery life or cost. This presentation discusses a fully integrated, off-the-shelf display IP subsystem solution, consisting of Mixel (MIPI C-PHY℠/D-PHY℠ combo), Rambus (MIPI DSI-2® controller) and Hardent (VESA DSC) IP, that can deliver this state-of-the-art performance in a power-efficient and compact footprint.
Presented by James Goel, MIPI Technical Steering Group chair, and Rick Wietfeldt, Security Working Group co-chair
This session brings you up to speed on all the latest developments within MIPI Automotive SerDes Solutions (MASS) – a framework that provides a full-stack, end-to-end sensor/display-to-ECU solution for autonomous driving and ADAS systems that leverage existing MIPI CSI-2®, DSI-2℠ and VESA eDP/DP protocols running over MIPI A-PHY℠. The presentation also explains how recent developments make it easier for you to integrate MIPI A-PHY into your next automotive E/E architecture and how, through A-PHY's adoption as an IEEE standard, it can be accessed for evaluation without MIPI membership.
In addition, the presenters discuss how recently released MIPI Camera and Display Service Extensions (CSE and DSE) and their associated protocol adaptation layers (PALs) work together to embed functional safety and security enablers natively at the "edge" – ultimately within the sensor, display and ECU components themselves.
Manoj Sharma Tanikella and Amitkumar Shrichand Gound of Synopsy describe various training sequences used in MIPI PHYs to reduce inter-symbol interference.The latest MIPI PHY specifications (M-PHY, D-PHY and C-PHY) introduce training sequences for the equalizer settings to reduce inter-symbol interference: adapt sequence in M-PHY, alternate sequence in D-PHY and C-PHY. In addition, C-PHY uses preamble and user-define sequences.
MIPI DevCon Bangalore 2017: Next generation MIPI Physical Layer Design and Ev...MIPI Alliance
SK Choi of Keysight Technologies covers the new technology innovation brought by MIPI PHY specifications and the new challenges to design or evaluation engineering. In this presentation, he examines the key changes in the specification and CTS (conformance test suite) and addresses the challenges to support the new PHY layer.
MIPI DevCon 2020 | Snapshot of MIPI RFFE v3.0 from a System-Architecture Per...MIPI Alliance
Lalan Mishra, vice-chair of the MIPI RFFE Working Group, presents the new features of MIPI RFFE v3.0 to help architecture and design engineers understand how the triggering features in the latest version work together to improve performance and to switch quickly among the various bands and band combinations in a 5G system.
MIPI DevCon 2020 | Interoperability Challenges and Solutions for MIPI I3CMIPI Alliance
This presentation from Geoffrey Duerden of Introspect Technology features a case study of several specific interoperability challenges and solutions in terms of circuit and layout guidelines, protocol implementations and target applications.
MIPI DevCon Taipei 2019: Addressing 5G RFFE Control Challenges with MIPI RFFE...MIPI Alliance
Andrew Scott-Mackie, RF control systems engineer at Intel Corporation, discusses how MIPI RFFE℠ 3.0 aims to meet the new 5G control timing requirements and adds several enhancements to the RFFE-Trigger specification to meet 5G use cases.
MIPI DevCon 2021: Meeting the Needs of Next-Generation Displays with a High-P...MIPI Alliance
Presented by Alain Legault, Hardent Inc.; Joe Rodriguez, Rambus Inc.; and Justin Endo, Mixel, Inc.
Next-generation display applications have an insatiable appetite for bandwidth. Using a combination of VESA Display Stream Compression (DSC) and MIPI DSI-2℠ technology, designers can achieve display resolutions up to 8K without compromise to video quality, battery life or cost. This presentation discusses a fully integrated, off-the-shelf display IP subsystem solution, consisting of Mixel (MIPI C-PHY℠/D-PHY℠ combo), Rambus (MIPI DSI-2® controller) and Hardent (VESA DSC) IP, that can deliver this state-of-the-art performance in a power-efficient and compact footprint.
Presented by James Goel, MIPI Technical Steering Group chair, and Rick Wietfeldt, Security Working Group co-chair
This session brings you up to speed on all the latest developments within MIPI Automotive SerDes Solutions (MASS) – a framework that provides a full-stack, end-to-end sensor/display-to-ECU solution for autonomous driving and ADAS systems that leverage existing MIPI CSI-2®, DSI-2℠ and VESA eDP/DP protocols running over MIPI A-PHY℠. The presentation also explains how recent developments make it easier for you to integrate MIPI A-PHY into your next automotive E/E architecture and how, through A-PHY's adoption as an IEEE standard, it can be accessed for evaluation without MIPI membership.
In addition, the presenters discuss how recently released MIPI Camera and Display Service Extensions (CSE and DSE) and their associated protocol adaptation layers (PALs) work together to embed functional safety and security enablers natively at the "edge" – ultimately within the sensor, display and ECU components themselves.
MPI DevCon Hsinchu City 2017: Building Intelligent, High-Speed Sensor Connect...MIPI Alliance
MIPI I3C enables multiple sensor connectivity using a single integrated bus with minimal pin count and throughput up to 33 Mbps. This presentation briefly describes I3C and its key features, and through examples details how I3C can be used in IoT and automotive systems to enable a more intelligent sensor connectivity.
Accelerating MIPI Interface Development and Validation - Introspect TechnologyJean-Marc Robillard
Modern MIPI interfaces enable remarkable user experiences through the deployment of highly innovative electrical signaling and protocol technologies. Extending well beyond mobile, these interfaces are finding use in autonomous driving systems, augmented reality systems, and rugged or embedded computing applications. Understanding the various interactions between the multitude of physical and protocol layers is critical to achieving successful design and validation of MIPI links, especially when conceived as part of larger system contexts.
MPI DevCon Hsinchu City 2017: Create Higher Resolution Displays With VESA Dis...MIPI Alliance
Alain Legault of Hardent discusses the challenges of designing products to meet the demands of current and future displays and highlights how DSC compression offers an innovative solution to deal with these challenges.
MIPI DevCon Seoul 2018: MIPI Alliance Meets the Needs of Autonomous DrivingMIPI Alliance
The chair of MIPI's Automotive Working Group, Matt Ronning of Sony Corporation, provides a status update on MIPI's requirements gathering and specification development efforts to support the automotive market.
MPI DevCon Hsinchu City 2017: Mobile Influenced Markets – Evolution of Camera...MIPI Alliance
Tom Watzka of Lattice Semiconductor discusses the evolution of innovative mobile-influenced applications (such as AR/VR and drones), including the unique issues faced by system and software developers.
MIPI DevCon Taipei 2019: An Introduction to MIPI I3C® v1.1 and What's NextMIPI Alliance
Ken Foust, principal engineer at Intel Corporation, focuses on the new features available in MIPI I3C® v1.1 and the efforts MIPI is taking to advance I3C for broad, long-term adoption across multiple industries and usages.
MPI DevCon Hsinchu City 2017: Practical Experiences in MIPI D-PHY & C-PHY Rec...MIPI Alliance
Steven Chiang of Trust-Tek Corporation addresses the challenges implementers face adhering to certain key requirements defined in the specifications, such as receiver stressed eye testing, while operating within contexts that do not warrant a literal interpretation of the methodology described in these specifications. He also offers best practices in test and focuses on contextual requirements and separating component-level testing/characterization needs from system-level ones.
MIPI DevCon 2021: MIPI I3C Signal Integrity Challenges on DDR5-based Server P...MIPI Alliance
Presented by Azusena Lupercio Ramirez, Juan Orozco and Nestor Hernandez Cruz, Intel Corporation
The MIPI I3C® protocol is first used in a server application for the DDR5 DIMM SPD function. MIPI I3C was defined for low capacitance applications, while DDR5 SPD exceeds by far the bus capacitance specification. This presentation covers the interoperability challenges of the dynamic push-pull and open-drain operating modes, on server applications with an in-depth analysis of the implications of long PCB traces, multiple DIMM routing branches, and multiple loads to the electrical and timing parameters.
Presented by Licinio Sousa, Synopsys, Inc., and Edo Cohen, Valens Semiconductor
Synopsys and Valens Semiconductor outline how MIPI automotive solutions can enable safe and robust long-reach connectivity for cameras and sensors. The ability for high volumes of data to travel at a fast rate over a long reach infrastructure is now mandatory in automotive vision applications. In addition, maintaining a reliable link can be the difference between successful operation and system failure in a car. In this presentation, Synopsys and Valens present a Valens MIPI A-PHY℠ design for in-vehicle connectivity using Synopsys’ ISO 26262-ready MIPI CSI-2® and MIPI C-PHY℠/D-PHY℠ IP in the FinFET process to meet their latency and bandwidth requirements. The presentation also previews examples of display applications that can benefit from the same architecture.
This presentation, from Gregor Sievers, Ph.D., of dSPACE GmbH, addresses how the MIPI CSI-2℠, D-PHY℠, CCS, and A-PHY℠ specifications simplify validation and testing and help bring autonomous driving to the streets.
MIPI DevCon 2021: MIPI HTI, PTI and STP: The Bases for Next-Generation Online...MIPI Alliance
Presented by Thomas B. Preußer and Alexander Weiss, Accemic Technologies GmbH
The key challenge for testing and debugging embedded multicore systems is their limited observability. MIPI trace protocols provide essential operational insights non-intrusively, and this presentation advocates for the continuous online analysis of these trace data. It also contrasts the challenges posed by the vigorously compressed MIPI trace protocols with the enormous benefits that can be gained by online processing.
MIPI DevCon 2021: MIPI D-PHY and MIPI CSI-2 for IoT: AI Edge DevicesMIPI Alliance
Presented by Ashraf Takla, Mixel Inc.
This presentation covers the deployment of MIPI D-PHY℠ and MIPI CSI-2® in IoT and edge devices. While many mobile-influenced applications benefit from the low-power, small-form factor of MIPI specifications, AI edge processors in particular are seeing a surge in the use of MIPI specifications for their sensors as market trends shift from processing in the cloud or central location, to processing at the edge.
This presentation includes a high-level system overview of a specific use case, Perceive Ergo edge inference processor, and how Mixel was able to meet Perceive’s stringent requirements with its MIPI D-PHY CSI-2 TX and D-PHY CSI-2 RX IPs.
MIPI DevCon Taipei 2019: New Trends in the High-Volume Manufacturing Test of ...MIPI Alliance
Mohamed Hafed, Ph.D., chief executive officer at Introspect Technology, summarizes the fundamental requirements for quality assurance and testing methods for high-speed interfaces including MIPI D-PHY℠, C-PHY℠ and M-PHY®. The presentation includes practical examples of test cell design, test program development and multi-site screening techniques.
MIPI DevCon 2021: MIPI I3C interface for the ETSI Smart Secure PlatformMIPI Alliance
Presented by Gulio Follero, ETSI
The ETSI Technical Committee Smart Card Platform (TC SCP) is developing the specification of the next generation secure element, the Smart Secure Platform (SSP). SCP is standardizing the MIPI I3C interface for SSP. This presentation describes the SSP architecture and its main use cases, followed by a discussion of how the MIPI I3C interface is adapted to the SSP and the main benefits in terms of speed, power and efficiency.
MIPI DevCon Seoul 2018: Evolving MIPI I3C for New Usages and IndustriesMIPI Alliance
Ken Foust of Intel Corporation focuses on the efforts MIPI is taking to evolve the capabilities and access of I3C℠ to allow broad, long-term adoption across multiple industries and usages.
Radio Frequency Front End (RFFE) MIPI core from Arasan Chip SystemsArasan Chip Systems
The RF Front-End Control Interface (RFFE) was developed to offer a common method for controlling RF front-end devices such as Power Amplifiers, Low-Noise Amplifiers (LNA), filters, switches, power management modules, antenna tuners and sensors that can be controlled using RFFE.
DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112GLeah Wilkinson
DesignCon 2019
112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity
Electrical interfaces at 112 Gbps are a critical enabler of faster, more efficient and cost effective networks and data centers. A panel of OIF contributors will discuss the ongoing CEI-112G electrical interface development projects, and the new architectures they will enable including chiplet packaging, co-packaged optics and internal cable based solutions. The panel will provide an update on the multiple interfaces being defined by the OIF including CEI-112G MCM, XSR, VSR, MR and LR for 112 Gbps applications of die-to-die, chip-to-module, chip-to-chip and long reach over backplane and cables. Listen to thought leaders in the electrical interface industry debate the issues surrounding the CEI-112G projects and the architectures they will enable.
This third webinar discusses the fundamentals of LTE Carriers and how LTE mobiles communicate with the network including what factors affect performance.
MPI DevCon Hsinchu City 2017: MIPI High Speed Serial Technologies: Debug & Co...MIPI Alliance
David Yang of Tektronix covers the three high-speed serial standards: D-PHY, M-PHY and C-PHY, which have similarities in terms of target segment and application use cases, but have wide contrasts with respect to electrical specifications. He discusses real-world problems and the process of uncovering them early on using the test and measurement equipment & solutions. In addition, this session highlights the test solutions needed to support the upcoming revisions of these PHY specifications.
MPI DevCon Hsinchu City 2017: Next generation MIPI Physical Layer Design and ...MIPI Alliance
SK Choi of Keysight Technologies looks at the key changes in the new MIPI C-PHY, MIPI D-PHY and MIPI M-PHY specifications, as well as the CTS (conformance test suite), and addresses the challenges to support the new PHY layer. The new MIPI PHY specifications will bring new technology innovation that will also bring new challenges to design or evaluation engineering.
MPI DevCon Hsinchu City 2017: Building Intelligent, High-Speed Sensor Connect...MIPI Alliance
MIPI I3C enables multiple sensor connectivity using a single integrated bus with minimal pin count and throughput up to 33 Mbps. This presentation briefly describes I3C and its key features, and through examples details how I3C can be used in IoT and automotive systems to enable a more intelligent sensor connectivity.
Accelerating MIPI Interface Development and Validation - Introspect TechnologyJean-Marc Robillard
Modern MIPI interfaces enable remarkable user experiences through the deployment of highly innovative electrical signaling and protocol technologies. Extending well beyond mobile, these interfaces are finding use in autonomous driving systems, augmented reality systems, and rugged or embedded computing applications. Understanding the various interactions between the multitude of physical and protocol layers is critical to achieving successful design and validation of MIPI links, especially when conceived as part of larger system contexts.
MPI DevCon Hsinchu City 2017: Create Higher Resolution Displays With VESA Dis...MIPI Alliance
Alain Legault of Hardent discusses the challenges of designing products to meet the demands of current and future displays and highlights how DSC compression offers an innovative solution to deal with these challenges.
MIPI DevCon Seoul 2018: MIPI Alliance Meets the Needs of Autonomous DrivingMIPI Alliance
The chair of MIPI's Automotive Working Group, Matt Ronning of Sony Corporation, provides a status update on MIPI's requirements gathering and specification development efforts to support the automotive market.
MPI DevCon Hsinchu City 2017: Mobile Influenced Markets – Evolution of Camera...MIPI Alliance
Tom Watzka of Lattice Semiconductor discusses the evolution of innovative mobile-influenced applications (such as AR/VR and drones), including the unique issues faced by system and software developers.
MIPI DevCon Taipei 2019: An Introduction to MIPI I3C® v1.1 and What's NextMIPI Alliance
Ken Foust, principal engineer at Intel Corporation, focuses on the new features available in MIPI I3C® v1.1 and the efforts MIPI is taking to advance I3C for broad, long-term adoption across multiple industries and usages.
MPI DevCon Hsinchu City 2017: Practical Experiences in MIPI D-PHY & C-PHY Rec...MIPI Alliance
Steven Chiang of Trust-Tek Corporation addresses the challenges implementers face adhering to certain key requirements defined in the specifications, such as receiver stressed eye testing, while operating within contexts that do not warrant a literal interpretation of the methodology described in these specifications. He also offers best practices in test and focuses on contextual requirements and separating component-level testing/characterization needs from system-level ones.
MIPI DevCon 2021: MIPI I3C Signal Integrity Challenges on DDR5-based Server P...MIPI Alliance
Presented by Azusena Lupercio Ramirez, Juan Orozco and Nestor Hernandez Cruz, Intel Corporation
The MIPI I3C® protocol is first used in a server application for the DDR5 DIMM SPD function. MIPI I3C was defined for low capacitance applications, while DDR5 SPD exceeds by far the bus capacitance specification. This presentation covers the interoperability challenges of the dynamic push-pull and open-drain operating modes, on server applications with an in-depth analysis of the implications of long PCB traces, multiple DIMM routing branches, and multiple loads to the electrical and timing parameters.
Presented by Licinio Sousa, Synopsys, Inc., and Edo Cohen, Valens Semiconductor
Synopsys and Valens Semiconductor outline how MIPI automotive solutions can enable safe and robust long-reach connectivity for cameras and sensors. The ability for high volumes of data to travel at a fast rate over a long reach infrastructure is now mandatory in automotive vision applications. In addition, maintaining a reliable link can be the difference between successful operation and system failure in a car. In this presentation, Synopsys and Valens present a Valens MIPI A-PHY℠ design for in-vehicle connectivity using Synopsys’ ISO 26262-ready MIPI CSI-2® and MIPI C-PHY℠/D-PHY℠ IP in the FinFET process to meet their latency and bandwidth requirements. The presentation also previews examples of display applications that can benefit from the same architecture.
This presentation, from Gregor Sievers, Ph.D., of dSPACE GmbH, addresses how the MIPI CSI-2℠, D-PHY℠, CCS, and A-PHY℠ specifications simplify validation and testing and help bring autonomous driving to the streets.
MIPI DevCon 2021: MIPI HTI, PTI and STP: The Bases for Next-Generation Online...MIPI Alliance
Presented by Thomas B. Preußer and Alexander Weiss, Accemic Technologies GmbH
The key challenge for testing and debugging embedded multicore systems is their limited observability. MIPI trace protocols provide essential operational insights non-intrusively, and this presentation advocates for the continuous online analysis of these trace data. It also contrasts the challenges posed by the vigorously compressed MIPI trace protocols with the enormous benefits that can be gained by online processing.
MIPI DevCon 2021: MIPI D-PHY and MIPI CSI-2 for IoT: AI Edge DevicesMIPI Alliance
Presented by Ashraf Takla, Mixel Inc.
This presentation covers the deployment of MIPI D-PHY℠ and MIPI CSI-2® in IoT and edge devices. While many mobile-influenced applications benefit from the low-power, small-form factor of MIPI specifications, AI edge processors in particular are seeing a surge in the use of MIPI specifications for their sensors as market trends shift from processing in the cloud or central location, to processing at the edge.
This presentation includes a high-level system overview of a specific use case, Perceive Ergo edge inference processor, and how Mixel was able to meet Perceive’s stringent requirements with its MIPI D-PHY CSI-2 TX and D-PHY CSI-2 RX IPs.
MIPI DevCon Taipei 2019: New Trends in the High-Volume Manufacturing Test of ...MIPI Alliance
Mohamed Hafed, Ph.D., chief executive officer at Introspect Technology, summarizes the fundamental requirements for quality assurance and testing methods for high-speed interfaces including MIPI D-PHY℠, C-PHY℠ and M-PHY®. The presentation includes practical examples of test cell design, test program development and multi-site screening techniques.
MIPI DevCon 2021: MIPI I3C interface for the ETSI Smart Secure PlatformMIPI Alliance
Presented by Gulio Follero, ETSI
The ETSI Technical Committee Smart Card Platform (TC SCP) is developing the specification of the next generation secure element, the Smart Secure Platform (SSP). SCP is standardizing the MIPI I3C interface for SSP. This presentation describes the SSP architecture and its main use cases, followed by a discussion of how the MIPI I3C interface is adapted to the SSP and the main benefits in terms of speed, power and efficiency.
MIPI DevCon Seoul 2018: Evolving MIPI I3C for New Usages and IndustriesMIPI Alliance
Ken Foust of Intel Corporation focuses on the efforts MIPI is taking to evolve the capabilities and access of I3C℠ to allow broad, long-term adoption across multiple industries and usages.
Radio Frequency Front End (RFFE) MIPI core from Arasan Chip SystemsArasan Chip Systems
The RF Front-End Control Interface (RFFE) was developed to offer a common method for controlling RF front-end devices such as Power Amplifiers, Low-Noise Amplifiers (LNA), filters, switches, power management modules, antenna tuners and sensors that can be controlled using RFFE.
DesignCon 2019 112-Gbps Electrical Interfaces: An OIF Update on CEI-112GLeah Wilkinson
DesignCon 2019
112-Gbps Electrical Interfaces: An OIF Update on CEI-112G
Brian Holden, Kandou Bus
Cathy Liu, Broadcom
Steve Sekel, Keysight
Nathan Tracy, TE Connectivity
Electrical interfaces at 112 Gbps are a critical enabler of faster, more efficient and cost effective networks and data centers. A panel of OIF contributors will discuss the ongoing CEI-112G electrical interface development projects, and the new architectures they will enable including chiplet packaging, co-packaged optics and internal cable based solutions. The panel will provide an update on the multiple interfaces being defined by the OIF including CEI-112G MCM, XSR, VSR, MR and LR for 112 Gbps applications of die-to-die, chip-to-module, chip-to-chip and long reach over backplane and cables. Listen to thought leaders in the electrical interface industry debate the issues surrounding the CEI-112G projects and the architectures they will enable.
This third webinar discusses the fundamentals of LTE Carriers and how LTE mobiles communicate with the network including what factors affect performance.
MPI DevCon Hsinchu City 2017: MIPI High Speed Serial Technologies: Debug & Co...MIPI Alliance
David Yang of Tektronix covers the three high-speed serial standards: D-PHY, M-PHY and C-PHY, which have similarities in terms of target segment and application use cases, but have wide contrasts with respect to electrical specifications. He discusses real-world problems and the process of uncovering them early on using the test and measurement equipment & solutions. In addition, this session highlights the test solutions needed to support the upcoming revisions of these PHY specifications.
MPI DevCon Hsinchu City 2017: Next generation MIPI Physical Layer Design and ...MIPI Alliance
SK Choi of Keysight Technologies looks at the key changes in the new MIPI C-PHY, MIPI D-PHY and MIPI M-PHY specifications, as well as the CTS (conformance test suite), and addresses the challenges to support the new PHY layer. The new MIPI PHY specifications will bring new technology innovation that will also bring new challenges to design or evaluation engineering.
MIPI DevCon 2016: Testing of MIPI High Speed PHY Standard ImplementationsMIPI Alliance
Interoperability in mobile devices shall be achieved through a variety of protocol standards such as MIPI CSI, DSI, UniPro or JEDEC UFS and their underlying physical layer standards MIPI M-PHY, D-PHY or C-PHY. Integration of different vendors' designs into a working system is simplified using standard conformant parts. Testing them according to the procedures outlined in the applicable Conformance Test Suite guarantees their conformance. However, increasing data rates, lower power dissipation and modularity of mobile devices create challenges for debugging and conformance verification of the affected components. In this presentation, Joel Birch of Keysight Technologies discusses these challenges and offers possible solutions to address them.
Practical Experiences in MIPI D-PHY and C-PHY Receiver TestingJean-Marc Robillard
This presentation from the MIPI Alliance DevCon 2017 event in Hsinchu City, Taiwan, covers the following topics:
- Overview of receiver test
- Illustration of practical module implementations and
evaluation platforms
- Recommendations and best practices
MIPI DevCon Taipei 2019: PHY Testing Challenges and Opportunities: The Need F...MIPI Alliance
Victor Sanchez-Rico, project manager MIPI at BitifEye Digital Test Solutions GmbH, highlights the challenges observed and the lessons learned from BitifEye's experience with testing of high-speed digital interconnect busses, with a focus on the complex high-speed electrical PHY layer receiver conformance tests.
MIPI DevCon Bangalore 2017: Enabling Higher Data Rates and Variety of Channel...MIPI Alliance
Raj Kumar Nagpal of Synopsys provides a brief roadmap of the D-PHY specification, including its flexibility, speed, power and cost benefits for cameras and displays in mobile applications. The presentation illustrates common use cases, and details how MIPI D-PHY can operate at 2.5 Mbps over multiple lanes to enable higher performance.
MIPI DevCon 2020 | MIPI A-PHY: Laying the Groundwork for MIPI’s Automotive Se...MIPI Alliance
MIPI board member Ariel Lasry and A-PHY subgroup vice lead Edo Cohen share technical details of MIPI A-PHY, the cornerstone of MIPI Automotive SerDes Solutions (MASS).
MPI DevCon Hsinchu City 2017: Enabling Higher Data Rates and Variety of Chann...MIPI Alliance
Hezi Saar of Synopsys describes MIPI D-PHY’s flexibility, speed, power and cost benefits for cameras and displays in mobile applications. The presentation illustrates common use cases, and details how MIPI D-PHY can operate at 2.5 Mbps over multiple lanes to enable higher performance. The presentation also gives a brief roadmap of the D-PHY specification.
The goal of this presentation is to understand how to identify the greatest vendor-related risks for an AMI deployment, understand who the stakeholders are for an AMI roll out, and to review and discuss examples of risk mitigation.
MIPI DevCon Seoul 2018: Troubleshooting MIPI M-PHY Link and Protocol IssuesMIPI Alliance
Gordon Getty and Juhyun Yang, both of Teledyne LeCroy, discuss how higher-layer protocols, including UniPro® and UFS, use MIPI M-PHY® to provide an efficient, low-power storage protocol to be enabled on mobile platforms.
Arrow Devices MIPI MPHY Verification IP SolutionArrow Devices
“Easy to Use”
“Catches tricky corner cases”
“Provides complete comprehensive test coverage”
These are some of the things being said by our customers about our MIPI MPHY Verification IP Solution.
Our MIPI MPHY Verification IP Solution has been adopted by many top SoC/IP companies. In the coming slides, we talk about the major aspects of our mature MIPI MPHY Verification Solution.
MIPI DevCon Seoul 2018: Dual Mode C-PHY/D-PHY Use in VR Display IC MIPI Alliance
This co-presentation from Ahmed Ella of Mixel, Inc., and Jeffrey Lukanc of Synaptics, will cover Synaptics VXR7200 DisplayPort to Dual MIPI VR Bridge IC, integrating a Mixel C-PHY℠/D-PHY℠ Combo IP and controller.
Adoption of MIPI standards is accelerating, making design verification and interoperability critically important. In this presentation, Ross Nelson of Protocol Insight discusses effective verification processes to test the physical, link and application layers and the complete system, focusing on debug, stress/corner case testing and conformance/interoperability verification. This presentation also covers effective verification processes and the new MIPI Product Registry model.
Overcoming challenges of_verifying complex mixed signal designsPankaj Singh
Efficient and Innovative Digital Mixed-Signal (DMS) verification methodology is required to enable effective verification of RX path of SERDES. This presentation describes the usage of Real value models and Capture -Verify approach to verify complex high speed mixed signal design.
Real value models are the backbone of DMS methodology. Real value models are created for all critical modules in Receive path like Equalizer and Sampler and its associated peripheral modules. It is critical to make sure created models are functionally equivalent to respective designs. This is achieved by verifying each created model with respective designs for all functional modes. While the Real Value models are effective in meeting overcoming the simulation performance bottleneck by achieving 10x faster simulation time; the Nonlinearity factors of the front-end design are not represented accurately in discrete domain real value models for next generation of SerDes Design at very high data rate.
To overcome this problem, a novel approach called ‘capture and verify’ is used for verifying the jitter tolerance and eye parameters. In this approach, waveforms from spice level verification of Equalizer for different functional modes are captured and stored. These stored waveforms are used to generate run time table-based models to accurately represent the analog modules. These run time models are used in top-level simulations along with real value models thereby achieving required goal of simulation performance without compromising on accuracy of results.
The complete Design Verification (DV) environment is developed using UVM-e Methodology. Verification environment contains model for transmitter with all de-emphasis settings along with protocol compliant channels with multiple attenuations. DV infrastructure has hooks to plug-in required channel models to verify SERDES. This verification environment is also capable of verifying the clock data recovery (CDR) path of the design using protocol compliant jitter and Spread-Spectrum Clocking (SSC) stimulus.
The real value modelling bridges the gap between the performance requirements of the simulation and accuracy limitations of design. A significant speed-up in simulation performance is achieved (almost 10X in this case) by replacing with functionally equivalent real value models for mixed signal designs. Usage of Capture and Verify methodology with spice simulation waveforms for critical blocks ensures non-linearity of the next generation high speed SerDes design is well captured in simulations provide complete comprehensive solution for high speed mixed signal designs.
MIPI DevCon Seoul 2018: Powering AI and Automotive Applications with the MIPI...MIPI Alliance
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MIPI DevCon Bangalore 2017: MIPI High Speed Serial Technologies: Debug & Conformance Testing Challenges and Solutions
1. MIPI High Speed Serial Technologies:
Debug & Conformance Testing
Challenges and Solutions
Ramesh P.E, Principal Engineer
&
Parthasarathy Raju, System Engineer
Tektronix