1. MINH NGUYEN
8404 Summerdale Rd, #A
San Diego, CA 92126
(858) 610-3980
m2jati@gmail.com
STAFF ENGINEER with over twenty years of experience. In-depth understanding of
ASIC/SOC/Mixed Signal design flows including all aspects of Floor planning, Synthesis, Placement and
Routing, Scan implementation, Clock Tree Synthesis, Parasitic Extraction, Static Timing Analysis, Logic
Equivalence Checking, DRC/LVS, DFM. Proven high quality technical support and hands-on experience
from gate level netlist to tape out without error. Led and managed complex tasks to achieve ultimate
goals consistent with timely program schedules and cost constraints. Self-starter, highly motivated, and
work well within team environment. Maximized two-year contract without any complaint. Successfully
delivered methodology flows and received the highest customer satisfaction score. Won contract over
competitors for understood customer expectations and requirements. Fostered management trust to take
on more challenging assignments. Facilitated customer relationships to successfully drive multi-million
gate designs to tape out.
Skills:
• EDA Tools:
Cadence: EDI, ETS, SOCE, First Encounter, NanoRoute, Wroute, QRC, CTGen, Silicon Ensemble,
Design Planer, Assura, Celtic, Vituoso, and Conformal
Others: ICC, Primetime, StarRC, Calibre, NEC Galet (NEC in-house tool).
• Worked with 10nm, 14nm, 20nm, 28nm, 32 nm, 45nm, 65nm processes.
• Programming Languages: Tcl and Perl.
• OS: UNIX, Linux, DOS, Windows, and Macintosh.
• Proficient with Microsoft Office, especially excel.
• Strong skills with standard PM process and tools.
STRENGTHS
• Identified chronic issue and presented plan to successfully mitigate it.
• Set expectations with customers to achieve ultimate goal of on-time deliveries for all projects.
• Drives and maintains schedules and plans for execution of development plans of record for a fast
paces innovative environment
• Enjoy the challenge of new projects and handling several responsibilities at once.
• Demonstrated excellent skills and knowledge in diagnosing problems and offered viable solutions.
• Experienced with identifying and solving complex problems.
• Learned new systems quickly, take initiative, and committed to delivering top quality service.
• Enthusiastic, conscientious individual who enjoy innovative problem solving techniques.
• Developed innovative solutions to make an impact to the company’s productivity and effectiveness.
• Quickly adapted to various physical environments such as, TI, NEC Electronics, ATI, Teradyne, ST
Microelectronics, AMD, and QCOM.
EMPLOYMENT HISTORY
Project Engineer 03/2013 – present

2. MINH NGUYEN
•Tracking record of ownership/leadership/accountability and hold others accountable for their
deliverables to the program while maintaining a collaborative team environment.
•Cooperating with our regional tech support and engineering teams for supporting resource planning,
scheduled delivery, and project prioritization
•Coordinating and partnering across all relevant program management and engineering groups to ensure
approved features and on-time deliveries.
•Managing and tracking portfolios of technology and library usage for every on-going projects
•Collecting and collaborating regional information to manage complex-cross functional programs across
multiple entities and geographies.
•Setting POR, planning resources, and mitigating technical risks with IP teams to ensure on-time
deliveries.
•Communicating project status, issues, and recommended mitigation plans to core cross-functional
groups and executives.
Physical Design Contractor 02/2010 – 03/2013
• Contracted for Qualcomm, AMD, St Microelectronics, and Teradyne.
• Successfully taped out several designs of various complexities and processes within schedule.
• Solved severe Signal Integrity (SI) issues that prevented design closure.
• Inspired customer trust to receive more challenging assignments from hierachial block to chip
level.
• Be productive while quickly mastered customers’ custom reference flows.
• Refined customers’ custom flows with EDA flows to be more effecient.
• Analyzed errors and diagnosed scripts to find root caused.
• Developed scripts to customize reports and assisted block owners as requested by management.
• Interfaced with Bangalore Design Center engineers to meet schedule milestone.
• Collaborated with top-level designers to resolve IR issues.
• Executed all aspects Redhawk analysis for 28nm heirachial block.
• Earned management trust to lead Redhawk analysis for 20nm top-level chip.
• Implemented all aspects of physical design for 28nm process from rtl netlist to gds using
Synopsys and Cadence tools.
• Solved clock gating that prevented tree balancing to close timing.
• Floorplaned for block with over 400 rams using 40 nm process.
• Assured management confident to implement top level pin assignment.
• Communicated with customers to understand issues and expectations.
• Developed new scripts to account for feed through wires with metal fill.
• Incorporated new developed scripts into the existing flow to meet tape out schedule.
• Developed new physical design methodology to utilize new features of EDI for the next revision
of the chip.
• Received great appreciation from customer for outstanding performance
• Safeguarded intellectual property of both parties.
• Communicated project status and coordinated activities to resolve bottle-neck issues.
• Enhanced effective methodology in accordance to client’s specific designs.
TEXAS INSTRUMENTS, INC., Dallas, TX 08/2006 – 11/2009
Physical Design Engineer
• Diligently communicated with designers to prevent issues and close timing with Primetime.
• Successfully taped out several designs of various complexities within schedule.

3. MINH NGUYEN
• Self-learned Assura and developed VDIO-Assura flow.
• Diagnosed/troubleshot libraries and tools issues to achieve desired results.
• Designed a web page and FAQ to assist HPA/HVAL users with VDIO flow.
• Be a focal point for team members to seek help with VDIO.
• Using knowledge and experience to assist co-worker solving VDIO issues and become more
effective with the tool.
• Followed up and ensured all customers’ issues addressed and properly resolved.
• Identified and immediately resolved customers' problems within 24 hours.
• Proactively solved chronic issues lingered for years within a few weeks.
SYNAPSE DESIGN AUTOMATION, INC., San Jose, CA 12/2004 – 2/2006
Physical Design Engineer
• Worked on low power 90 nm processes with over 1 million placed instances using both
Synopsys and Cadence tools as well as COT.
• Analyzed Primetime reports and used customer in-house syntax/scripts to write physical eco files
to fix setup/hold, data/clock slow nodes, and celtic violations.
• Took gate level netlist, completed all tasks from floorplanning to GDSII. This includes:
floorplan, placement, clock-tree synthesis, scan chain, detail route, RC extraction, signal
integrity, equivalent check, drc, lvs, eco.
• Performed tape out checks for quality assurance.
• Troubleshot customer’s complex flow to execute the methodology and achieve the desired
results.
CADENCE DESIGN SYSTEMS, INC., San Jose, CA 02/1997 – 09/2003
Lead Services Consultant Engineer
• Floor planned, placed and routed several designs for different customers from flat to hierarchical.
• Diagnosed/troubleshot libraries and tools issues to achieve desired results.
• Integrated and assembled full chip along with power and timing budgeting.
• Prioritized and multiplexed several customer situations.
• Worked with various logic design teams on synthesis/scan issues on high speed, deep sub-micron
designs and provided constructive feedback.
• Trained customers' engineers to be more proficient with Cadence tools.
NEC ELECTRONICS INC., Santa Clara, CA 02/1994 – 02/1997
Technical Application Engineer, EDA Group
• Debugged problems within tight schedule.
• Interfaced with engineers to achieve timing convergence.
• Developed scripts to assist front-end engineers using physical design tools.
• Explained technical issues in plain English to other engineers and senior managements.
• Evaluated tools and presented the results to managers and users.
• Floor planed, placed and routed several designs from gate arrays to cell based designs using
Cadence and Galet tool sets.
EDUCATION
B.S., Computer Science, California State University Hayward, Hayward, CA, 1994

4. MINH NGUYEN
Continuing education on technology through combination of courses and researches.