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Tech talk with Antmicro - Building an open source system verilog ecosystem

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RISC-V International
RISC-V International

This document discusses building an open source SystemVerilog ecosystem. It outlines Antmicro's work in tools, hardware, software and AI for the RISC-V ecosystem. It describes the need for open source SystemVerilog support in tools to enable collaborative design. Efforts discussed include developing an SV compliance test suite, the open source Verible linter/formatter, the Surelog parser, and integrating the Universal Hardware Data Model interface in other tools like Verilator and Yosys. The goal is to extend open source tools with SV features and create reusable solutions.

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Building an open source SystemVerilog ecosystem RISC-V Summit 2020, Online, 2020-12-08 Karol Gugala, kgugala@antmicro.com
OUR WORK IN THE RISC-V ECOSYSTEM SOFTWARE & AI OS porting, building BSPs, build systems, device management, edge & cloud AI FPGA & ASIC Custom IP blocks, SiP development, soft SoCs, heterogeneous processing systems TOOLS Tools, new software and hardware development and testing methodologies HARDWARE Proof of Concepts (PoC), demonstrators, prototyping, open source platforms Building an open source SystemVerilog ecosystem
Building an open source SystemVerilog ecosystem • Proprietary licensing of existing tools makes it hard to build scalable, reproducible CIs ▫ Especially publicly accessible CIs in multi-org projects - OpenTitan, CHIPS Alliance • Number of open source RISC-V cores and lots of pre-existing IP implemented in SystemVerilog, e.g. ▫ SweRV ▫ Ibex • Open source tools will help building collaborative ecosystem around ASIC and FPGA design ▫ Open source design verification (e.g. riscv-dv) can enable creating well tested, good quality open source designs WHY DO WE NEED SYSTEMVERILOG SUPPORT IN OPEN SOURCE TOOLS?
• Identify missing functionalities and features • Reuse existing solutions ▫ There already are many existing projects which can be improved • Create well documented and transparent projects ▫ Include automated tests and status reporting in projects • Cooperate with others ▫ Gather information on what is needed HOW TO BUILD AN OPEN SOURCE SYSTEMVERILOG ECOSYSTEM Building an open source SystemVerilog ecosystem
• Syntax support in parsers ▫ Relatively straightforward to implement ▫ There is a number of open source parsers supporting SV spec • Tools functionalities required to handle SV features ▫ Constrained random ▫ Classes support ▫ Scheduler WHAT DOES SYSTEMVERILOG SUPPORT IN TOOLS MEAN? Building an open source SystemVerilog ecosystem
• Available on GitHub github.com/symbiflow/sv-tests • Used to identify SystemVerilog support level in open source tools • Results are presented on auto generated webpage symbiflow.github.io/sv-tests/ SYSTEMVERILOG COMPLIANCE SUITE Building an open source SystemVerilog ecosystem
• Runs number of tests against many tools • Tests cover unit tests checking single SV feature up to complex designs • Dedicated tests for different tools classes (simulators, parsers, synthesis tools etc) SYSTEMVERILOG COMPLIANCE SUITE Building an open source SystemVerilog ecosystem
• Released by Google on GitHub: github.com/google/verible • Actively developed by Google and Antmicro • Provides lintining and formatting functionalities ▫ Used e.g. in Ibex CI • Kythe subproject can be used to index a SystemVerilog project and generate an interactive viewer VERIBLE - OPEN SOURCE LINTER/FORMATTER Building an open source SystemVerilog ecosystem
• Surelog is an open source SystemVerilog 2017 Pre-processor, Parser, Elaborator and UHDM Compiler • Available on GitHub github.com/alainmarcel/Surelog • Universal Hardware Data Model UHDM is used to exchange the information about elaborated SV design between the parser and other tool • Available on GitHub github.com/alainmarcel/UHDM • More on Surelog/UHDM in WOSET 2020 talk: woset-workshop.github.io/WOSET2020.html#article-10 SURELOG/UHDM Building an open source SystemVerilog ecosystem
• Ongoing work on integrating UHDM interface in Verilator and Yosys • 2020 goal is to be able to synthesize Ibex directly from SystemVerilog in UHDM+Yosys (we demonstrated this with pure Yosys earlier this year) • Code is available on GitHub github.com/alainmarcel/uhdm-integration UHDM INTEGRATION Building an open source SystemVerilog ecosystem
libuhdm UNIVERSAL HARDWARE DATA MODEL SystemVerilog design Surelog Design expressed in UHDM Yosys (ASIC/FPGA) Verible? Another parser? Verilator Another tool? libuhdm Building an open source SystemVerilog ecosystem
Ongoing work on extending Verilator with SystemVerilog features required by UVM: • Stratified scheduler • Randomize methods • Class support OPEN SOURCE UVM Building an open source SystemVerilog ecosystem
• Testing the completeness with SystemVerilog test suite github.com/SymbiFlow/sv-tests • Extending the existing open source tools with functionalities required by our partners • Creating reusable and scalable solutions github.com/alainmarcel/uhdm-integration HOW ANTMICRO HELPS BUILDING OPEN SYSTEMVERILOG ECOSYSTEM Building an open source SystemVerilog ecosystem
WE CAN HELP YOU Building an open source SystemVerilog ecosystem Reach out at contact@antmicro.com if you think we could help you improve your ASIC/FPGA design flow or if you want to collaborate.
THANK YOU FOR YOUR ATTENTION!

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Tech talk with Antmicro - Building an open source system verilog ecosystem

  • 1. Building an open source SystemVerilog ecosystem RISC-V Summit 2020, Online, 2020-12-08 Karol Gugala, kgugala@antmicro.com
  • 2. OUR WORK IN THE RISC-V ECOSYSTEM SOFTWARE & AI OS porting, building BSPs, build systems, device management, edge & cloud AI FPGA & ASIC Custom IP blocks, SiP development, soft SoCs, heterogeneous processing systems TOOLS Tools, new software and hardware development and testing methodologies HARDWARE Proof of Concepts (PoC), demonstrators, prototyping, open source platforms Building an open source SystemVerilog ecosystem
  • 3. Building an open source SystemVerilog ecosystem • Proprietary licensing of existing tools makes it hard to build scalable, reproducible CIs ▫ Especially publicly accessible CIs in multi-org projects - OpenTitan, CHIPS Alliance • Number of open source RISC-V cores and lots of pre-existing IP implemented in SystemVerilog, e.g. ▫ SweRV ▫ Ibex • Open source tools will help building collaborative ecosystem around ASIC and FPGA design ▫ Open source design verification (e.g. riscv-dv) can enable creating well tested, good quality open source designs WHY DO WE NEED SYSTEMVERILOG SUPPORT IN OPEN SOURCE TOOLS?
  • 4. • Identify missing functionalities and features • Reuse existing solutions ▫ There already are many existing projects which can be improved • Create well documented and transparent projects ▫ Include automated tests and status reporting in projects • Cooperate with others ▫ Gather information on what is needed HOW TO BUILD AN OPEN SOURCE SYSTEMVERILOG ECOSYSTEM Building an open source SystemVerilog ecosystem
  • 5. • Syntax support in parsers ▫ Relatively straightforward to implement ▫ There is a number of open source parsers supporting SV spec • Tools functionalities required to handle SV features ▫ Constrained random ▫ Classes support ▫ Scheduler WHAT DOES SYSTEMVERILOG SUPPORT IN TOOLS MEAN? Building an open source SystemVerilog ecosystem
  • 6. • Available on GitHub github.com/symbiflow/sv-tests • Used to identify SystemVerilog support level in open source tools • Results are presented on auto generated webpage symbiflow.github.io/sv-tests/ SYSTEMVERILOG COMPLIANCE SUITE Building an open source SystemVerilog ecosystem
  • 7. • Runs number of tests against many tools • Tests cover unit tests checking single SV feature up to complex designs • Dedicated tests for different tools classes (simulators, parsers, synthesis tools etc) SYSTEMVERILOG COMPLIANCE SUITE Building an open source SystemVerilog ecosystem
  • 8. • Released by Google on GitHub: github.com/google/verible • Actively developed by Google and Antmicro • Provides lintining and formatting functionalities ▫ Used e.g. in Ibex CI • Kythe subproject can be used to index a SystemVerilog project and generate an interactive viewer VERIBLE - OPEN SOURCE LINTER/FORMATTER Building an open source SystemVerilog ecosystem
  • 9. • Surelog is an open source SystemVerilog 2017 Pre-processor, Parser, Elaborator and UHDM Compiler • Available on GitHub github.com/alainmarcel/Surelog • Universal Hardware Data Model UHDM is used to exchange the information about elaborated SV design between the parser and other tool • Available on GitHub github.com/alainmarcel/UHDM • More on Surelog/UHDM in WOSET 2020 talk: woset-workshop.github.io/WOSET2020.html#article-10 SURELOG/UHDM Building an open source SystemVerilog ecosystem
  • 10. • Ongoing work on integrating UHDM interface in Verilator and Yosys • 2020 goal is to be able to synthesize Ibex directly from SystemVerilog in UHDM+Yosys (we demonstrated this with pure Yosys earlier this year) • Code is available on GitHub github.com/alainmarcel/uhdm-integration UHDM INTEGRATION Building an open source SystemVerilog ecosystem
  • 11. libuhdm UNIVERSAL HARDWARE DATA MODEL SystemVerilog design Surelog Design expressed in UHDM Yosys (ASIC/FPGA) Verible? Another parser? Verilator Another tool? libuhdm Building an open source SystemVerilog ecosystem
  • 12. Ongoing work on extending Verilator with SystemVerilog features required by UVM: • Stratified scheduler • Randomize methods • Class support OPEN SOURCE UVM Building an open source SystemVerilog ecosystem
  • 13. • Testing the completeness with SystemVerilog test suite github.com/SymbiFlow/sv-tests • Extending the existing open source tools with functionalities required by our partners • Creating reusable and scalable solutions github.com/alainmarcel/uhdm-integration HOW ANTMICRO HELPS BUILDING OPEN SYSTEMVERILOG ECOSYSTEM Building an open source SystemVerilog ecosystem
  • 14. WE CAN HELP YOU Building an open source SystemVerilog ecosystem Reach out at contact@antmicro.com if you think we could help you improve your ASIC/FPGA design flow or if you want to collaborate.
  • 15. THANK YOU FOR YOUR ATTENTION!