Memory Mapping Implementation (mmap) in Linux KernelAdrian Huang
Note: When you view the the slide deck via web browser, the screenshots may be blurred. You can download and view them offline (Screenshots are clear).
Viller Hsiao presents information on Linux vsyscall and vDSO. vDSO (virtual dynamic shared object) is mapped into userspace and contains implementations of common system calls to make them faster. It gets benefits from ASLR and allows additional system calls compared to the older vsyscall method. The kernel generates the vDSO shared object which is then loaded and accessed by the glibc dynamic linker to provide optimized system call implementations to applications.
The document provides an overview of the ARM instruction set architecture, including details about ARM versions, assembly language, programming model, data types, instructions, flow of control, and subroutine calling conventions. It describes the RISC-based load/store design of ARM, how most instructions execute in a single cycle, and that instructions can be conditionally executed. Examples are provided of common operations like assignments, if/else statements, and for loops in ARM assembly language.
In-memory OLTP storage with persistence and transaction supportAlexander Korotkov
Nowadays it becomes evident that single storage engine can't be "one size fits all". PostgreSQL community starts its movement towards pluggable storages. Significant restriction which is imposed in the current approach is compatibility. We consider pluggable storages to be compatible with (at least some) existing index access methods. That means we've long way to go, because we have to extend our index AMs before we can add corresponding features in the pluggable storages themselves.
In this talk we would like look this problem from another angle, and see what can we achieve if we try to make storage completely from scratch (using FDW interface for prototyping). Thus, we would show you a prototype of in-memory OLTP storage with transaction support and snapshot isolation. Internally it's implemented as index-organized table (B-tree) with undo log and optional persistence. That means it's quite different from what we have in PostgreSQL now.
The proved by benchmarks advantages of this in-memory storage are: better multicore scalability (thanks to no buffer manager), reduced bloat (thanks to undo log) and optimized IO (thank to logical WAL logging).
The document discusses stack data structures and their implementation in CPU organization. It describes stacks as last-in, first-out (LIFO) data structures that support two main operations: push and pop. It then covers register and memory-based stack implementations, including the use of stack pointers, data registers, and algorithms for push and pop in each case. The key difference is that register stacks grow with increasing addresses while memory stacks grow with decreasing addresses. The document concludes with an example of how stacks are used to evaluate arithmetic expressions by operating on the top two elements of the stack.
Memory Mapping Implementation (mmap) in Linux KernelAdrian Huang
Note: When you view the the slide deck via web browser, the screenshots may be blurred. You can download and view them offline (Screenshots are clear).
Viller Hsiao presents information on Linux vsyscall and vDSO. vDSO (virtual dynamic shared object) is mapped into userspace and contains implementations of common system calls to make them faster. It gets benefits from ASLR and allows additional system calls compared to the older vsyscall method. The kernel generates the vDSO shared object which is then loaded and accessed by the glibc dynamic linker to provide optimized system call implementations to applications.
The document provides an overview of the ARM instruction set architecture, including details about ARM versions, assembly language, programming model, data types, instructions, flow of control, and subroutine calling conventions. It describes the RISC-based load/store design of ARM, how most instructions execute in a single cycle, and that instructions can be conditionally executed. Examples are provided of common operations like assignments, if/else statements, and for loops in ARM assembly language.
In-memory OLTP storage with persistence and transaction supportAlexander Korotkov
Nowadays it becomes evident that single storage engine can't be "one size fits all". PostgreSQL community starts its movement towards pluggable storages. Significant restriction which is imposed in the current approach is compatibility. We consider pluggable storages to be compatible with (at least some) existing index access methods. That means we've long way to go, because we have to extend our index AMs before we can add corresponding features in the pluggable storages themselves.
In this talk we would like look this problem from another angle, and see what can we achieve if we try to make storage completely from scratch (using FDW interface for prototyping). Thus, we would show you a prototype of in-memory OLTP storage with transaction support and snapshot isolation. Internally it's implemented as index-organized table (B-tree) with undo log and optional persistence. That means it's quite different from what we have in PostgreSQL now.
The proved by benchmarks advantages of this in-memory storage are: better multicore scalability (thanks to no buffer manager), reduced bloat (thanks to undo log) and optimized IO (thank to logical WAL logging).
The document discusses stack data structures and their implementation in CPU organization. It describes stacks as last-in, first-out (LIFO) data structures that support two main operations: push and pop. It then covers register and memory-based stack implementations, including the use of stack pointers, data registers, and algorithms for push and pop in each case. The key difference is that register stacks grow with increasing addresses while memory stacks grow with decreasing addresses. The document concludes with an example of how stacks are used to evaluate arithmetic expressions by operating on the top two elements of the stack.
Linux Binary Exploitation - Return-oritend ProgramingAngel Boy
The document discusses using return-oriented programming (ROP) to bypass address space layout randomization (ASLR) and data execution prevention (DEP). It describes using the procedure linkage table (PLT) to leak the address of functions like puts to bypass ASLR. A ROP chain is then constructed to call read to read "/bin/sh" into memory and execute it, achieving arbitrary code execution.
This document provides an outline for a course on 8086 Assembly Language Programming. It begins with an introduction to machine language and assembly language. It then covers topics like the organization of the 8086 processor, assembly language syntax, data representation, variables, instruction types, memory segmentation, program structure, addressing modes, and input/output. The document is intended to guide students through the key concepts needed to program in 8086 assembly language.
GNU Toolchain is the de facto standard of IT industrial and has been improved by comprehensive open source contributions. In this session, it is expected to cover the mechanism of compiler driver, system interaction (take GNU/Linux for example), linker, C runtime library, and the related dynamic linker. Instead of analyzing the system design, the session is use case driven and illustrated progressively.
Tracing MariaDB server with bpftrace - MariaDB Server Fest 2021Valeriy Kravchuk
Bpftrace is a relatively new eBPF-based open source tracer for modern Linux versions (kernels 5.x.y) that is useful for analyzing production performance problems and troubleshooting software. Basic usage of the tool, as well as bpftrace one liners and advanced scripts useful for MariaDB DBAs are presented. Problems of MariaDB Server dynamic tracing with bpftrace and some possible solutions and alternative tracing tools are discussed.
1) Verified boot is the process of assuring users of the integrity of software running on a device by reducing risks from malware and preventing rollbacks to vulnerable past versions. It uses hashing, public key cryptography, and tamper-evident storage.
2) Android Verified Boot 2.0 (AVB) is Google's recommended method for verified boot integration. It uses a signed VBMeta structure containing hashes, hashtrees and rollback indexes to verify the integrity of partitions before booting.
3) AVB supports features like A/B partitions, locked/unlocked device states, and delegates verification authority through chained partitions. It interacts with bootloaders, uses avbtool to generate signatures,
The document discusses assembly language programming concepts including the stack segment, stack, stack instructions, subroutines, macros, and recursive procedures. It provides examples and explanations of these concepts. It also includes sample programs and solutions related to stacks, subroutines, and other assembly language topics.
The document summarizes the general purpose registers on the x86 architecture. It describes the common uses of registers like EAX, EBX, ECX, EDX, ESI, EDI, and EBP. It also covers special purpose registers like EIP and flags. Additionally, it provides an overview of the stack and how it is used to store function parameters, local variables, and return addresses. Finally, it discusses some simple instructions for math, logic, jumping, strings, and manipulating the stack.
Ramon Fried covers the following topics:
* What DMA is.
* DMA Buffer Allocations and Management.
* Cache Coherency.
* PCI and DMA.
* dmaengine Framework.
Ramon is an Embedded Linux team leader in TandemG, leading various cutting edge projects in the Linux kernel.
He has years of experience in embedded systems, operating systems and Linux kernel.
1. The document discusses Linux kernel page reclamation.
2. Direct reclaim is when the caller performs reclamation directly, while daemon reclaim uses kswapd processes.
3. Daemon reclaim involves kswapd processes waking up and using kswapd_shrink_zone() to reclaim pages until all zones are above the high watermark. This helps balance memory usage across zones.
Master Canary Forging by Yuki Koike - CODE BLUE 2015CODE BLUE
Stack Smashing Protection(SSP) is one of the oldest and fundamental protections against exploits, and is now supported by most compilers and modern operating systems.
One technique for SSP is using stack canaries, which verify if a stack buffer has been overflown by checking the integrity of a value stored immediately after the buffer.
Previously, the main methods to bypass stack canaries were to exploit different vulnerabilities to either avoid the canary validation completely, or to provide the correct canary value by leaking the value.
In this talk I will propose a new technique to bypass stack canaries in SSP which takes a different approach from the previous two methods.
Linux Kernel Booting Process (1) - For NLKBshimosawa
Describes the bootstrapping part in Linux and some related technologies.
This is the part one of the slides, and the succeeding slides will contain the errata for this slide.
The document discusses using the PERFORMANCE_SCHEMA in MySQL 5.6 to analyze and troubleshoot performance issues. It provides an overview of the PERFORMANCE_SCHEMA, how to configure what is instrumented and collected, and examples of using it to find bottlenecks like long wait times on InnoDB mutexes. The PERFORMANCE_SCHEMA provides visibility into where time is spent and which resources are most used through its set of in-memory tables.
The document discusses the IA-64 architecture, which was jointly developed by Intel and HP as a 64-bit architecture intended for implementation on EPIC processors like Itanium. Some key points:
- IA-64 uses explicit instruction-level parallelism specified by the compiler rather than relying on superscalar execution. It supports long instruction bundles containing multiple operations.
- The architecture has large register sets, multiple execution units, predicated execution, and support for software pipelining to further exploit instruction level parallelism.
- The Itanium processor implemented IA-64 using a superscalar design with hardware support for the EPIC features like predication and speculation.
* Know the reasons why various operating systems exist and how they are functioned for dedicated purposes
* Understand the basic concepts while building system software from scratch
• How can we benefit from cheap ARM boards and the related open source tools?
- Raspberry Pi & STM32F4-Discovery
This document provides information about x86 architecture including registers, flags, modes, common instructions, Intel and AT&T syntax, system calls, examples, and references. It defines the purpose of key registers like EAX, EBX, ESP and flags. It explains real and protect modes and differences between Intel and AT&T syntax. Examples demonstrate how to write assembly code and call system calls. References provided can be used to learn more about x86 assembly programming.
The CPU, or processor, carries out the instructions of a computer program and is the primary component responsible for a computer's functions. As microelectronic technology advanced, more transistors were placed on integrated circuits, decreasing the number of chips needed for a complete CPU. Processor registers provide the fastest way for a CPU to access data and are located at the top of the memory hierarchy. Common processor architectures include the ARM architecture which has influenced the design of many CPUs due to its low power consumption and flexibility.
This presentation is about such well-known vulnerabilities as Meltdown and Spectre and the way they use imperfections of modern processors on an architectural level. In this regard, ARM architecture, which is now a standard in embedded system, is discussed.
The talk was delivered by Andrii Lukin (Senior Software Engineer, Consultant, GlobalLogic) at GlobalLogic Embedded Career Day #2 on February 10, 2018.
More about GlobalLogic Embedded Career Day #2: https://www.globallogic.com/ua/events/globallogic-kyiv-embedded-career-day-2-materials
Linux Binary Exploitation - Return-oritend ProgramingAngel Boy
The document discusses using return-oriented programming (ROP) to bypass address space layout randomization (ASLR) and data execution prevention (DEP). It describes using the procedure linkage table (PLT) to leak the address of functions like puts to bypass ASLR. A ROP chain is then constructed to call read to read "/bin/sh" into memory and execute it, achieving arbitrary code execution.
This document provides an outline for a course on 8086 Assembly Language Programming. It begins with an introduction to machine language and assembly language. It then covers topics like the organization of the 8086 processor, assembly language syntax, data representation, variables, instruction types, memory segmentation, program structure, addressing modes, and input/output. The document is intended to guide students through the key concepts needed to program in 8086 assembly language.
GNU Toolchain is the de facto standard of IT industrial and has been improved by comprehensive open source contributions. In this session, it is expected to cover the mechanism of compiler driver, system interaction (take GNU/Linux for example), linker, C runtime library, and the related dynamic linker. Instead of analyzing the system design, the session is use case driven and illustrated progressively.
Tracing MariaDB server with bpftrace - MariaDB Server Fest 2021Valeriy Kravchuk
Bpftrace is a relatively new eBPF-based open source tracer for modern Linux versions (kernels 5.x.y) that is useful for analyzing production performance problems and troubleshooting software. Basic usage of the tool, as well as bpftrace one liners and advanced scripts useful for MariaDB DBAs are presented. Problems of MariaDB Server dynamic tracing with bpftrace and some possible solutions and alternative tracing tools are discussed.
1) Verified boot is the process of assuring users of the integrity of software running on a device by reducing risks from malware and preventing rollbacks to vulnerable past versions. It uses hashing, public key cryptography, and tamper-evident storage.
2) Android Verified Boot 2.0 (AVB) is Google's recommended method for verified boot integration. It uses a signed VBMeta structure containing hashes, hashtrees and rollback indexes to verify the integrity of partitions before booting.
3) AVB supports features like A/B partitions, locked/unlocked device states, and delegates verification authority through chained partitions. It interacts with bootloaders, uses avbtool to generate signatures,
The document discusses assembly language programming concepts including the stack segment, stack, stack instructions, subroutines, macros, and recursive procedures. It provides examples and explanations of these concepts. It also includes sample programs and solutions related to stacks, subroutines, and other assembly language topics.
The document summarizes the general purpose registers on the x86 architecture. It describes the common uses of registers like EAX, EBX, ECX, EDX, ESI, EDI, and EBP. It also covers special purpose registers like EIP and flags. Additionally, it provides an overview of the stack and how it is used to store function parameters, local variables, and return addresses. Finally, it discusses some simple instructions for math, logic, jumping, strings, and manipulating the stack.
Ramon Fried covers the following topics:
* What DMA is.
* DMA Buffer Allocations and Management.
* Cache Coherency.
* PCI and DMA.
* dmaengine Framework.
Ramon is an Embedded Linux team leader in TandemG, leading various cutting edge projects in the Linux kernel.
He has years of experience in embedded systems, operating systems and Linux kernel.
1. The document discusses Linux kernel page reclamation.
2. Direct reclaim is when the caller performs reclamation directly, while daemon reclaim uses kswapd processes.
3. Daemon reclaim involves kswapd processes waking up and using kswapd_shrink_zone() to reclaim pages until all zones are above the high watermark. This helps balance memory usage across zones.
Master Canary Forging by Yuki Koike - CODE BLUE 2015CODE BLUE
Stack Smashing Protection(SSP) is one of the oldest and fundamental protections against exploits, and is now supported by most compilers and modern operating systems.
One technique for SSP is using stack canaries, which verify if a stack buffer has been overflown by checking the integrity of a value stored immediately after the buffer.
Previously, the main methods to bypass stack canaries were to exploit different vulnerabilities to either avoid the canary validation completely, or to provide the correct canary value by leaking the value.
In this talk I will propose a new technique to bypass stack canaries in SSP which takes a different approach from the previous two methods.
Linux Kernel Booting Process (1) - For NLKBshimosawa
Describes the bootstrapping part in Linux and some related technologies.
This is the part one of the slides, and the succeeding slides will contain the errata for this slide.
The document discusses using the PERFORMANCE_SCHEMA in MySQL 5.6 to analyze and troubleshoot performance issues. It provides an overview of the PERFORMANCE_SCHEMA, how to configure what is instrumented and collected, and examples of using it to find bottlenecks like long wait times on InnoDB mutexes. The PERFORMANCE_SCHEMA provides visibility into where time is spent and which resources are most used through its set of in-memory tables.
The document discusses the IA-64 architecture, which was jointly developed by Intel and HP as a 64-bit architecture intended for implementation on EPIC processors like Itanium. Some key points:
- IA-64 uses explicit instruction-level parallelism specified by the compiler rather than relying on superscalar execution. It supports long instruction bundles containing multiple operations.
- The architecture has large register sets, multiple execution units, predicated execution, and support for software pipelining to further exploit instruction level parallelism.
- The Itanium processor implemented IA-64 using a superscalar design with hardware support for the EPIC features like predication and speculation.
* Know the reasons why various operating systems exist and how they are functioned for dedicated purposes
* Understand the basic concepts while building system software from scratch
• How can we benefit from cheap ARM boards and the related open source tools?
- Raspberry Pi & STM32F4-Discovery
This document provides information about x86 architecture including registers, flags, modes, common instructions, Intel and AT&T syntax, system calls, examples, and references. It defines the purpose of key registers like EAX, EBX, ESP and flags. It explains real and protect modes and differences between Intel and AT&T syntax. Examples demonstrate how to write assembly code and call system calls. References provided can be used to learn more about x86 assembly programming.
The CPU, or processor, carries out the instructions of a computer program and is the primary component responsible for a computer's functions. As microelectronic technology advanced, more transistors were placed on integrated circuits, decreasing the number of chips needed for a complete CPU. Processor registers provide the fastest way for a CPU to access data and are located at the top of the memory hierarchy. Common processor architectures include the ARM architecture which has influenced the design of many CPUs due to its low power consumption and flexibility.
This presentation is about such well-known vulnerabilities as Meltdown and Spectre and the way they use imperfections of modern processors on an architectural level. In this regard, ARM architecture, which is now a standard in embedded system, is discussed.
The talk was delivered by Andrii Lukin (Senior Software Engineer, Consultant, GlobalLogic) at GlobalLogic Embedded Career Day #2 on February 10, 2018.
More about GlobalLogic Embedded Career Day #2: https://www.globallogic.com/ua/events/globallogic-kyiv-embedded-career-day-2-materials
GOD MODE UNLOCKED - Hardware Backdoors in x86 CPUsPriyanka Aash
Complexity is increasing. Trust eroding. In the wake of Spectre and Meltdown, when it seems that things cannot get any darker for processor security, the last light goes out. This talk will demonstrate what everyone has long feared but never proven: there are hardware backdoors in some x86 processors, and they're buried deeper than we ever imagined possible. While this research specifically examines a third-party processor, we use this as a stepping stone to explore the feasibility of more widespread hardware backdoors.
This document provides an overview of ARM architecture and its registers, memory, and instruction set. It compares ARM to other microcontroller architectures like Intel, AVR, and PIC. It describes the Cortex processor families and some specific Cortex models. It details the ARM register set including general purpose registers, the program counter, and special registers like the stack pointer and interrupt mask. It also summarizes the ARM memory system and stack operations. Finally, it outlines the ARM instruction set types and syntax.
The document provides an overview of the evolution of the ARM architecture from ARM7TDMI through various generations including Thumb, Thumb-2, and Cortex processors. It describes the key features added at each stage such as instruction sets, pipeline improvements, memory management units, and introduction of features like trustzone and SIMD. The ARM architecture can be implemented with different microarchitectures by various vendors to balance performance and power usage.
Here are the ARM instructions to translate the given C statement:
LDR r0, [r2, r1, LSL #2]
This loads the word from the address calculated by adding the value of register r1 left shifted by 2 (to scale the offset) to the base address in register r2. Since r1 contains the index y, this loads the word from the array at index y.
Here are the ARM instructions to translate the given C statement:
LDR r0, [r2, r1, LSL #2]
This loads the word from the address calculated by adding the value of register r1 left shifted by 2 (to scale the offset) to the base address in register r2. Since r1 contains the index y, this calculates the address of the element as base + (index * word size).
This document provides an introduction to ARM microcontrollers. It discusses that ARM designs RISC processor cores that are used in many microcontrollers produced by various manufacturers. The popular ARM7TDMI architecture is a 32-bit RISC processor that can operate in both 32-bit ARM and 16-bit THUMB modes. It has 31 registers and 7 operating modes. The ARM instruction set allows conditional execution and includes instructions for arithmetic, logical operations, and loading/storing data. Using THUMB instructions reduces code size by 30-40% compared to ARM.
ARM 7 TDMI Processor architecture ,with reference to Processing modes, CPSR Register organization, Privileged and Unprivileged modes are explained.
https://www.youtube.com/watch?v=8oAZEJCwZu8&t=11
This document discusses the ARM instruction set and ARM-based microcontrollers. It describes load-store instructions for single and multiple register data transfer. It also covers branch instructions and theThumb instruction set. The document then discusses the LPC2148 ARM-based microcontroller, including its architecture, memory mapping, and peripherals. It notes the microcontroller has flash memory for code/data storage and SRAM for volatile storage, and peripherals are controlled via register access. Finally, it lists some hardware and software tools used for labs.
The document discusses interrupt setup and handling on ARM and MIPS architectures in Linux. For interrupt setup, it describes copying the interrupt vector table to a specific memory location, initializing interrupt descriptor structures, and registering interrupt handlers. For interrupt handling, it explains the process when an interrupt occurs, including switching to interrupt mode, identifying the interrupt line, calling the registered interrupt service routine, and restoring processor state before returning.
The document provides an introduction and overview of ARM processors. It discusses the background and architecture of ARM, including that ARM is a RISC processor designed for efficiency. It also describes some key features of ARM including Thumb mode, different memory banks, and specialized instructions. The document then discusses ARM concepts such as the ARM instruction set and assembly language programming.
This document provides an introduction to exploiting ARM Linux systems by describing the ARM architecture, assembly instructions, and techniques for exploitation such as stack overflows, altering control flow, and writing shellcode. It explains the ARM instruction set architecture including registers, status flags, instruction classes, and gives examples of assembly instructions for arithmetic, logic, branching, and other operations. The goal is to educate security researchers on analyzing and attacking ARM-based devices.
The document provides information about the ARM architecture including:
1. ARM started as a replacement for the 8-bit 6502 chip in 1985 and was later spun off as its own company focusing on embedded CPU cores.
2. ARM is a 32-bit architecture with a load/store design using 3-operand instructions. It has a large register set and pipelined execution, along with some CISC features like complex multiply and load/store instructions.
3. The ARM programming model includes 7 processor modes, 37 registers including general purpose and special registers like the program counter and status registers, and conditional execution of instructions.
- GCC for ARMv64 Aarch64 introduced new features such as load-acquire/store-release atomics, larger PC-relative addressing, and AdvSIMD for general purpose floating point math.
- The 64-bit registers include integer, SIMD, and floating point registers that share the same register bank.
- Aarch64 supports LP64 and LLP64 data models to address key OS partners such as Linux/UNIX and Windows.
Microcontrollers can be classified based on their bit size and embedded vs external design. The document then describes the characteristics of Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC) architectures. It introduces the Von Neumann and Harvard architectures and lists some common microcontroller families like 8051, PIC, and AVR. The document focuses on describing the AVR architecture, features of the ATmega16 microcontroller, and its memory types, peripherals, and instruction set.
The ARM7TDMI-S processor is a 32-bit RISC microprocessor developed in the 1980s. It uses a 3-stage pipeline to increase processing speed. The pipeline stages are fetch, decode, and execute. The ARM7 has 37 registers, including 31 general-purpose 32-bit registers and status registers. It supports various instruction sets like ARM, Thumb, and Java bytecodes. The ARM architecture emphasizes low power consumption and small size.
The ARM7TDMI-S processor is a 32-bit RISC microprocessor developed in the 1980s. It uses a 3-stage pipeline to increase processing speed. The pipeline stages are fetch, decode, and execute. The ARM7 has 37 registers, including 31 general-purpose 32-bit registers and status registers. It supports various instruction sets like ARM, Thumb, and Java bytecodes. The ARM architecture emphasizes low power consumption and small size.
ARM Ltd designs ARM processor cores and licenses them to semiconductor companies. It also develops software and hardware tools to support the ARM architecture. The ARM architecture uses 32-bit RISC instructions and has 7 processor modes. It supports conditional execution, uses a barrel shifter as part of data processing instructions, and provides various branch instructions for flow control.
Similar to How to get LBR contents on Intel x86 (20)
This was a paper that I wrote about a CFI system, which works alongside randomization techniques like ASLR. It uses the offsets of branch instruction's destination instead of the absolute address. This works alongside ASLR because randomization based protection mechanisms, do the randomization on PAGE size basis, not inside the page itself...
This document outlines the basics of C++ programming, including:
- The history and evolution of C++ and other programming languages.
- How a C++ source code is compiled into an executable program by the compiler in multiple steps like preprocessing, compiling, linking etc.
- The structure of a basic C++ program and key elements like main function, headers, comments.
- How to use input/output streams, variables, arithmetic operations, and conditional statements like if-else in a C++ program.
Linux executables are in ELF format. The document discusses Linux executable formats, compiling C programs in Linux using GCC, and executing programs. It also covers libraries in Linux including static and shared libraries, error handling using errno and assertions, signals and signal handling, process monitoring and /proc filesystem, and managing command line arguments using getopt_long.
An analysis of how ASLR works in Linux. All examples are in CentOS 5. This slide is written in Farsi (Persian) language which by now is the only choice.
Microservice Teams - How the cloud changes the way we workSven Peters
A lot of technical challenges and complexity come with building a cloud-native and distributed architecture. The way we develop backend software has fundamentally changed in the last ten years. Managing a microservices architecture demands a lot of us to ensure observability and operational resiliency. But did you also change the way you run your development teams?
Sven will talk about Atlassian’s journey from a monolith to a multi-tenanted architecture and how it affected the way the engineering teams work. You will learn how we shifted to service ownership, moved to more autonomous teams (and its challenges), and established platform and enablement teams.
E-commerce Application Development Company.pdfHornet Dynamics
Your business can reach new heights with our assistance as we design solutions that are specifically appropriate for your goals and vision. Our eCommerce application solutions can digitally coordinate all retail operations processes to meet the demands of the marketplace while maintaining business continuity.
GraphSummit Paris - The art of the possible with Graph TechnologyNeo4j
Sudhir Hasbe, Chief Product Officer, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
Transform Your Communication with Cloud-Based IVR SolutionsTheSMSPoint
Discover the power of Cloud-Based IVR Solutions to streamline communication processes. Embrace scalability and cost-efficiency while enhancing customer experiences with features like automated call routing and voice recognition. Accessible from anywhere, these solutions integrate seamlessly with existing systems, providing real-time analytics for continuous improvement. Revolutionize your communication strategy today with Cloud-Based IVR Solutions. Learn more at: https://thesmspoint.com/channel/cloud-telephony
WhatsApp offers simple, reliable, and private messaging and calling services for free worldwide. With end-to-end encryption, your personal messages and calls are secure, ensuring only you and the recipient can access them. Enjoy voice and video calls to stay connected with loved ones or colleagues. Express yourself using stickers, GIFs, or by sharing moments on Status. WhatsApp Business enables global customer outreach, facilitating sales growth and relationship building through showcasing products and services. Stay connected effortlessly with group chats for planning outings with friends or staying updated on family conversations.
DDS Security Version 1.2 was adopted in 2024. This revision strengthens support for long runnings systems adding new cryptographic algorithms, certificate revocation, and hardness against DoS attacks.
E-commerce Development Services- Hornet DynamicsHornet Dynamics
For any business hoping to succeed in the digital age, having a strong online presence is crucial. We offer Ecommerce Development Services that are customized according to your business requirements and client preferences, enabling you to create a dynamic, safe, and user-friendly online store.
Essentials of Automations: The Art of Triggers and Actions in FMESafe Software
In this second installment of our Essentials of Automations webinar series, we’ll explore the landscape of triggers and actions, guiding you through the nuances of authoring and adapting workspaces for seamless automations. Gain an understanding of the full spectrum of triggers and actions available in FME, empowering you to enhance your workspaces for efficient automation.
We’ll kick things off by showcasing the most commonly used event-based triggers, introducing you to various automation workflows like manual triggers, schedules, directory watchers, and more. Plus, see how these elements play out in real scenarios.
Whether you’re tweaking your current setup or building from the ground up, this session will arm you with the tools and insights needed to transform your FME usage into a powerhouse of productivity. Join us to discover effective strategies that simplify complex processes, enhancing your productivity and transforming your data management practices with FME. Let’s turn complexity into clarity and make your workspaces work wonders!
AI Fusion Buddy Review: Brand New, Groundbreaking Gemini-Powered AI AppGoogle
AI Fusion Buddy Review: Brand New, Groundbreaking Gemini-Powered AI App
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https://sumonreview.com/ai-fusion-buddy-review
AI Fusion Buddy Review: Key Features
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See My Other Reviews Article:
(1) AI Genie Review: https://sumonreview.com/ai-genie-review
(2) SocioWave Review: https://sumonreview.com/sociowave-review
(3) AI Partner & Profit Review: https://sumonreview.com/ai-partner-profit-review
(4) AI Ebook Suite Review: https://sumonreview.com/ai-ebook-suite-review
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Despite its grandiose-sounding title, this deck consists of just three slides showing the Scala 3 code to be rewritten whenever the details of the operators begin to fade away.
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How to get LBR contents on Intel x86
1. How to get LBR contents
on Intel x86
Reading Last Branch Record MSRs using a
simple Linux kernel module
M.Golyani
(MAGMAG)
2. Table of contents
● What is LBR?
● What is a branch
instruction?
● What is MSR?
● Accessing LBR
● A little about rings
● Enabling LBR in Intel
● WRMSR, RDMSR
● Filtering LBR
● Address of LBR registers
● Reading LBR
● One MSR set for each CPU
● Entering ring-0
● LKM 4 LBR
3. What is LBR
● Intel says:
“Processors based on Intel micro-architecture (Nehalem) provide 16
pairs of MSR to
record last branch record information.”
● Nehalem??
Intel uses code names for it's products. Nehalem is the codename of Intel
micro-architecture. First CPU using this arch was core i7, released in 2008.
4. What is Branch
● From Wikipedia:
“A branch is an instruction in a computer program that may, when
executed by a computer, cause the computer to begin execution of a
different instruction sequence.”
● Instructions like: jmp, call, jz, jnz, …. are all branch instructions.
● When a branch instruction is executed, the execution flow, redirects from
where it was to a specific destination.
● Here, the term “Source” is the address where this instruction is located and
the term “Destination” is the address where it is redirecting to.
5. What is MSR
●
Wikipedia says:
“A model-specific register (MSR) is any of various control registers in the x86 instruction
set used for debugging, program execution tracing, computer performance monitoring,
and toggling certain CPU features”
● Intel says:
- “Most IA-32 processors (starting from Pentium processors) and Intel 64 processors
contain a model-specific registers (MSRs). A given MSR may not be supported across
all families and models for Intel 64 and IA-32 processors.
- Some MSRs are designated as architectural to simplify software programming; a
feature introduced by an architectural MSR is expected to be supported in future
processors. Non-architectural MSRs are not guaranteed to be supported or to have the
same functions on future processors.”
7. Accessing LBR
● To access LBR in a processor, we should first enable this option
in desired processor.
● After enabling LBR, we can use Intel's “rdmsr” instruction to
read the contents of LBR model specific registers.
● Each MSR, has a number (Address) in every processor and to
access a LBR, we should use that address with rdmsr
instruction.
● The rdmsr instruction must be executed in ring 0 (kernel mode)
8. Kernel, the lord of the rings
● Wikipedia:
In computer science, hierarchical protection domains, often called protection rings, are
mechanisms to protect data and functionality from faults (by improving fault tolerance)
and malicious behavior (by providing computer security).
● Me!!:
Protection rings is an access control mechanism used in some
operating systems (Multics,...) and is implemented in some processors.
Read “operating system security” (Trent Jaeger) for further information.
9. Kernel, the lord of the rings
Ash nazg durbatulûk ,
Ash nazg gimbatul,
Ash nazg thrakatulûk
Agh burzumishi
krimpatul.
In Linux, kernel modules run here
(image from wikipedia)
10. Enabling LBR
● To enable LBR, you should read Intel's data-sheet of your system's
processor (if it's Intel).
● In “Intel® 64 and IA-32 Architectures Software Developer’s Manual”, it
is mentioned that enabling LBR is done using a MSR with address of
01D9H.
● Take care in reading these data-sheets, the MSR addresses may vary
across different processors of Intel (although, usually are the same).
● My processor is an Intel core i7 (/proc/cpuinfo), so I used the
information listed in section 19.6 of this data-sheet.
11. Enabling LBR
The first bit of IA32_DEBUGCTL MSR should be set to 1 for enabling LBR
in each of my CPUs (Intel core i7 on lenovo thinkpad T420)
12. WRMSR,RDMSR
● To change a MSR value, we should use “wrmsr” instruction and to
read a MSR value, “rdmsr” is used.
● wrmsr and rdmsr must be executed in ring-0.
● Reading Intel instruction set reference, will teach us how to use these
instructions.
13. Enabling LBR
● Finding that IA32_DEBUGCTL MSR is located at address 1D9H, we
can use the following code to set it's first bit to “1” and rest of them to
“0” :
asm volatile (
"xor %%edx, %%edx;"
"xor %%eax, %%eax;"
"inc %%eax;"
"mov $0x1d9, %%ecx;"
"wrmsr;"
:
:
:
);
14. Filtering LBR
● After enabling LBR, we can filter it to contain only user-space branch
traces.
According to appendix B, section B.4 in Intel software developer's manual,
MSR_LBR_SELECT for Nehalem based CPUs is located at 1C8H.
15. Filtering LBR
● To filter LBR to contain only user-space branches, it's enough to write
“0x1” into MSR_LBR_SELECT register (located at 1C8H).
asm volatile (
"xor %%edx, %%edx;"
"xor %%eax, %%eax;"
"inc %%eax;"
"mov $0x1c8, %%ecx;"
"wrmsr;"
:
:
:
);
16. Address of LBR registers
● The 16 MSR pairs which contain last branch record, for my CPU is
located at 680H (1664 D) up to 68FH regarding to 16 registers of
MSR_LASTBRANCH_FROM_IP and from 6C0H to 6CFH regarding
to 16 registers of MSR_LASTBRANCH_TO_IP.
● Each FROM_IP MSR, indicates the “source” of branch and
corresponding TO_IP MSR, indicates the “destination” of that branch.
● Table B-5, MSRs in Processors Based on Intel Microarchitecture is for
my CPU. Find Yours yourself :D
18. One MSR set for each CPU
● Each CPU has it's own MSR registers, so it's very possible that you
enable LBR on one CPU and have it disabled on others.
● This could lead to lost of branch traces as the target application, will
probably run on all of existing CPUs (unless using processor affinity).
● To enable LBR on all CPUs, best way (AFAIK) is to write a multi-thread
code with number of threads equal to number of processors, then
binding each thread to one processor and finally enabling LBR on each
of them.
19. Entering ring-0
● As mentioned before, wrmsr and rdmsri must be executed in ring-0.
● To do so, the simplest way (again AFAIK) is to write a kernel module
and then inserting it into kernel (insmod).
● Using a KM, we can print LBR contents on /var/log/kern.log
(/var/log/messages) using “printk()” function.
● A very good point to start writing kernel modules is “The Linux Kernel
Module Programming Guide” written by Peter Salzman et al. Although
there are some differences between writing a KM for kernel 2.X and
3.x.
20. LKM 4 LBR
● BTW, to compile a kernel module, first you should obtain the running
kernel source files (linux-headers) Here is mine:
21. LKM 4 LBR
● After that, you can start writing your code and creating appropriate
Makefile for it, like this:
22. LKM 4 LBR
● After creating Makefile, you can compile your module, using make
command: