This document provides specifications for a System on Chip (SoC) design containing a Memory Interface Block (MIB) and a Universal Asynchronous Receiver and Transmitter (UART) interface. It includes block diagrams, I/O descriptions, state machines, and verification simulations for the top level design and all internal blocks. The top level interacts with a provided TramelBlaze microcontroller core and contains the MIB and UART blocks. The MIB allows the TramelBlaze to interface with an off-chip memory. The UART block contains independently designed transmit and receive engines that have been verified to successfully transmit and receive serial data to and from a terminal via the UART interface. Revision 4.0

1. CSULB
COLLEGE OF ENGINEERING
Department of Computer Engineering and Computer Science
FINAL Project
Final System on Chip Specification
MIB, UART, & TramelBlaze
CECS 460: System on Chip Design
Submitted by:
Phuong Nguyen
(013132325)
on December 16, 2016
Submitted to:
Mr. John Tramel
CECS Faculty

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Document Name:
Final Specification
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This document contains information proprietary to the
CSULB student that created the file - any reuse without
adequate approval and documentation is prohibited.
In submitting this file for class work at CSULB
I am confirming that this is my work and the work
of no one else.
In the event, other code sources are utilized I will
document which portion of code and who is the author.
In submitting this project, I acknowledge that plagiarism
in student project work is subject to dismissal from the class.

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Table of Contents
1. Introduction ........................................................................................................................... 10
1.1. Purpose........................................................................................................................... 10
2. External Documents .............................................................................................................. 11
2.1. PicoBlaze........................................................................................................................ 11
2.1.1. Architecture............................................................................................................. 11
2.1.2. Instruction Set......................................................................................................... 12
2.2. Nexys 4 Data Sheet ........................................................................................................ 14
2.2.1. UART Connection .................................................................................................. 14
2.2.2. Basic I/O connection............................................................................................... 15
2.2.3. Cellular RAM Interface .......................................................................................... 16
2.3. ASCII Table ................................................................................................................... 16
2.4. Spartan-6 Libraries Guide for HDL Designs ................................................................. 17
2.5. Micron MT458MW16BGX Data Sheet......................................................................... 18
3. Requirements......................................................................................................................... 19
3.1. Interface Requirements .................................................................................................. 19
3.2. Physical Requirements................................................................................................... 20
4. Top Level Design .................................................................................................................. 21
4.1. Description ..................................................................................................................... 21
4.2. Detailed Block Diagram................................................................................................. 22
4.4. Data Flow Description ................................................................................................... 23
4.5. I/O................................................................................................................................... 23
4.5.1. Signal Names .......................................................................................................... 23
4.5.2. Pin Assignment....................................................................................................... 24
4.5.3. Electrical Characteristics ........................................................................................ 24
4.6. Clocks............................................................................................................................. 25

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4.7. Resets ............................................................................................................................. 25
4.8. Software ......................................................................................................................... 26
5. Externally Developed Blocks ................................................................................................ 31
5.1. Asynchronous In, Synchronous Out (AISO).................................................................. 31
5.2. TramelBlaze ................................................................................................................... 32
6. Internally Developed Blocks ................................................................................................. 33
6.1. Core................................................................................................................................ 33
Description............................................................................................................................. 33
I/O.......................................................................................................................................... 34
6.1.1. Memory Interface Block (MIB).............................................................................. 35
6.1.2. Universal Asynchronous Receiver and Transmitter (UART)................................. 38
6.1.3. Baud Rate Decoder ................................................................................................. 61
6.1.4. Pulse Maker ............................................................................................................ 62
6.1.5. RS Flop ................................................................................................................... 63
6.2. Technology Specific Instantiation (TSI)........................................................................ 64
Description............................................................................................................................. 64
I/O.......................................................................................................................................... 65
7. Chip Level Verification......................................................................................................... 66
7.1. Revision 2.0: Transmit Engine....................................................................................... 66
7.2. Revision 3.0: Receive Engine ........................................................................................ 67
7.3. Revision 4.0: Memory Interface Block.......................................................................... 69
8. Chip Level Test ..................................................................................................................... 70
9. Appendix ............................................................................................................................... 71
A1. Top Module Source Code................................................................................................... 71
A2. Core Source Code............................................................................................................... 74
A3. MIB Source Code............................................................................................................... 77

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A4. UART Top Source Code.................................................................................................... 81
A5. Transmit Engine Top Source Code .................................................................................... 83
A6. Transmit Bit Count Source Code ....................................................................................... 85
A7. Transmit Bit Time Counter Source Code........................................................................... 86
A8. Transmit Controller Source Code....................................................................................... 87
A9. Transmit Bit 10 & 9 Decoder Source Code ....................................................................... 88
A10. Transmit Shift Register Source Code............................................................................... 89
A11: Receive Engine Top Source Code.................................................................................... 90
A12: Receive Shift Register Source Code ................................................................................ 92
A13. Receive State Machine Source Code................................................................................ 93
A14. Receive Controller Source Code ...................................................................................... 95
A15: Receive Bit Count Source Code....................................................................................... 97
A16: Receive Bit Time Counter Source Code .......................................................................... 98
A17. Baud Rate Decoder Source Code ..................................................................................... 99
A18. AISO Source Code......................................................................................................... 100
A19. Pulse Maker Source Code .............................................................................................. 101
A20. RS Flop Source Code ..................................................................................................... 102
A21. TSI Source Code ............................................................................................................ 103
Table of Figures
Figure 1: PicoBlaze/TramelBlaze Architecture............................................................................ 11
Figure 2: Input and Output Timing Diagram................................................................................ 12
Figure 3: Nexys 4 UART Interface............................................................................................... 14
Figure 4: Nexys 4 I/O Interface .................................................................................................... 15
Figure 5: Nexys 4 Cellular RAM Interface................................................................................... 16

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Figure 6: ASCII Table .................................................................................................................. 16
Figure 7: Timing Diagrams for Reading and Writing .................................................................. 18
Figure 8: Design Top Module....................................................................................................... 21
Figure 9: Detailed Top Module..................................................................................................... 22
Figure 10: AISO Block Diagram .................................................................................................. 31
Figure 11: TramelBlaze Block Diagram....................................................................................... 32
Figure 12: Core Top Module & Core Interface Interactions ........................................................ 33
Figure 13: MIB Top Module......................................................................................................... 35
Figure 14: MIB State Machine ..................................................................................................... 37
Figure 15: MIB Verification......................................................................................................... 37
Figure 16: UART Top Module ..................................................................................................... 38
Figure 17: UART Detailed Block Diagram.................................................................................. 39
Figure 18: Transmit Engine Top Module ..................................................................................... 41
Figure 19: Transmit Engine Detailed Block Diagram .................................................................. 42
Figure 20: Transmit Engine Verification...................................................................................... 43
Figure 21: Transmit Bit Count Module ........................................................................................ 44
Figure 22: Transmit Bit Count Verification.................................................................................. 44
Figure 23: Transmit Bit Time Counter Module............................................................................ 45
Figure 24: Bit Time Counter Verification .................................................................................... 45
Figure 25: Transmit Controller Module........................................................................................ 46
Figure 26: Transmit Controller Verification................................................................................. 46
Figure 27: Bit Decoder Module.................................................................................................... 47
Figure 28: Bit Decoder Verification ............................................................................................. 47
Figure 29: Transmit Shift Register Module.................................................................................. 48
Figure 30: Transmit Shift Register Verification ........................................................................... 48
Figure 31: Receive Engine Top Module....................................................................................... 49

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Figure 32: Receive Engine Detailed Block Diagram.................................................................... 50
Figure 33: Receive Engine Verification ....................................................................................... 52
Figure 34: Receive Shift Register Module.................................................................................... 53
Figure 35: Receive Shift Register Verification............................................................................. 53
Figure 36: Receive State Machine Module................................................................................... 54
Figure 37: Receive State Machine ................................................................................................ 54
Figure 38: Receive State Machine Verification............................................................................ 55
Figure 39: Receive Controller Module ......................................................................................... 56
Figure 40: Receive Ready Signal Verification ............................................................................. 57
Figure 41: Parity Error Verification (working)............................................................................. 57
Figure 42: Parity Error Verification (not working)....................................................................... 57
Figure 43: Framing Error Verification (working)......................................................................... 58
Figure 44: Framing Error Verification (not working)................................................................... 58
Figure 45: Overflow Error Verification (working)....................................................................... 58
Figure 46: Overflow Error Verification (not working)................................................................. 58
Figure 47: Receive Bit Count Module.......................................................................................... 59
Figure 48: Receive Bit Count Verification ................................................................................... 59
Figure 49: Receive Bit Time Counter Module ............................................................................. 60
Figure 50: Receive Bit Time Counter Verification....................................................................... 60
Figure 51: Baud Rate Decoder Module ........................................................................................ 61
Figure 52: Baud Rate Decoder Verification ................................................................................. 61
Figure 53: Pulse Maker Module ................................................................................................... 62
Figure 54: Pulse Maker Verification............................................................................................. 62
Figure 55: RS Flop Module .......................................................................................................... 63
Figure 56: RS Flop Verification ................................................................................................... 63
Figure 57: TSI Top Module.......................................................................................................... 64

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Figure 58: Transmit Engine w/ TramelBlaze Verification ........................................................... 66
Figure 59: Transmit Engine with TramelBlaze Serial Terminal Output ...................................... 66
Figure 60: Receive Engine w/ Transmit Engine Feed Verification.............................................. 67
Figure 61: Test connection between Transmit Engine and Receive Engine ................................ 67
Figure 62: Full UART and TramelBlaze Serial Terminal Output ................................................ 68
Figure 63: MIB with Cell Ram Verification................................................................................. 69
Figure 64: Memory Address and Data.......................................................................................... 69
Figure 65: Chip Level Test with MIB, Full UART, and TramelBlaze......................................... 70
Table of Tables
Table 1: PicoBlaze Instruction Set................................................................................................ 12
Table 2: Instructions used by Design............................................................................................ 13
Table 3: Buffers used in TSI......................................................................................................... 17
Table 4: Baud Rate Truth Table.................................................................................................... 19
Table 5: Parity Truth Table........................................................................................................... 19
Table 6: Design Switch Interface.................................................................................................. 20
Table 7: Design Button Interface.................................................................................................. 20
Table 8: Design LED Interface..................................................................................................... 20
Table 9: Top Level Signal Names ................................................................................................ 23
Table 10: Top Level Pin Assignments.......................................................................................... 24
Table 11: Memory Address and Bidirectional Data Ports............................................................ 24
Table 12: AISO I/O....................................................................................................................... 31
Table 13: AISO Register Map ...................................................................................................... 31
Table 14: TramelBlaze I/O ........................................................................................................... 32
Table 15: TramelBlaze Register Map........................................................................................... 32
Table 16: Core I/O ........................................................................................................................ 34

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Table 17: MIB I/O ........................................................................................................................ 36
Table 18: MIB Register Map........................................................................................................ 37
Table 19: UART I/O ..................................................................................................................... 40
Table 20: Transmit Engine I/O ..................................................................................................... 43
Table 21: Transmit Engine Register Map..................................................................................... 43
Table 23: Transmit Bit Count I/O................................................................................................. 44
Table 22: Bit Time Counter I/O.................................................................................................... 45
Table 24: Transmit Controller I/O ................................................................................................ 46
Table 25: Bit Decoder Truth Table............................................................................................... 47
Table 26: Bit Decoder I/O............................................................................................................. 47
Table 27: Transmit Shift Register I/O .......................................................................................... 48
Table 28: Receive Engine I/O....................................................................................................... 51
Table 29: Receive Engine Register Map ...................................................................................... 51
Table 35: Receive Shift Register I/O............................................................................................ 53
Table 31: Receive State Machine I/O ........................................................................................... 54
Table 34: Receive Controller I/O.................................................................................................. 56
Table 32: Receive Bit Count I/O .................................................................................................. 59
Table 33: Receive Bit Count Truth Table..................................................................................... 59
Table 30: Receive Bit Time Counter I/O...................................................................................... 60
Table 36: Baud Rate Decoder I/O................................................................................................. 61
Table 37: Baud Rate Decoder Register Map ................................................................................ 61
Table 38: Pulse Maker I/O............................................................................................................ 62
Table 39: Pulse Maker Register Map............................................................................................ 62
Table 40: RS Flop I/O................................................................................................................... 63
Table 41: RS Flop Register Map .................................................................................................. 63
Table 42: TSI I/O.......................................................................................................................... 65

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1. Introduction
This Chip Specification document is intended to describe every detail of the Memory
Interface Block (MIB) and Full Universal Asynchronous Receiver and Transmitter (UART)
Interface implemented by the preparer. In Revision 2.0, the Transmit Engine was interfaced to
the TramelBlaze, which was provided by Mr. John Tramel. Revision 3.0 built on top of the
Transmit Engine with the implementation of the Receive Engine. The two engines instantiated
together created the Full UART, which proved capable of receiving and transmitting data from/to
a Serial Terminal. In this final revision, a Memory Interface Block was implemented to grant the
TramelBlaze the ability to access the on-board Micron memory of the Nexys 4.
1.1. Purpose
The purpose of this document is to describe the details of the MIB and Full UART. First,
this document will elaborate on the chip‟s top level specifications with block diagrams, dataflow
descriptions, and details on the system‟s I/O ports. Secondly, this document will elaborate on the
details of each externally and internally developed block. The details will include their purposes,
Block Diagrams, I/O, State Machines (if necessary) and Register Map. With each internally
developed block, verification will be provided through the use of ISim‟s simulations. Lastly the
document provides a Chip Level Verification and Chip Level Test to prove the competence of
the MIB and the Full UART by exercising their functionalities.

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2. External Documents
These documents were used in the development of the design. They were used to assist in
understanding the TramelBlaze and its interfaces but also assisted in creating the actual interface
and the Programmable Read-Only Memory (PROM) of the system.
2.1. PicoBlaze
The PicoBlaze is a cost-effective fully embedded 8-bit RISC microcontroller that
provided the basis of how the TramelBlaze was developed. Because of the identical instruction
set and architecture of the two microcontrollers, the PicoBlaze‟s user‟s guide proved helpful in
understanding and developing the ROM of the TramelBlaze.
2.1.1. Architecture
Figure 1: PicoBlaze/TramelBlaze Architecture
Understanding the connections between different components of the TramelBlaze
provided a vast amount of information on how the data flows. Especially with the development
of Read-Only Memory (ROM), having a schematic to detail the pathway of data provided
tremendous insight on how to properly develop the ROM.

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2.1.2. Instruction Set
Program Control
JUMP aaa
JUMP Z, aaa
JUMP C, aaa
JUMP NC, aaa
CALL aaa
CALL Z, aaa
CALL C, aaa
CALL NC, aaa
RETURN
RETURN Z
RETURN NZ
RETURN C
RETURN NC
Arithmetic
ADD sX, kk | (sX, sY)
ADDCY sX, kk | (sX, sY)
SUB sX, kk | (sX, sY)
SUBCY sX, kk | (sX, sY)
COMPARE sX, kk | (sX,
sY)
Logical
LOAD sX, kk | (sX, sY)
AND sX, kk | (sX, sY)
OR sX, kk | (sX, sY)
XOR sX, kk | (sX, sY)
TEST sX, kk | (sX, sY)
Shift and Rotate
SR0 sX
SR1 sX
SRX sX
SRA sX
RR sX
SL0 sX
SL1 sX
SLX sX
SLA sX
RL sX
Interrupt
RETURNI ENABLE
RETURNI DISABLE
ENABLE INTERRUPT
DISABLE INTERRUPT
Storage
STORE sX, ss | (sX,
(sY))
FETCH sX, ss | (sX,
(sY))
Input/output
INPUT sX, pp | (sX, sY)
OUTPUT sX, pp | (sX, sY)
Table 1: PicoBlaze Instruction Set
Table 1 list out every instruction available to use for the PicoBlaze; in general, the
TramelBlaze utilizes the same instruction set, so ROM development will be similar to that of the
PicoBlaze.
Figure 2: Input and Output Timing Diagram
Figure 2 shows the timing diagrams behind the INPUT and OUTPUT instructions. These
are instructions are crucial in making the UART work properly as the UART utilizes these two
instructions to communicate with the TramelBlaze.

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Instruction Description Function Zero Carry
ADD sX, kk Add sX with literal kk sX ← sX + kk ? ?
CALL aaa Unconditionally call subroutine at aaa TOS ← PC
PC ← aaa
- -
COMP sX, kk Compare sX with literal kk, Set CARRY and
ZERO flags as appropriate.
If sX=kk, ZERO ← 1
If sX<kk, CARRY ← 1
? ?
ENINT Enable interrupt input INTERRUPT_ENABLE ← 1 - -
FETCH sX, ss Read scratchpad RAM location ss into
register sX
sX ← RAM[ss] - -
INPUT sX, pp Read value on input port location pp into
register sX
PORT_ID ← pp
sX ← IN_PORT
- -
JUMP aaa Unconditionally jump to aaa PC ← aaa - -
JUMPZ aaa If ZERO flag set, jump to aaa If ZERO=1, PC ← aaa - -
LOAD sX, kk Load register sX with literal kk sX ← kk - -
OUTPUT sX, pp Write register sX to output port location
pp
PORT_ID ← pp
OUT_PORT ← sX
- -
RETEN Return from interrupt service routine. PC ← TOS
ZERO ← Preserved ZERO
CARRY ← Preserved CARRY
INTERRUPT_ENABLE ← 1
? ?
RETURN Unconditionally return from subroutine PC ← TOS+1 - -
STORE sX, (sY) Write register sX to scratchpad RAM
location pointed to by register sY
RAM[(sY)] ← sX - -
Table 2: Instructions used by Design
In the development of this design, many of the TramelBlaze‟s instructions were used to
create the ROM. Table 2 goes into detail with every instruction used in the development of the
UART.

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2.2. Nexys 4 Data Sheet
The datasheet provided all the essential information on the hardware of the Nexys 4. This
consisted of the 100MHz Crystal Oscillator, UART connections, basic I/O connections and
interface information for the Micron Memory.
2.2.1. UART Connection
Figure 3: Nexys 4 UART Interface
The figure above was taken directly from the Data Sheet and showed the connections
between the Micro-USB and the Nexys 4 board. Though the diagram shows a FT2232 driver
between the Nexys 4 Chip and USB, it was unnecessary in this application as JTAG was not
being utilized. Hence, the diagram showed that port C4 is used to received data from the Micro-
USB and D4 is used to transmit data to the Micro-USB.

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2.2.2. Basic I/O connection
Figure 4: Nexys 4 I/O Interface
This figure shows the connection of the LEDs, switches, and buttons and their interfaces.
It provided information on the voltages required to provide a logic 1 or logic 0 on both the
switches and buttons.

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2.2.3. Cellular RAM Interface
Figure 5: Nexys 4 Cellular RAM Interface
This figure provides information on how to connect the required signals to the Cellular
RAM. Along with this figure, a table was also provided to show the ports for both the address
bus and data bus. This was essential in the instantiation between the project and the 8Mbyte
RAM.
2.3. ASCII Table
Figure 6: ASCII Table
An ASCII Table assisted in developing every interface. It provided a quick and easy way
to translate the given ASCII values into understandable character.

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2.4. Spartan-6 Libraries Guide for HDL Designs
The Spartan-6 Libraries Guide provided essential information to complete the design for
the MIB and TSI. Particularly, this document provided details on the IBUFG, IBUF, OBUF,
IOBUF, include the Instantiation Templates and Logic Tables. This provided the foundation in
completing the TSI.
Buffer Description
IBUFG is used to connect incoming clocks to
the Core. This can only be driven by the global
clock pin; in the case of the Nexys 4, would be
pin E3.
IBUF is a simple buffer used to connect any
input from the top level to the design‟s core.
OBUF is a simple buffer used to drive output
signals to the FPGA from the core.
IOBUF allows the design to utilize
bidirectional pins on the FPGA board. T
controls the direction of the data flow as seen
in the truth table below.
T I IO O
1 X Z IO
0 1 1 1
0 0 0 0
Table 3: Buffers used in TSI

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2.5. Micron MT458MW16BGX Data Sheet
The Nexys 4 utilizes a cellular RAM from Micron called the MT458MW16BGX. The
data sheet provided information on how to access the memory through signals. The signals
allowed the Nexys to read and write to memory based on the times provided by this data sheet.
Provided in Figure 7, are the timing diagrams for both the read and write. The datasheet also
provides the timing of each of the signals labeled by the figure.
Figure 7: Timing Diagrams for Reading and Writing

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3. Requirements
3.1. Interface Requirements
This design must be able to utilize three main components, the TramelBlaze, the UART,
and the MIB. These components must be instantiated together to create the core. And any signals
from the core must interact with a Technology Specific Instantiation (TSI) before it interacts
with the FPGA. The core must utilize the MIB by taking in characters from the Receive Engine
of the UART, and storing them into the on-board Micron Memory. Once an asterisk is received
by the design, the Tramelblaze must take whatever was stored into the Micron memory and
output all the characters onto the Serial Terminal via Transmit Engine. Along with the outputting
of the memory data, a banner must be implemented to interface the Serial Terminal.
The Requirements from previous revisions must be implemented as well. The on-board
switches must be able to control the Baud Rate and the options for the UART parity.
Baud Switches Baud Rate Bit Time Nexys 4 Count
0000 300 0.003333333 333333
0001 1200 0.000833333 83333
0010 2400 0.000416667 41667
0011 4800 0.000208333 20833
0100 9600 0.000104167 10417
0101 19200 5.20833E-05 5208
0110 38400 2.60417E-05 2604
0111 57600 1.73611E-05 1736
1000 115200 8.68056E-06 868
1001 230400 4.34028E-06 434
1010 460800 2.17014E-06 217
1011 921600 1.08507E-06 109
Table 4: Baud Rate Truth Table
The logic table below describes the operations of each switch. The MSB will control
whether the transmit engine will send 7 bits or 8 bits. The second bit will enable or disable the
parity bit. And the LSB will control whether the parity will be even or odd.
Bits and Parity Switches Bits Sent Parity Options
000 7 Disabled
001 7 Disabled
010 7 Enabled/Even
011 7 Enabled/Odd
100 8 Disabled
101 8 Disabled
110 8 Enabled/Even
111 8 Enabled/Odd
Table 5: Parity Truth Table

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3.2. Physical Requirements
SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0
N/A 8bits/7bits Parity En oHeL Baud 3 Baud 2 Baud 1 Baud 0
Table 6: Design Switch Interface
The table above shows the interface of the first byte of switches provided by the Nexys 4.
The values in every port change the UART‟s configurations.
BTNU BTND BTNC BTNL BTNR
N/A N/A Global Reset N/A N/A
Table 7: Design Button Interface
Only one of the buttons will be utilized and it will be used to reset the system entirely.
Because it is a reset, it does not require a debounce as crucial data is not being passed through
once it is pressed.
LD4 LD3 LD2 LD1 LD0
Overflow Framing Error Parity Error Transmit Ready Receive Ready
Table 8: Design LED Interface
In addition to the switches and buttons implemented in Transmit Engine, Revision 3.0
requires LEDs to turn on if the given line is asserted.
 Overflow: Occurs when the Receive Engine is done receiving all the necessary bits but
Receive Ready is still asserted.
 Framing Error: Occurs when the Receive Engine is done receiving the expected number
of bits but the last bit is not asserted.
 Parity Error: Occurs when the generated parity and received parity do not match.
 Transmit Ready: This is asserted when the Transmit Engine is done transmitting its
data.
 Receive Ready: This is asserted when the Receive Engine has received the expected
number of bits based on Parity Options.

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4. Top Level Design
4.1. Description
The Top Level is responsible for connection two things, the Core and the TSI. The Core
consists of the design itself, while the TSI contains all references to the target technology
libraries. Any communication from the core‟s I/O‟s must pass through the TSI before interacting
with the FPGA.
Figure 8: Design Top Module

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4.2. Detailed Block Diagram
Figure 9: Detailed Top Module
4.3. Source Code: Appendix A1

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4.4. Data Flow Description
The previous revisions of this design have verified the functionalities of both the
Transmit Engine and Receive Engine of the UART. The Transmit Engine was verified when the
statement “CSULB CECS 460 <CR><LF>” was consistently printed onto a Serial Terminal.
Next the Receive Engine was verified when it was able to take in a user inputted character and
transmit directly to the terminal. Typically known as an echo, the design was also able to detect
parity errors, framing errors, and overflow errors in case the transmission of data from one
machine to the next was not correct. Additionally, the TramelBlaze was able to service the
correct engine based on the Port ID‟s.
In this revision, a MIB was created to give the TramelBlaze access to the on-board
Micron Memory. Alongside with the Full UART, the TramelBlaze should be able to take in data
from the Serial Terminal and write those characters into a location in memory. Once an asterisk
is received by the Receive Engine, the data in the memory will then be read by the TramelBlaze
and outputted to the Serial Terminal.
4.5. I/O
4.5.1. Signal Names
Signal From To Description
c_clk TSI Core 100MHz Crystal Oscillator
c_reset TSI Core System Reset
c_switches TSI Core Baud Rate and Parity Options
c_Tx Core TSI Transmit Line out to USB
c_Rx TSI Core Receive Line in from USB
c_mem_addr Core TSI Points to a location in Micron Memory
c_status Core TSI Detects data errors, and Engine readiness
c_CE Core TSI Chip Enable for Micron Memory
c_WE Core TSI Write Enable for Micron Memory
c_OE Core TSI Output Enable for Micron Memory
c_ADV Core TSI Address Valid
c_CRE Core TSI Control Register Enable
c_UB Core TSI Upper 6 bits of Micron Memory Address
c_LB Core TSI Lower 16 bits of Micron Memory Address
c_mem_clk TSI Core Cell Ram Clock
MIB_I Core TSI Data from MIB to Micron Memory
MIB_O TSI Core Data from Micron Memory to MIB
T Core TSI IOBUF Selector
Table 9: Top Level Signal Names

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4.5.2. Pin Assignment
Input Signals Assignment Output Signals Assignment
clk_in E3 Tx_Out D4
reset E16 ADV_n T13
Rx_In C4 CE_n L18
Parity_ops [2] V6 LB_n J15
Parity_ops [1] V7 UB_n J13
Parity_ops [0] R5 OE_n H14
Baud_Selector [3] R6 WE_n R11
Baud_Selector [2] R7 CRE J14
Baud_Selector [1] U8 mem_clk T15
Baud_Selector [0] U9 Status [7] U6
Status [6] U7
Status [5] T4
Status [4] T5
Status [3] T6
Status [2] R8
Status [1] V9
Status [0] T8
Table 10: Top Level Pin Assignments
Address Bus Data Bus
m_address[22]: U13 m_address[13]: U16 m_address[4]: H16 MIB_IO[1]: P17 MIB_IO[6]: T18
m_address[21]: M16 m_address[12]: P14 m_address[3]: J17 MIB_IO[1]: N17 MIB_IO[5]: R17
m_address[20]: T10 m_address[11]: V12 m_address[2]: H15 MIB_IO[1]: P18 MIB_IO[4]: U18
m_address[19]: U17 m_address[10]: V14 m_address[1]: H17 MIB_IO[1]: M17 MIB_IO[3]: R13
m_address[18]: V17 m_address[9]: U14 m_address[0]: J18 MIB_IO[1]: M18 MIB_IO[2]: U12
m_address[17]: M13 m_address[8]: V16 MIB_IO[1]: G17 MIB_IO[1]: T11
m_address[16]: N16 m_address[7]: N15 MIB_IO[9]: G18 MIB_IO[0]: R12
m_address[15]: N14 m_address[6]: K13 MIB_IO[8]: F18
m_address[14]: R15 m_address[5]: K15 MIB_IO[7]: R18
Table 11: Memory Address and Bidirectional Data Ports
4.5.3. Electrical Characteristics
 Switches
o 1.8V are considered Logical 1
o 0V are considered Logical 0
 Buttons
o 3.3V are considered Logical 1
o 0V are considered Logical 0

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4.6. Clocks
The Nexys 4 is powered by a 100MHz crystal oscillator which is connected to pin E3.
Every single flop in the project will utilize this clock.
4.7. Resets
The project will utilize a HIGH active reset, this HIGH active reset will be fed into an
Asynchronous In, Synchronous Out (AISO) module that ensure that every flop will be reset
synchronously.

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4.8. Software
;Programmers: Tony Le and Phuong Nguyen
;Last Updated: December 9, 2016
;Description: .tba file for interacting with memory
; Will receive an input and output the same value
; As well as saving the data to memory
;PORT_ID Function Reference
;0000 R/W data
;0001 Read status bits
;0011 Write to Address Register 0
;0012 Write to Address Register 1
;0013 Write to Data Out Register
;0014 Read Data In Register
;0015 Perform Memory Read
;0016 Perform Memory Write
ZEROS EQU 0000
ONE EQU 0001
FLAG_BITS EQU 0003
BOTH_FLAGS EQU 0003
RX_FLAG EQU 0001
TX_FLAG EQU 0002
ASTERICK EQU 002A
BACKSPACE EQU 0008
SPACE EQU 0020
CR EQU 000D
LF EQU 000A
C EQU 0043
E EQU 0045
H EQU 0048
I EQU 0049
L EQU 004C
O EQU 004F
W EQU 0057
;REGISTERS
BAN_FLAG EQU R0
ADDR_CHECK EQU R0
STATUS EQU R1
DATA EQU R2
FLAG EQU R4
ADDR_7UB EQU R5
ADDR_16LB EQU R6
COUNTER_UB EQU R7
COUNTER_LB EQU R8
PROM_FLAG EQU R9
SCRATCH EQU RA
DEL_FLAG EQU RB
MEM_DATA EQU RC
BAN_DATA EQU RC
NEWLINE EQU RD
NL_FLAG EQU RE
BANNER EQU RF

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START LOAD R0, ONE ;INITIALIZE VALUES
LOAD DATA, ZEROS
LOAD FLAG, ZEROS
LOAD ADDR_7UB, ZEROS
LOAD ADDR_16LB, ZEROS
LOAD COUNTER_UB, ZEROS
LOAD COUNTER_LB, ZEROS
LOAD SCRATCH, BACKSPACE ;store values for delete
STORE SCRATCH, 0000
LOAD SCRATCH, SPACE
STORE SCRATCH, 0001
LOAD SCRATCH, BACKSPACE
STORE RA, 0002
LOAD SCRATCH, ZEROS
;Load Backspace characters into scratch
LOAD NEWLINE, CR
STORE NEWLINE, 0010
LOAD NEWLINE, LF
STORE NEWLINE, 0011
LOAD NEWLINE, 0010
;Load 'I WILL ECHO' into scratch
LOAD BANNER, I
STORE BANNER, 0020
LOAD BANNER, SPACE
STORE BANNER, 0021
LOAD BANNER, W
STORE BANNER, 0022
LOAD BANNER, I
STORE BANNER, 0023
LOAD BANNER, L
STORE BANNER, 0024
LOAD BANNER, L
STORE BANNER, 0025
LOAD BANNER, SPACE
STORE BANNER, 0026
LOAD BANNER, E
STORE BANNER, 0027
LOAD BANNER, C
STORE BANNER, 0028
LOAD BANNER, H
STORE BANNER, 0029
LOAD BANNER, O
STORE BANNER, 002A
LOAD BANNER, CR
STORE BANNER, 002B
LOAD BANNER, LF
STORE BANNER, 002C
LOAD BANNER, 0020
LOAD FLAG, ONE
ENINT

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MAIN ADD R0, ZEROS ;MAIN LOOP
JUMP MAIN
ADDRESS 0300
ISR INPUT STATUS, 0001 ;Input Status Flags
AND STATUS, FLAG_BITS ;Mask Status
COMP STATUS, BOTH_FLAGS ;If Both are HIGH -- Jump
JUMPZ BOTH
COMP STATUS, RX_FLAG ;If Rx Flag is HIGH -- Jump
JUMPZ RX
COMP STATUS, TX_FLAG ;If Tx Flag is HIGH -- Jump
JUMPZ TX
RETEN
BOTH COMP DEL_FLAG, ONE
JUMPZ DEL ;If Delete Flag is HIGH -- Jump
COMP NL_FLAG, ONE
JUMPZ NLCHECK ;If New Line Flag is HIGH -- Jump
COMP PROM_FLAG, ONE
JUMPZ CHECK_Z ;If Prompt Flag is HIGH -- Jump
INPUT DATA, 0000
COMP DATA, 007F
JUMPNZ PROM_COMP ;If DATA is NOT Backspace -- Jump
LOAD DEL_FLAG, ONE ;Assert DEL_FLAG
COMP ADDR_16LB, ZEROS
JUMPNZ DEC_MEM ;If Lower Addr is NOT 0000 -- Jump
COMP ADDR_7UB, ZEROS
JUMPZ DEL ;If Upper Address is 0000 -- Jump
SUB ADDR_7UB, ONE ;Else Decrement Upper Address
DEC_MEM SUB ADDR_16LB, ONE ;Decrement Lower Address
JUMP DEL ;Unconditional Jump to DEL
PROM_COMP COMP DATA, ASTERICK
JUMPNZ ECHO ;If NOT "*" input -- Jump
LOAD PROM_FLAG, ONE ;Else Set Prompt Flag
LOAD NL_FLAG, ONE ; and New Line Flag
JUMP NLCHECK ;Unconditional Jump to NLCHECK
ECHO OUTPUT ADDR_7UB, 0011 ;Output Upper Address to MICRON
OUTPUT ADDR_16LB, 0012 ;Output Lower Address to MICRON
OUTPUT DATA, 0013 ;Write Data Out Register
OUTPUT DATA, 0016 ;Perform Memory Write
OUTPUT DATA, 0000 ;Output Received Data to S/T
LOAD FLAG, ZEROS ;Clear FLAG
COMP ADDR_16LB, FFFF
JUMPNZ DONT_IUB ;If Lower Addr is NOT FFFF -- Jump
ADD ADDR_7UB, ONE ;Else increment Upper Address
DONT_IUB ADD ADDR_16LB, ONE ;Increment Lower Adddress
RETEN
RX INPUT DATA, 0000 ;Input Data
COMP DATA, 007F
JUMPNZ CONT ;If DATA is NOT 007F -- Jump

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LOAD DEL_FLAG, ONE ;Assert DEL_FLAG
COMP ADDR_16LB, ZEROS
JUMPNZ DEC_MEM2 ;If Lower Address -- Jump
COMP ADDR_7UB, ZEROS
JUMPZ DEL ;If Upper Address -- Jump
SUB ADDR_7UB, ONE ;Else Decrement Upper Address
DEC_MEM2 SUB ADDR_16LB, ONE ;Decrement Lower Address
CONT COMP DATA, ASTERICK
JUMPNZ CONT2 ;If NOT "*" -- Jump
LOAD PROM_FLAG, ONE ;Assert PROMPT FLAG
CONT2 LOAD FLAG, ONE ;Assert FLAG
OUTPUT ADDR_7UB, 0011 ;Output Upper Address
OUTPUT ADDR_16LB, 0012 ;Output Lower Address
OUTPUT DATA, 0013 ;Write to Data Register
OUTPUT DATA, 0016 ;Perform Memory Write
COMP ADDR_16LB, FFFF
JUMPNZ DONT_IUB2 ;If Upper Addr is NOT FFFF -- Jump
ADD ADDR_7UB, ONE ;Else Increment Upper Address
DONT_IUB2 ADD ADDR_16LB, ONE ;Increment Lower Address
JUMP RETURN ;Unconditional Jump to RETURN
TX COMP BAN_FLAG, ONE
JUMPZ BAN_OUT ;If Banner Flag -- Jump
COMP DEL_FLAG, ONE
JUMPZ DEL ;If DEL Flag -- Jump
COMP NL_FLAG, ONE
JUMPZ NLCHECK ;If New Line Flag -- Jump
COMP PROM_FLAG, ONE
JUMPZ CHECK_Z ;If Prompt Flag -- Jump
COMP FLAG, ZEROS
JUMPZ RETURN ;If FLAG is 0000 -- Jump
OUTPUT DATA, 0000 ;Else Output DATA
LOAD FLAG, ZEROS ;Clear FLAG
JUMP RETURN
BAN_OUT FETCH BAN_DATA, BANNER ;Fetch Banner ASCII Values
OUTPUT BAN_DATA, 0000 ;Output to S/T
ADD BANNER, ONE ;Increment Banner Address
COMP BANNER, 002D
JUMPNZ RETURN ;If Banner Address is 002D -- Jump
LOAD BAN_FLAG, ZEROS ;Clear Banner FLAG
RETEN
DEL FETCH DATA, SCRATCH ;Fetch DATA ASCII Values
OUTPUT DATA, 0000 ;Output DATA to S/T
ADD SCRATCH, ONE ;Increment SCRATCH Address
COMP SCRATCH, 0003
JUMPNZ RETURN ;If Scratch is 0003 -- Jump
LOAD SCRATCH, ZEROS ;Reload Scratch with 0000
LOAD DEL_FLAG, ZEROS ;Clear DEL_FLAG FLAG
RETEN

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NLCHECK COMP NL_FLAG, ONE
JUMPNZ CHECK_Z ;If NOT New Line Flag -- Jump
FETCH DATA, NEWLINE ;Fetch NEWLINE Values
OUTPUT DATA, 0000 ;Output Values to S/T
ADD NEWLINE, ONE ;Increment NEWLINE Address
COMP NEWLINE, 0012
JUMPZ NL_RESET ;If NEWLINE is 0012 -- Jump
RETEN
CHECK_Z COMP ADDR_7UB, 0000
JUMPNZ PROMPT ;If COUNTER_UB is NOT 0000 -- Jump
COMP ADDR_16LB, 0000
JUMPNZ PROMPT ;If COUNTER_LB is NOT 0000 -- Jump
LOAD PROM_FLAG, ZEROS
RETEN
PROMPT COMP PROM_FLAG, ONE
JUMPNZ RETURN ;If Prompt Flag is NOT HIGH -- Jump
OUTPUT COUNTER_UB, 0011 ;Output Upper to MICRON
OUTPUT COUNTER_LB, 0012 ;Output Lower to MICRON
INPUT MEM_DATA, 0015 ;Perform Memory Read
SCHECK INPUT STATUS, 0001 ;Check Status
AND STATUS, 0002 ;Mask Tx Ready
COMP STATUS, 0002
JUMPNZ SCHECK ;If Tx Rdy is NOT HIGH -- Jump
INPUT MEM_DATA, 0014 ;Else input data
OUTPUT MEM_DATA, 0000 ;Output Data to S/T
INC_MEM COMP COUNTER_LB, FFFF
JUMPNZ DONT_ICUB ;If Lower is not full -- Jump
ADD COUNTER_UB, ONE ;Else Increment Upper
DONT_ICUB ADD COUNTER_LB, ONE ;Increment Lower
COMP COUNTER_UB, ADDR_7UB
JUMPNZ RETURN ;If addr, count NOT equal -- Jump
COMP COUNTER_LB, ADDR_16LB
JUMPNZ RETURN ;If addr, count NOT equal -- Jump
LOAD ADDR_7UB, ZEROS ;Clear Addresses and Counters
LOAD ADDR_16LB, ZEROS
LOAD COUNTER_UB, ZEROS
LOAD COUNTER_LB, ZEROS
LOAD PROM_FLAG, ZEROS
LOAD NL_FLAG, ONE ;Set New Line Flag
RETEN
NL_RESET LOAD NEWLINE, 0010 ;Load Flag
LOAD NL_FLAG, ZEROS ;Clear Flag
RETEN
RETURN RETEN
ADDRESS 0FFE
JUMP ISR
END

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5. Externally Developed Blocks
5.1. Asynchronous In, Synchronous Out (AISO)
Description
This block ensures the reset to every
block‟s reset is synchronous to each other
hence the name. The reset of this block is
directly connected to a button (BTNC), which
when asserted will synchronously reset every
module.
I/O
Signal I/O Connected to
clk_in Input 100MHz Crystal Oscillator
reset Input BTNC
sync Output Every Block‟s Reset
Table 12: AISO I/O
Register Map
Register Usage Description
flop [1:0] Synchronize Upon reset, sends a single pulse to all modules
Table 13: AISO Register Map
Source Code: Appendix A17
Figure 10: AISO Block Diagram

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5.2. TramelBlaze
Description
The TramelBlaze is a 16-bit soft-
core microcontroller that emulates the
PicoBlaze. The TramelBlaze provides the
instantiation for a ROM, which it will read
from and perform actions based on the
instructions provided by the ROM. In this
application, the TramelBlaze utilize every
port in order to receive ASCII values and
to transmit ASCII values to a Serial
Terminal. The READ_STROBE and
WRITE_STROBE will be outputted to
UART which will help the UART
determine whether to use the Transmit or
Receive Engine during a specific operation.
I/O
Signal I/O Connected to
IN_PORT [15:0] Input UART
CLK Input 100MHz Crystal Oscillator
INTERRUPT Input RS Flop
RESET Input AISO
OUT_PORT [15:0] Output UART
PORT_ID [15:0] Output UART & In_Sel MUX
INTERRUPT_ACK Output RS Flop
READ_STROBE Output UART
WRITE_STROBE Output UART
Table 14: TramelBlaze I/O
Register Map
Register Usage Description
R[15:0] PROM Functions individually in TramelBlaze PROM
Table 15: TramelBlaze Register Map
Figure 11: TramelBlaze Block Diagram

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6. Internally Developed Blocks
6.1. Core
Description
Implemented in Revision 4.0, the Core compiles the processor and its interfaces in one
large instantiation. Any signals that interacts with the Core in any way must go through the TSI
first. In this design, the Core consists of the externally developed TramelBlaze, and internally
developed Full UART and MIB, these modules interact as seen in Figure 12. Aside from the
main components, the core also instantiates some accessory components as well, such as the
AISO to provide a synchronous reset to all modules, and a Pulse Maker and RS Flop to handle
the TramelBlaze‟s interrupts.
Figure 12: Core Top Module & Core Interface Interactions

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I/O
All Inputs and Outputs state in this table are connected to the TSI before interacting with
other components of the FPGA.
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I On-board Button – BTNC
Rx_In 1 I USB
mem_data_in 16 I Micron Memory
Baud_Sel 4 I On-board switches
Parity_ops 3 I On-board switches
mem_addr 23 O Micron Memory
mem_data_out 16 O Micron Memory
IOBUF_T_LoE 1 O TSI
CE_LoE 1 O Micron Memory
WE_LoE 1 O Micron Memory
OE_LoE 1 O Micron Memory
ADV_LoE 1 O Micron Memory
CRE_HiE 1 O Micron Memory
UB_LoE 1 O Micron Memory
LB_LoE 1 O Micron Memory
Tx_Out 1 O USB
status 8 O On-board LEDs
mem_clk 1 O Micron Memory
Table 16: Core I/O
Source Code: Appendix A2

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6.1.1. Memory Interface Block (MIB)
Description
The MIB consists of two major components, the state machine and the control flops. The
state machine sends the appropriate signals based on what it has receives in terms of Port ID. The
state machine allows the signals to be one of three configurations, IDLE, MEMREAD, and
MEMWRITE, and these states control the signals CE#, WE#, OE#, and T. With the signals
being sent, the control flops of the state machine manage the memory addresses and the data
coming to and from the Micron Memory. From this point, the TramelBlaze‟s ROM controls the
timing in when to send the memory address location and went to send or receive data.
Figure 13: MIB Top Module

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I/O
Signal Size (bits) I/O Connected to
clk 1 I 100MHz Crystal Oscillator
reset 1 I AISO
Read 1 I TramelBlaze
Write 1 I TramelBlaze
Port_ID 16 I TramelBlaze
mem_data_in 16 I Micron Memory
TB_outport 16 I TramelBlaze
CE_LoE 1 O Micron Memory
WE_LoE 1 O Micron Memory
OE_LoE 1 O Micron Memory
IOBUF_T_LoE 1 O TSI
ADV_LoE 1 O Micron Memory
CRE_HiE 1 O Micron Memory
UB_LoE 1 O Micron Memory
LB_LoE 1 O Micron Memory
mem_addr 23 O Micron Memory
mem_data_out 16 O Micron Memory
TB_inport 16 O TramelBlaze
Table 17: MIB I/O
Register Map
Register Module Description
CE_LoE MIB Chip Enable Signal for Micron Memory
WE_LoE MIB Write Enable Signal for Micron Memory
OE_LoE MIB Output Enable Signal for Micron Memory
IOBUF_T_LoE MIB Controller for IOBUF in TSI
ADV_LoE MIB Address Valid Signal for Micron Memory
CRE_HiE MIB Control Register Enable Signal for Micron Memory
UB_LoE MIB Upper Byte Signal for Micron Memory
LB_LoE MIB Lower Byte Signal for Micron Memory
mem_addr MIB Memory Address location
mem_data_out MIB Data sent to Micron Memory
TB_inport MIB Data sent to TramelBlaze
state MIB State of MIB state machine
next_state MIB Next state of MIB state machine
WCLK MIB Counter to stay in write state for 130ns
RCLK MIB Counter to stay in read state for 130ns
nCE_LoE MIB Next state of Chip Enable
nWE_LoE MIB Next state of Write Enable
nOE_LoE MIB Next state of Output Enable
nIOBUF_T_LoE MIB Next state of T

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nADV_LoE MIB Next state of Address Valid
nCRE_HiE MIB Next state of Control Register Enable
nUB_LoE MIB Next state of Upper Byte
nLB_LoE MIB Next state of Lower Byte
WA_R0 MIB Register to store and send Upper Byte
WA_R1 MIB Register to store and send Lower Byte
WD_R MIB Register to store and send character to Micron Memory
RD_R MIB Register to store and receive character from Micron Memory
Table 18: MIB Register Map
State Machine
Figure 14: MIB State Machine
This state machine is representative how the MIB‟s state machine works. Both WClk and
RClk are used to stay in that state for at 120ns.
Source Code: Appendix A3
Verification
Figure 15: MIB Verification
This verification was created by connecting the project to a module cell ram that
simulates the working behavior of the Micron Memory. At the bottom, the registers are taking
the correct data, especially when an asterisk (ASCII value: 2A) is received. The values are then
seen taken to the TramelBlaze and outputted onto the Transmit line.

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6.1.2. Universal Asynchronous Receiver and Transmitter (UART)
Description
The UART consists of three components, the Transmit Engine and Baud Rate Decoder
from Revision 2.0, and the Receive Engine developed in Revision 3.0. The Transmit Engine is
responsible for shifting data out to the Transmit Line of the USB, while the Receive Engine is
responsible for shifting data into its register before outputting them to the TramelBlaze to be
processed. Both these Engines require a Baud Rate which is provided by a user inputted 4-bit
value that will translate to appropriate values that dictate the speed of transmitting and receiving
data.
An Interrupt signal is also implemented in the UART to cause the TramelBlaze to enter
the Interrupt Service Routine. The Interrupt signal named UART_Interrupt is asserted whenever
either the Transmit Engine or the Receive Engine are ready to work.
Figure 16: UART Top Module

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Detailed Block Diagram
Figure 17: UART Detailed Block Diagram

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I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
Port_ID 16 I TramelBlaze
Data_in 8 I TramelBlaze
Rate_Sel 4 I Baud Rate Decoder
Parity_ops 3 I On-Board Switches
write_strobe 1 I TramelBlaze
read_strobe 1 I TramelBlaze
Rx_In 1 I USB
Rx_Out 10 O TramelBlaze
Status 8 O TramelBlaze & On-Board LEDs
UART_Interrupt 1 O Pulse Maker
Tx_Out 1 O USB
Table 19: UART I/O
Source Code: Appendix A4

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6.1.2.1. Transmit Engine
Description
The Transmit Engine is comprised of five major components, the Transmit Bit Time
Counter, the Transmit Bit Counter, the Transmit Controller, the Bit Decoder and the Transmit
Shift Register. On a Transmit Engine level, these individual components work together in
achieving the goal of shifting data out to the Transmit Line. The first component, the Bit Time
Counter determines the speed at which the Engine can shift out data; the speed is ultimately
determined by the value provided by the Baud Rate Decoder of the UART. Next, the bit count
ensures that the Engine will only shift out 11 bits of data. The Bit Decoder takes in Data values
received by the Controller and determine the values that enter the 10th
and 9th
bit of the shift
register based on the Parity Options. The Shift Register concatenates the values from the Parity
Selector and Controller with 0 and 1, before shifting those values out from the LSB to MSB. All
of the previously mentioned components are controlled by the Controller. The Controller
consists of three flops that send signals to the Bit Time Counter, Bit Count, Shift Register and
UART Interrupt.
Figure 18: Transmit Engine Top Module

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Detailed Block Diagram
Figure 19: Transmit Engine Detailed Block Diagram

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I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
ld_in 1 I Write Strobe & Port ID
Baud_Rate 19 I Baud Rate Decoder
Data_in 8 I TramelBlaze
Parity_ops 3 I On-Board Switches
Tx_Rdy 1 I UART Interrupt
Tx_Out 1 I USB
Table 20: Transmit Engine I/O
Register Map
Register Module Description
count [18:0] Time_Counter Baud Rate Counter
count [3:0] Bit_Count Fixed number on how many times shift register can shift
Tx_Rdy Controller Acknowledge that Transmission is Ready
Load_D1 Controller Delays data to reach DoIt and Shift Register for one clock period
DoIt Controller Allows Bit Count and Bit Time Counter to increment
D_out [7:0] Controller Takes in Data from TramelBlaze
bit_10_9 Bit Decoder Determines what bit 10 and 9 of shift register will do
register [10:0] Shift Register Prepare data to be shifted out to a designated pin
SD0 Shift Register Takes in Data from TramelBlaze
Table 21: Transmit Engine Register Map
Source Code: Appendix A5
Verification
Figure 20: Transmit Engine Verification
The Transmit Engine is able to shift out data through the Tx_out line in accordance to the
requirements. This was done by giving the Transmit Engine different values, different Baud
Rates, and different Parity options to ensure that It was shifting out data properly.

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Components
 Transmit Bit Count
Description
The Transmit Bit Count holds the
responsibility of ensuring that the shift register
shifts out only 11 bits a time during transmission.
This is achieved through creating a flop that will
increment every time the Transmit Bit Time
Counter and Controller sends the appropriate
signals.
In Revision 3.0, the bit count had to be
changed to 12 in order to accommodate for the lack
of a STOP bit when both Eight and Parity Enable
options were selected.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
DOIT 1 I Tx Controller
BTU 1 I Tx Bit Time Counter
DONE 1 O Tx Controller
Table 22: Transmit Bit Count I/O
Source Code: Appendix A6
Verification
Figure 22: Transmit Bit Count Verification
The Test Bench shows that as soon as the value equals to 11, DONE is asserted to signify
that every bit has been shifted out.
Figure 21: Transmit Bit Count Module

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 Transmit Bit Time Counter
Description
The Transmit Bit Counter controls the
speed at which the system runs at. A Baud
Rate value is inputted into the module and it
will increment to that value as long as the
Controller allows it to. Given that the value
equates the Baud Rate value, it will assert its
signal, BTU, and reset the count back to 0.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
DOIT 1 I Tx Controller
Baud_Rate 19 I Global Input
BTU_Out 1 O Tx Shift Register & Bit Count
Table 23: Bit Time Counter I/O
Source Code: Appendix A7
Verification
Figure 24: Bit Time Counter Verification
The Test Bench shows that as soon as count is equal to 109, BTU_out is asserted for one
clock cycle before the count is reset to 0.
Figure 23: Transmit Bit Time Counter Module

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 Transmit Controller
Description
The Transmit Controller comprises of
two RS flops and two D flop. A Tx_Rdy RS flop
that tells the processor that the Engine is ready to
be utilized. A delay D flop to stall the load to the
Shift Register. A DoIt RS Flop that allows the
two counters to count. And an 8-bit load register
that take in data from the TramelBlaze and
transmit them to the Bit Decoder and Transmit
Shift Register.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
done 1 I Tx Bit Count
load 1 I Write Strobe & Port ID
Out_Port 8 I TramelBlaze
Tx_rdy 1 O Pulse Maker
Load_D1 1 O Transmit Shift Register
DoIt 1 O Tx Bit Count & Bit Time Counter
D_out 8 O Tx Shift Register & Bit Decoder
Table 24: Transmit Controller I/O
Source Code: Appendix A8
Verification
Figure 26: Transmit Controller Verification
This Test Bench shows the verification of the three flops. It shows that upon reset, Tx_rdy
remains high contrary to the Load_D1 and DoIt signal. When the load signal is asserted, Tx_rdy
goes low while the other two go high, and Out_Port takes up the test value. When done is
asserted, all flops go back to their original state.
Figure 25: Transmit Controller Module

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 Bit Decoder
Description
The Bit Decoder determines the
values that will be placed in the 10th
and 9th
bit location of the Transmit Shift Register.
This is entirely based on the values of the
Eight, Parity Enable, and oHeL lines which
are taken directly from the Nexys 4‟s on-
board switches. Table 25 provides the True
Table logic for the decoder.
Eight Parity oHeL 10 9
0 0 0 1 1
0 0 1 1 1
0 1 0 1 ^Data [6:0]
0 1 1 1 ~^Data [6:0]
1 0 0 1 Data [7]
1 0 1 1 Data [7]
1 1 0 ^Data [7:0] Data [7]
1 1 1 ~^ Data [7:0] Data [7]
Table 25: Bit Decoder Truth Table
I/O
Signal Size (bits) I/O Connected to
Reg8_in 8 I Tx Controller
bits_parity_oHeL 3 I On-board Switches
bit_10_9 2 O Tx Shift Register
Table 26: Bit Decoder I/O
Source Code: Appendix A9
Verification
Figure 28: Bit Decoder Verification
This Test Bench proves how the different options work with the same data of 8H‟9E.
Figure 27: Bit Decoder Module

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 Transmit Shift Register
Description
The Transmit Shift Register is responsible
for taking in data from the Controller and Bit
Decoder and shifting it out based on the speed of
the Baud Rate. While shifting data out to the USB
line, it shifts in 1‟s to signify the inactive behavior
of the Engine when data is not being transmitted.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
load 1 I Tx Controller
shift_en 1 I Tx Bit Time Counter
S_Data_in 1 I 1‟b1
D_in 11 I Bit Decoder, Tx Controller, 2‟b01
SD0 1 O USB
Table 27: Transmit Shift Register I/O
Source Code: Appendix A10
Verification
Figure 30: Transmit Shift Register Verification
This Test Bench shows the signal load allowing sample data 11‟b555 loading into
register. It also shows how register is shifting data out to SD0 while being filled in with 1‟s.
Figure 29: Transmit Shift Register Module

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6.1.2.2. Receive Engine
Description
Like the Transmit Engine, the Receive Engine comprises of five major components, the
Receive Bit Time Counter, State Machine, Receive Bit Count, Receive Controller, and Receive
Shift Register. Individually, there are many components that are almost identical to those of the
Transmit Engine, but every component was modified to allow this part of the design to receive
data rather than to transmit data. The first component, the State Machine, determines when the
Receive Engine will work. It is also used to detect the Start Bit of the Transmitter to allow the
Engine to manipulate values that run into the Bit Time Counter and Bit Count. Next, the Bit
Time Counter, controls the speed at which the Receive Engine operates at. The speed is
determined entirely by the Baud Rate Decoder of the UART. Additionally, whenever the State
Machine detects a Start bit, the value of the Baud Rate will temporarily be divided by 2 to
calibrate the Engine in a way that allows it to pick up values at the halfway mark of every bit.
The Receive Bit Count is essentially the same as the Transmit Bit Count, but rather than be given
a fixed value of how many bits to count, it entirely depends on whether the Transmitter is
sending seven or eight bits and whether there will be a parity sent or not. The Receive Controller
takes care of two responsibilities, the first is to send a signal to let the processor know it is ready
to receive values and the second is to take the value received and to check for errors. Lastly, the
Receive Shift Register is similar to the Transmit Shift Register, except that it will output two; a
ten-bit value sent to the controller to check for errors, and an eight-bit value that will be sent
straight to the TramelBlaze for processing.
Figure 31: Receive Engine Top Module

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Detailed Block Diagram
Figure 32: Receive Engine Detailed Block Diagram

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I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
Rx_In 1 I USB
Eight 1 I On-Board Switches
Parity_En 1 I On-Board Switches
oHeL 1 I On-Board Switches
read_strobe 1 I TramelBlaze
Rate 19 I Baud Rate Decoder
Port_ID 16 I TramelBlaze
Rx_Rdy 1 O UART Interrupt
Parity_Err 1 O On-Board LED
Frame_Err 1 O On-Board LED
Overflow 1 O On-Board LED
Rx_Data_TB 8 O TramelBlaze
Table 28: Receive Engine I/O
Register Map
Register Module Description
count [18:0] Rx Time Counter Baud Rate Counter
Start State Machine Detection of a Start bit
DOIT State Machine Allows Counter to count
State [1:0] State Machine Current position in receiving
next_state [1:0] State Machine Holds value of next state
next_Start State Machine Holds value of next Start
next_DOIT State Machine Holds value of next DOIT
count [3:0] Rx Bit Count Fixed number on how many times shift register can shift
bits [3:0] Rx Bit Count Based on Parity Options, determines compare value
Rx_Rdy Rx Controller Signify readiness to take in data
Parity_Err Rx Controller If asserted, generate Parity does not match received
Frame_Err Rx Controller Stop Bit not detected
Overflow Rx Controller Too much information
F_Check Rx Controller Holds last value received by Shift Register
Data_Ctrl [9:0] Rx Shift Register Data sent to Rx Controller
Data_TB [7:0] Rx Shift Register Data sent to TramelBlaze
Data_Out [9:0] Rx Shift Register Raw Data shifted from Transmitter
Table 29: Receive Engine Register Map
Source Code: Appendix A11

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Verification
Figure 33: Receive Engine Verification
Testing the Receive Engine required using the ROM from the previous Revision and
Transmit Engine to feed the Transmit line into the Receive line. This was done to simulate data
entering and being processed by the Receive Engine. This Test Bench demonstrates a working
Receive Engine that is able to accurately detect when the Start bit occurs. Simultaneously, it able
to properly shift in the Transmit line data and re-map the data according to where it needs to be
sent off to.

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Components
 Receive Shift Register
Description
The Receive Shift Register is responsible for
taking in the data from the Rx Line and shifting them
into a register. Because of the Eight and Parity Enable
switch, the register values need to be re-mapped
accordingly. The raw value is copied into two separate
registers, Data_Ctrl and Data_TB. Data_Ctrl is the data
sent to the Controller that consists of every bit of
information to calculate any errors. Data_TB is the data
sent to the TramelBlaze, and this consists of only the
ASCII value that was sent. This data is extracted using a
combinational block that will shift the value further and
fill the unnecessary information with 0‟s.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
BTU 1 I Rx Bit Time Counter
Start 1 I State Machine
Rx_In 1 I USB
Eight 1 I On-board Switches
Parity_En 1 I On-board Switches
Data_Ctrl 10 O Rx Controller
Data_TB 8 O TramelBlaze
Table 30: Receive Shift Register I/O
Source Code: Appendix A12
Verification
Figure 35: Receive Shift Register Verification
The Verification shows when Shift Enable is asserted, Data_Out takes in Rx_In value at
every positive edge of the clock. The data is also shifted according in Data_Ctrl and Data_TB.
Figure 34: Receive Shift Register Module

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 State Machine
Description
The Receive Engine State Machine determines
the state of the signal it is receiving. In Figure 30, it is
illustrated to show how the data in this machine flows.
The Start bit is most significant bit of information the
State Machine needs to detect. It allows the Engine to
enter the second state and allows itself to prepare for the
on-coming data. Once this bit has been detected, the
State Machine allows the counters to count and begins
collection. Once the Bit Count has received the
necessary number of bits, it will return to the IDLE state
and it will wait for the next Start bit.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
Rx_Line 1 I USB
BTU 1 I Rx Bit Time Counter
DONE 1 I Rx Bit Count
Start 1 O Rx Bit Time Counter
DOIT 1 O Rx Bit Time Counter & Rx Bit
Count
Table 31: Receive State Machine I/O
State Machine
Figure 36: Receive State Machine Module
Figure 37: Receive State Machine

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Source Code: Appendix A13
Verification
Figure 38: Receive State Machine Verification
Figure 31‟s Test bench demonstrates the State machine at work. During the correct states,
Start and DOIT are on at the appropriate times. As this was a rough test, the States continue to
cycle through one another because Rx_Line is consistently low, while BTU is consistently high.

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 Receive Controller
Description
The Receive Controller consists of multiple RS
flops, all with a different purpose. The first flop sends out
a signal called Rx_Rdy which is asserted whenever the
Engine is done receiving data from the Transmitter. When
active, this signal asserts the interrupt to the TramelBlaze.
Next, the Parity_Err flop is a signal sent to one of the
Nexys 4‟s on-board LEDs. The LED turns on whenever
the generated parity does not match the received parity,
which indicates that there is an error in the transmission.
Next, the Frame_Err flop sends a signal to the LEDs
whenever the Stop bit is not detected after a transmission.
Lastly, the Overflow flop sends a signal to the LEDs
whenever a Stop bit has occurred but there is still more
data coming in. These signals allow any user to be able to
detect the errors that may occur during the transmission of
data to the Receive Engine.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
DONE 1 I Rx Bit Count
Clear 1 I Read Strobe & Port ID
Eight 1 I On-board Switches
Parity_En 1 I On-board Switches
Even 1 I On-board Switches
D_In 10 I Shift Register
Rx_Rdy 1 O TramelBlaze
Parity_Err 1 O On-board LEDs
Frame_Err 1 O On-board LEDs
Overflow 1 O On-board LEDs
Table 32: Receive Controller I/O
Source Code: Appendix A14
Figure 39: Receive Controller Module

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Verification
 Rx_Rdy Signal
Figure 40: Receive Ready Signal Verification
The Rx_Rdy signal is an RS flop which takes in two inputs to set and reset the value.
Whenever DONE is asserted, the Rx_Rdy signal goes high, but the Clear signal has priority over
DONE, which causes it to stay low as long as Clear is high.
 Parity Error Signal
Figure 41: Parity Error Verification (working)
In this first test, the module was given a test signal of 10‟B11_1001_0011 at 8-bits and
odd parity enabled. It was able to pass the test with no issues as the test signal was correct.
Figure 42: Parity Error Verification (not working)
To test whether the Parity Error signal worked, the same signal was sent in this test but
rather than sending an odd parity, an even parity was requested. Because it was the same signal,
the Parity Error signal went high, as the Generated Parity did not match up with the Received
Parity.

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 Framing Error Signal
Figure 43: Framing Error Verification (working)
Framing Error tested whether a Stop bit was detected or not. The same example from
Parity Error was run through the Framing Portion, and it detected no framing error because the
two most significant bits were 1‟s
Figure 44: Framing Error Verification (not working)
To ensure Framing Error was in working condition, the two most significant bits were
changed to 0‟s to simulate the nonoccurrence of a Stop bit. Once the flop detected this, the Error
was asserted.
 Overflow Signal
Figure 45: Overflow Error Verification (working)
Overflow occurs whenever DONE and Rx_Rdy are both asserted at the same time, as
neither of them are not asserted at this time. Overflow does not occur.
Figure 46: Overflow Error Verification (not working)
Once both are them are asserted at the same time, an Overflow does occur as the Test
Bench demonstrates.

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 Receive Bit Count
Description
The Receive Bit Count behaves similarly to the
Transmit Bit Count, where it counts the number of bits to
ensure that the Engine is picking up the correctly number of
bits. But in addition to this, the Engine is also tasked with the
responsibility of changing the compared values due to the
difference in how many bit needs to received based on the
Eight and Parity Enable options. Table 33 shows the truth
table behind how it many needs to be detected.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
DOIT 1 I State Machine
BTU 1 I Rx Bit Time Counter
Eight 1 I On-board Switches
Parity_En 1 I On-board Switches
DONE 1 O State Machine & Rx Controller
Table 33: Receive Bit Count I/O
Table 34: Receive Bit Count Truth Table
Source Code: Appendix A15
Verification
Figure 48: Receive Bit Count Verification
This Test Bench shows the Bit Count working with an option of 8-bits. It matches the
truth table above and allows the Receive Engine to sample 10 bits before asserting.
Eight Parity Bits
0 0 9
0 1 10
1 0 10
1 1 11
Figure 47: Receive Bit Count Module

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 Receive Bit Time Counter
Description
The Receive Bit Time Counter is
similar to the Transmit Bit Time Counter,
where it determines the speed at which the
Engine runs based off of the value inputted
by the Baud Rate Decoder. The difference
between the two Bit Time Counters is that
the Receive Engine does not hold the same
value whenever it receives a bit. Whenever
the Engine detects a Start Bit, the value of
the Baud Rate will temporarily be divided
by two so that the Receive Engine can
sample the transmitted data at the half way
mark of every bit. This allows the Engine
to accurately pick up data and allows room
for any sort of drift.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
reset 1 I AISO
DOIT 1 I State Machine
Start 1 I State Machine
Baud_Rate 19 I Baud Rate Decoder
BTU 1 O Tx Bit Count, State Machine & Tx
Shift Register
Table 35: Receive Bit Time Counter I/O
Source Code: Appendix A16
Verification
Figure 50: Receive Bit Time Counter Verification
This Test Bench shows the change in Baud Rate when the Start signal goes high. As soon
as Start is asserted, Rate changes immediately.
Figure 49: Receive Bit Time Counter Module

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6.1.3. Baud Rate Decoder
Description
The Baud Rate Decoder is a 4-bit
Decoder that determines the speed at which the
Transmit and Receive Engine run at.
I/O
Signal Size (bits) I/O Connected to
Rate_Sel 4 I R6, R7, U8, U9
Baud_Rate 19 O Transmit Engine
Table 36: Baud Rate Decoder I/O
Register Map
Register Usage Description
Baud_Rate
[18:0]
Constant Change the constant that Bit Time Counter compares to
Table 37: Baud Rate Decoder Register Map
Source Code: Appendix A17
Verification
Figure 52: Baud Rate Decoder Verification
The Baud Rate Decoder proves that it is working properly by associating the correct
value with the correct switch orientation.
Figure 51: Baud Rate Decoder Module

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6.1.4. Pulse Maker
Description
This block generates a one clock period
pulse whenever a signal is asserted. With two D
flops inside, it is able to take the signal and generate
a one clock period pulse to the output. In this
application, The D_in input will take in an interrupt
signal from the UART and it will set the Interrupt
through the pulse and sent it over to an RS flop,
which manages the interrupt of the TramelBlaze.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
D_in 1 I UART
reset 1 I AISO
pulse 1 O RS Flop (S)
Table 38: Pulse Maker I/O
Register Map
Register Usage Description
flop [1:0] Pulse Create a one clock cycle pulse when flop [1:0] = [0, 1]
Table 39: Pulse Maker Register Map
Source Code: Appendix A19
Verification
Figure 54: Pulse Maker Verification
This Test bench proves that the Pulse Maker is working properly, it is only sends a one
clock period pulse regardless of how long the signal may be.
Figure 53: Pulse Maker Module

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6.1.5. RS Flop
Description
The RS Flop module exactly models how an RS Flop
works. Through the S input, the RS Flop is connected to the
Pulse Maker, which sets D_out high whenever this input is
asserted. On the contrary, the R input is connected to the
TramelBlaze‟s Interrupt Acknowledge, which when asserted
will clear the value of D_out and cause it to go to low.
This module is also used to manage the Transmit
Ready and Receive ready before they enter the Pulse Maker.
I/O
Signal Size (bits) I/O Connected to
clk_in 1 I 100MHz Crystal Oscillator
R 1 I TramelBlaze
Reset 1 I AISO
S 1 I Pulse Maker
D_out 1 O TramelBlaze
Table 40: RS Flop I/O
Register Map
Register Usage Description
D_Out Interrupt Send interrupt when S is asserted
Table 41: RS Flop Register Map
Source Code: Appendix A20
Verification
Figure 56: RS Flop Verification
This Test Bench shows a working RS Flop. It is set high whenever S is asserted but R
will deassert the value while also having priority over S.
Figure 55: RS Flop Module

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6.2. Technology Specific Instantiation (TSI)
Description
The TSI is a newly developed block in Revision 4.0, that combined with the Core
provides a more organized and chip specific design. With the TSI, the design is improved by
providing easier access to I/O cells that are more specific towards the chip‟s design. In this
design, the usage of an IOBUF was necessary to be able to access the memory through a
bidirectional wire. Without this type of buffer, the design would not be able to access the
memory as it does.
Figure 57: TSI Top Module

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I/O
Signal Size (bits) I/O Connected to
clkI 1 I 100MHz Crystal Oscillator
resetI 1 I On-board Buttons -- BTNC
switchesI 7 I On-board Switches
clk 1 O Core
reset 1 O Core
Switches 7 O Core
Tx 1 I UART
Rx_I 1 I UART
Tx_O 1 O USB
Rx 1 O USB
MEM_A 23 I MIB
status 8 I UART
mem_clk 1 I Always Logic „0‟
CE 1 I MIB State Machine
WE 1 I MIB State Machine
OE 1 I MIB State Machine
ADV 1 I Always Logic „0‟
CRE 1 I Always Logic „0‟
UB 1 I Always Logic „0‟
LB 1 I Always Logic „0‟
MEM_A_O 23 O Micron Memory
statusO 8 O On-board LEDs
mem_clk_O 1 O Micron Memory
CE_O 1 O Micron Memory
WE_O 1 O Micron Memory
OE_O 1 O Micron Memory
ADV_O 1 O Micron Memory
CRE_O 1 O Micron Memory
UB_O 1 O Micron Memory
LB_O 1 O Micron Memory
MIB_T 1 I MIB State Machine
MIB_I 16 I MIB
MIB_O 16 O MIB
MIB_IO 16 IO Micron Memory
Table 42: TSI I/O
Source Code: Appendix A21

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7. Chip Level Verification
7.1. Revision 2.0: Transmit Engine
Figure 58: Transmit Engine w/ TramelBlaze Verification
Figure 50‟s waveform demonstrates a simulation of the Transmit Engine with key signals
passing through it. The most important signal to note is the Tx_Line which shows the data
entering the Transmit Engine being shifted out serially to a receiver.
Figure 59: Transmit Engine with TramelBlaze Serial Terminal Output
When loaded up onto the Nexys 4 board and connected to RealTerm, the results were as
seen in Figure 51. This shows a consistent transmission to the Serial Terminal as long as the
Engine and Serial Terminal agree upon the Parity options and number of bits being sent.

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7.2. Revision 3.0: Receive Engine
Figure 60: Receive Engine w/ Transmit Engine Feed Verification
Once the Transmit Engine was verified, the Receive Engine could be tested. Figure 52,
taken from the Receive Engine verification demonstrates the working behavior of the Receive
Engine. As seen in the Figure 53, by taking the Transmit Line and feeding it into the Receive
Line, the system simulated how data would flow into the Receive Engine, as if they were user
inputs. This was done with the Transmit Engine ROM; it was consistently sending out the string
“CSULB CECS 460<CR><LF>” into the Receive Engine, so that it could show how data flows
through the it. The values of Data_TB matches with the value of Reg_out and this provides
enough evidence to say that the Receive Engine is working properly.
Figure 61: Test connection between Transmit Engine and Receive Engine

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Figure 62: Full UART and TramelBlaze Serial Terminal Output
After ensure that both the Transmit Engine and Receive Engine were working properly as
individuals, a new ROM was developed in order to utilized both engines. Once the ROM was
properly developed, the design was connected to the Serial Terminal to test its capabilities. In
this test, every option was tested to ensure absolute completeness of the design. The figure above
shows four statements that was typed in by the preparer. Each statement consisted of different
switch options to fully test the UART‟s functionalities. Through these tests, the UART was able
to accurately print each statement and its Parity Options without fault. This was also done at the
fastest Baud Rate to ensure the design was exercised at its fullest potential.

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7.3. Revision 4.0: Memory Interface Block
Figure 63: MIB with Cell Ram Verification
Verifying that the MIB worked required different methods than the ones used to verify
the UART. First, the MIB had to be connected to a Cell RAM module provided by Micron in
order to simulate it. This was critical in properly designing the MIB so that it meets the timing
required to partake in certain read‟s and write‟s. After this was complete and data was seen to be
stored in the Cell RAM as seen in Figure 64, it was apparent that the system was able to access
the Micron Memory. After ensuring that the MIB was working correctly, another ROM had to be
created to utilize all the tools that the MIB provided. Once this was complete, clearing any
lingering bugs was done with ease.
Figure 64: Memory Address and Data

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8. Chip Level Test
Figure 65: Chip Level Test with MIB, Full UART, and TramelBlaze
After ensure MIB‟s test benches were working properly, it was appropriate to begin
testing it using the Full UART and serial terminal. Like the previous revisions, a new ROM had
to be developed in order to accommodate for the additional functionalities of the MIB. To save
time, only one parity option was used throughout the entire development process, 8 bits/No
Parity. The other parity options were already confirmed to be working in the previous revision,
when testing the Receive Engine. This test was solely focused on the usability of the MIB. At the
top the banner “I WILL ECHO<CR><LF>” appears whenever reset is pressed. After that, the
user is able to input character into the serial terminal, exactly like in the previous revision, except
the system has the added functionalities of being able to backspace properly, and stores each
character into a location in the on-board memory. Whenever a “*” is pressed, memory then
dumps out the stored data, and simply prints whatever the user had inputted. This is clearly
shown in the next two statements in the figure above.

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Final Specification
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9. Appendix
The Appendix includes the Verilog code to every module developed or mentioned in this
report with the exception of the TramelBlaze.
A1. Top Module Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Class: CECS 460 - System on Chip Design //
// Project name: Final SOC Specification //
// File name: Lab4_TopModule.v //
// //
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This is the project's top module. It instantiates the //
// Core and the TSI into one module. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Instantiation of Core and TSI //
// Revision 0.5 - Test Benched //
// - Nexys 4 Test //
// Revision 1.0 - Ready for Demonstration //
//***********************************************************************//
module Lab4_TopModule(clk_in, reset, switches,
Rx, Tx,
m_address, status, CE_n, WE_n, OE_n, ADV_n, CRE, UB_n, LB_n,
mem_clk, MIB_IO
);
//FPGA Connection
input clk_in, reset;
input [6:0] switches;
wire c_clk, c_reset;
wire [6:0] c_switches;
//UART Connection
input Rx;
wire c_Tx, c_Rx;
output Tx;
//MIB Connection
wire [22:0] c_mem_addr;
wire [7:0] c_status;
wire c_CE, c_WE, c_OE, c_ADV, c_CRE, c_UB, c_LB;
wire c_mem_clk;
output [22:0] m_address;
output [7:0] status;
output CE_n, WE_n, OE_n, ADV_n, CRE, UB_n, LB_n;
output mem_clk;
output [15:0] MIB_IO;

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wire [15:0] MIB_I, MIB_O;
wire T;
//INPUTS: clk_in, reset, Rx_In, [15:0] mem_data_in, [3:0] Baud_Sel,
// [2:0] Parity_ops;
//OUTPUTS: [22:0] mem_addr, [15:0] mem_data_out, IOBUF_T_LoE;
// CE_LoE, WE_LoE, OE_LoE, ADV_LoE, CRE_HiE, UB_LoE, LB_LoE;
// Tx_Out, [7:0] Status, mem_clk
Core Core(
.clk_in(c_clk),
.reset(c_reset),
.Rx_In(c_Rx), //From TSI -- Micro USB
.mem_data_in(MIB_O), //From TSI -- IOBUF
.Baud_Sel(c_switches[3:0]), //From TSI -- Switches
.Parity_ops(c_switches[6:4]), //From TSI -- Switches
.mem_addr(c_mem_addr), //To TSI -- Micron Memory
.mem_data_out(MIB_I), //To TSI -- IOBUF
.IOBUF_T_LoE(T), //To TSI -- IOBUF
.CE_LoE(c_CE), //To TSI -- Micron Memory
.WE_LoE(c_WE), //To TSI -- Micron Memory
.OE_LoE(c_OE), //To TSI -- Micron Memory
.ADV_LoE(c_ADV), //To TSI -- always "0"
.CRE_HiE(c_CRE), //To TSI -- always "0"
.UB_LoE(c_UB), //To TSI -- always "0"
.LB_LoE(c_LB), //To TSI -- always "0"
.Tx_Out(c_Tx), //To TSI -- Micro USB
.Status(c_status), //To TSI -- LEDs
.mem_clk(c_mem_clk) //To TSI -- Micron Memory
);
//FPGA Inputs
//INPUTS: clkI, resetI, [6:0] switchesI, Tx, Rx_I,
// [22:0] MEM_A, [7:0] status, CE, WE, OE, ADV, CRE, UB, LB
// MIB_T, [15:0] MIB_I
//OUTPUTS: clk, reset, [6:0] switches, Tx_O, Rx
// [22:0] MEM_A_O, [7:0] statusO, CE_O, WE_O, OE_O, ADV_O,
// CRE_O, UB_O, LB_O
// [15:0] MIB_O
//INOUTS: [15:0] MIB_IO
TSI TSI (
.clkI(clk_in), //Global In -- System Clock
.resetI(reset), //Global In -- Reset
.switchesI(switches), //Global In -- Switches
.clk(c_clk), //To Core -- System Clock
.reset(c_reset), //To Core -- Reset
.switches(c_switches), //To Core -- Switches
.Tx(c_Tx), //From Core -- Transmit Engine
.Rx_I(Rx), //Global In -- Receive Engine
.Tx_O(Tx), //Global Out -- Transmit Engine
.Rx(c_Rx), //To Core -- Receive Engine
.MEM_A(c_mem_addr), //From Core -- MIB
.status(c_status), //From Core -- Statuses
.mem_clk(c_mem_clk), //From Core -- Top
.CE(c_CE), //From Core -- MIB
.WE(c_WE), //From Core -- MIB
.OE(c_OE), //From Core -- MIB

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.ADV(c_ADV), //From Core -- MIB
.CRE(c_CRE), //From Core -- MIB
.UB(c_UB), //From Core -- MIB
.LB(c_LB), //From Core -- MIB
.MEM_A_O(m_address), //Global Out -- Micron Memory
.mem_clk_O(mem_clk), //Global Out -- Micron Memory
.statusO(status), //Global Out -- Micron Memory
.CE_O(CE_n), //Global Out -- Micron Memory
.WE_O(WE_n), //Global Out -- Micron Memory
.OE_O(OE_n), //Global Out -- Micron Memory
.ADV_O(ADV_n), //Global Out -- Micron Memory
.CRE_O(CRE), //Global Out -- Micron Memory
.UB_O(UB_n), //Global Out -- Micron Memory
.LB_O(LB_n), //Global Out -- Micron Memory
.MIB_T(T), //From Core -- MIB
.MIB_I(MIB_I), //From Core -- IOBUF Data
.MIB_O(MIB_O), //From Core -- IOBUF Data
.MIB_IO(MIB_IO) //From Core -- IOBUF Data
);
endmodule

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A2. Core Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Class: CECS 460 - System on Chip Design //
// Project name: Final SOC Specification //
// File name: Core.v //
// //
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The Core contains the instantiation of design's //
// processor, its interfaces, and its accessory modules. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 1.0 - Imported from CECS 460 Project 3: Full UART //
// Revision 1.1 - Name change to Core //
// Revision 1.2 - Instantiation of MIB //
// - Modification of conditional assignment //
// - MIB variables declared //
// Revision 1.3 - Creation of mem_clk conditional assignment //
// Revision 1.4 - Test Benched //
// Revision 2.0 - Ready for Demonstration //
//***********************************************************************//
module Core(clk_in, reset, Rx_In, mem_data_in, Baud_Sel, Parity_ops,
mem_addr, mem_data_out, IOBUF_T_LoE, CE_LoE, WE_LoE, OE_LoE,
ADV_LoE, CRE_HiE, UB_LoE, LB_LoE, Tx_Out, Status, mem_clk,
);
input clk_in, reset, Rx_In;
input [15:0] mem_data_in;
input [3:0] Baud_Sel;
input [2:0] Parity_ops;
output [22:0] mem_addr;
output [15:0] mem_data_out;
output IOBUF_T_LoE;
output wire CE_LoE, WE_LoE, OE_LoE, ADV_LoE, CRE_HiE, UB_LoE, LB_LoE;
output wire Tx_Out;
output wire [7:0] Status;
output wire mem_clk;
wire [15:0] TB_In, TB_inport;
wire [15:0] Port_ID;
wire [15:0] TB_outport;
wire [7:0] Rx_Data;
wire reset_sync;
wire write_strobe, read_strobe, UART_Int;
wire Pulse, Interrupt, Interrupt_Ack;
wire ld_in, In_Sel;
assign mem_clk = 1'b0;

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assign ld_in = write_strobe && (Port_ID == 16'b0000); //To Tx_Engine
assign TB_In = (Port_ID == 16'h0001) ? {8'b0, Status}:
(Port_ID == 16'h0000) ? {8'b0, Rx_Data}:
(Port_ID == 16'h0014) ? TB_inport:
16'b0;
//INPUTS: clk_in, reset, Read, Write, [15:0] Port_ID, [15:0] mem_data_in,
// [15:0] TB_outport
//OUTPUTS: CE_LoE, WE_LoE, OE_LoE, IOBUF_T_LoE, ADV_LoE, CRE_HiE, UB_LoE,
// LB_LoE, [22:0] mem_addr, [15:0] mem_data_out, [15:0] TB_inport;
MIB MIB (.clk(clk_in),
.reset(reset),
.Port_ID(Port_ID), //From TramelBlaze
.Read(read_strobe), //From TramelBlaze
.Write(write_strobe), //From TramelBlaze
.TB_outport(TB_outport), //From TramelBlaze
.mem_data_in(mem_data_in), //Global -- To TSI
.CE_LoE(CE_LoE), //Global -- To Memory
.WE_LoE(WE_LoE), //Global -- To Memory
.OE_LoE(OE_LoE), //Global -- To Memory
.IOBUF_T_LoE(IOBUF_T_LoE), //Global -- To TSI
.ADV_LoE(ADV_LoE), //Global -- To Memory
.CRE_HiE(CRE_HiE), //Global -- To Memory
.UB_LoE(UB_LoE), //Global -- To Memory
.LB_LoE(LB_LoE), //Global -- To Memory
.mem_addr(mem_addr), //Global -- To Memory
.mem_data_out(mem_data_out), //Global -- To TSI
.TB_inport(TB_inport) //From TramelBlaze
);
//INPUTS: clk_in, reset, *Port_ID, *****Data_In, **Rate_Sel,
// ***Parity_ops, write_strobe, read_strobe, Rx_In,
//OUTPUTS: ****Rx_Data_TB, *****Status, UART_Interrupt, Tx_Out
//*[15:0], **[3:0], ***[2:0], ****[9:0], *****[7:0];
UART_Top UART(.clk_in(clk_in),
.reset(reset_sync),
.Port_ID(Port_ID), //From TramelBlaze
.Data_In(TB_outport), //From TramelBlaze
.Rate_Sel(Baud_Sel), //Global Input – Switches
.Parity_ops(Parity_ops), //Global Input – Switches
.write_strobe(write_strobe), //From TramelBlaze
.read_strobe(read_strobe), //From TramelBlaze
.Rx_In(Rx_In), //From USB***
.Interrupt_Ack(Interrupt_Ack), //From TramelBlaze
.ld_in(ld_in), //From Assign Statement
.Rx_Data_TB(Rx_Data), //To TramelBlaze
.Status(Status), //Global Output
.UART_Interrupt(UART_Int), //To Pulse Maker
.Tx_Out(Tx_Out) //To USB
);
//INPUTS: CLK, RESET, *IN_PORT, INTERRUPT,
//OUTPUTS: *OUT_PORT, *PORT_ID, READ_STROBE, WRITE_STROBE, INTERRUPT_ACK
//*[15:0]
tramelblaze_top TramelBlaze (.CLK(clk_in),
.RESET(reset_sync),
.IN_PORT(TB_In), //From UART,
.INTERRUPT(Interrupt), //From RS Flop
.OUT_PORT(TB_outport), //To UART
.PORT_ID(Port_ID), //To UART, MIB

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.READ_STROBE(read_strobe), //To UART, MIB
.WRITE_STROBE(write_strobe), //To UART, MIB
.INTERRUPT_ACK(Interrupt_Ack) //To RS Flop
);
//INPUTS: clk_in, reset
//OUTPUTS: sync
AISO AISO(.clk_in(clk_in),
.reset(reset),
.sync(reset_sync) //To All Module Resets
);
//INPUTS: clk_in, reset, D_in
//OUTPUTS: pulse
pulse_maker Pulse_Maker(.clk_in(clk_in),
.reset(reset_sync),
.D_in(UART_Int), //From UART
.pulse(Pulse) //To RS Flop
);
//INPUTS: clk_in, reset, R, S
//OUTPUTS: D_out
RS_Flop RS_Flop(.clk_in(clk_in),
.reset(reset_sync),
.R(Interrupt_Ack), //From TramelBlaze
.S(Pulse), //From Pulse Maker
.D_out(Interrupt) //To TramelBlaze
);
endmodule

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A3. MIB Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Class: CECS 460 - System on Chip Design //
// Project name: Final SOC Specification //
// File name: MIB.v //
// //
// Created by Tony Le & Phuong Nguyen //
// Copyright © 2016 Tony Le & Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The MIB sends signals to the Micron Memory as it //
// receives data and sends data to it based on the //
// signals. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Creation of State Machine //
// Revision 0.5 - Creation of Control Flops //
// Revision 0.6 - Changes to Clock Counter //
// Revision 0.7 - Test Benched with Cell Ram Module //
// Revision 0.8 - Changes to RD_R flop //
// Revision 1.0 - Ready for Demonstration //
//***********************************************************************//
module MIB(clk, reset, Port_ID, Read, Write, //LoE = Low Enable
TB_outport, mem_data_in, //HiE = High Enable
CE_LoE, WE_LoE, OE_LoE, IOBUF_T_LoE,
ADV_LoE, CRE_HiE, UB_LoE, LB_LoE,
mem_addr, mem_data_out, TB_inport
);
input clk, reset;
input Read, Write;
input [15:0] Port_ID;
input [15:0] mem_data_in;
input [15:0] TB_outport;
//control lines
output reg CE_LoE, WE_LoE, OE_LoE, IOBUF_T_LoE; //signal depends on state
output reg ADV_LoE, CRE_HiE, UB_LoE, LB_LoE; //signal will always be 1'b0
//output data signals
output reg [22:0] mem_addr;
output reg [15:0] mem_data_out;
output reg [15:0] TB_inport;
reg [3:0] state, next_state;
reg [3:0] WCLK, RCLK; //counter for read and write state
wire write_done, read_done; //done signal for write and read state
reg nCE_LoE, nWE_LoE, nOE_LoE, nIOBUF_T_LoE; //next state command signal
reg nADV_LoE, nCRE_HiE, nUB_LoE, nLB_LoE;

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//internal registers holding the addr and data
reg [6:0] WA_R0;
reg [15:0] WA_R1, WD_R;
reg [15:0] RD_R;
parameter //control word parameter
IDLE = 4'h0,
MEM_WRITE = 4'h1,
MEM_READ = 4'h2,
//operation word parameter
WADDR1 = 16'h11,
WADDR2 = 16'h12,
WDATA = 16'h13,
RDATA = 16'h14,
MEMREAD = 16'h15,
MEMWRITE = 16'h16;
//************************************************************************************
//Control Word Present state logic
always @(posedge clk, posedge reset) begin
if(reset)
begin
state <= IDLE; //reset to idle state
//because low polarity, resets to one
{CE_LoE, WE_LoE, OE_LoE, IOBUF_T_LoE} <= 4'b1_1_1_1;
//signal always 0
{ADV_LoE, CRE_HiE, UB_LoE, LB_LoE} <= 4'b0_0_0_0;
end
else
begin
state <= next_state;
{CE_LoE, WE_LoE, OE_LoE, IOBUF_T_LoE} <=
{nCE_LoE, nWE_LoE, nOE_LoE, nIOBUF_T_LoE};
end
end
//Control Word Next State Logic
always @ (*) begin
case(state)
IDLE: //idle state not accessing memory
begin
{nCE_LoE, nWE_LoE, nOE_LoE, nIOBUF_T_LoE} = 4'b1_1_1_1;
if((Port_ID == 16'h16) && Write) //condition to write
next_state = MEM_WRITE;
else if(Port_ID == 16'h15 && Read) //condition to read
next_state = MEM_READ;
else
next_state = IDLE;
end
MEM_WRITE: //MEM_WRITE access memory to write into it
begin
{nCE_LoE, nWE_LoE, nOE_LoE, nIOBUF_T_LoE} = 4'b0_0_1_0;
if(WCLK == 4'b1100) next_state = IDLE;
else next_state = MEM_WRITE;

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end
MEM_READ: //MEM_READ access memory to read form it
begin
{nCE_LoE, nWE_LoE, nOE_LoE, nIOBUF_T_LoE} = 4'b0_1_0_1;
if(RCLK == 4'b1100) next_state = IDLE;
else next_state = MEM_READ;
end
default: //default is idle state
begin
{nCE_LoE, nWE_LoE, nOE_LoE, nIOBUF_T_LoE} = 4'b1_1_1_1;
if(Port_ID == 16'h14 && Write)
next_state = MEM_WRITE;
else if(Port_ID == 16'h15 && Read)
next_state = MEM_READ;
else
next_state = state;
end
endcase
end
always @ (posedge clk, posedge reset) begin
if(reset) begin
WCLK <= 4'b0;
RCLK <= 4'b0;
end
else if (state == IDLE) begin
WCLK <= 4'b0;
RCLK <= 4'b0;
end
else if (state == MEM_WRITE) WCLK <= WCLK + 4'b1;
else if (state == MEM_READ) RCLK <= RCLK + 4'b1;
else begin
WCLK <= WCLK;
RCLK <= RCLK;
end
end
//****************************************************************************
//End of state machine
//==============================================
//Legend for input/output and register reference
//==============================================
// WA_R0, WA_R1, WD_R, RD_R == register holding the address and data
//
// mem_addr = output connected to memory address
// mem_data_out = output data going to memory
// mem_data_in = input data coming from memory
//
// TB_outport = input data coming from TB
// TB_inport = output data going to TB
//****************************************************************************

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//start of operation logic
always @ (posedge clk, posedge reset)
if(reset) begin
WA_R0 <= 7'h0;
WA_R1 <= 16'h0;
WD_R <= 16'h0;
mem_addr <= 16'h0;
mem_data_out <= 16'h0;
TB_inport <= 16'h0;
end
else
case(Port_ID)
WADDR1: if(Write) WA_R0 <= TB_outport[6:0];
else WA_R0 <= WA_R0;
WADDR2: if(Write) WA_R1 <= TB_outport;
else WA_R1 <= WA_R1;
WDATA: if(Write) WD_R <= TB_outport;
else WD_R <= WD_R;
RDATA: TB_inport <= RD_R;
MEMREAD: if(Read)
mem_addr <= {WA_R0, WA_R1};
else
mem_addr <= mem_addr;
MEMWRITE: if(Write) begin
mem_addr <= {WA_R0, WA_R1};
mem_data_out <= WD_R;
end
else begin
mem_addr <= mem_addr;
mem_data_out <= mem_data_out;
end
default: begin
WA_R0 <= WA_R0;
WA_R1 <= WA_R1;
WD_R <= WD_R;
mem_addr <= mem_addr;
mem_data_out <= mem_data_out;
TB_inport <= TB_inport;
end
endcase
always @ (posedge clk, posedge reset)
if(reset) RD_R <= 16'h0000;
else if(RCLK == 4'b1011) RD_R <= mem_data_in;
else RD_R <= RD_R;
endmodule

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A4. UART Top Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Class: CECS 460 - System on Chip Design //
// Project name: Final SOC Specification //
// File name: UART.v //
// //
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen . All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The Universal Asynchronous Receiver and Transmitter //
// instantiates the Transmit Engine, Receive Engine and //
// Baud Rate Decoder together. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Assign statement for Tx Load, UART Interrupt //
// Revision 0.4 - Concatenate Statuses and Tx_Rdy and Rx_Rdy //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module UART_Top(clk_in, reset, Port_ID, Data_In, Rate_Sel, Parity_ops,
write_strobe, read_strobe, Rx_In, Interrupt_Ack, ld_in,
Rx_Data_TB, Status, UART_Interrupt, Tx_Out);
input clk_in, reset;
input [15:0] Port_ID;
input [7:0] Data_In;
input [3:0] Rate_Sel;
input [2:0] Parity_ops;
input write_strobe, read_strobe;
input Rx_In, Interrupt_Ack;
input ld_in;
output [7:0] Rx_Data_TB, Status;
output UART_Interrupt, Tx_Out;
wire [18:0] B_Rate;
wire Rx_Rdy, Tx_Rdy, Rx_RS, Tx_RS;
wire PERR, FERR, OVF;
assign UART_Interrupt = Rx_Rdy || Tx_Rdy; //Global Output
assign Status = {3'b0, OVF, FERR, PERR, Tx_Rdy, Rx_Rdy}; //Global Output
//INPUTS: clk_in, reset, ld_in, [18:0] Baud_Rate, [7:0] Data_in,
// [2:0] Parity_ops;
//OUTPUTS: Tx_Rdy, Tx_Out;
Tx_Engine_Top Tx_Engine (.clk_in(clk_in),
.reset(reset),
.ld_in(ld_in), //Global Input
.Baud_Rate(B_Rate), //From Baud Decoder
.Data_in(Data_In), //Global Input -- TramelBlaze
.Parity_ops(Parity_ops), //Global Input -- Switches
.Tx_Rdy(Tx_RS), //To Transmit RS Flop
.Tx_Out(Tx_Out) //Global Output

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);
//INPUT: clk_in, reset, R, S;
//OUTPUT: D_out;
RS_Flop Transmit_RS (.clk_in(clk_in),
.reset(reset),
.R(Interrupt_Ack),
.S(Tx_RS),
.D_out(Tx_Rdy)
);
//INPUTS: clk_in, reset, Rx_In, Eight, Parity_En, oHeL, read_strobe,
// [18:0] Rate, [15:0] Port_ID,
//OUTPUTS: Rx_Rdy, Parity_Err, Frame_Err, Overflow, [7:0] Rx_Data_TB
Rx_Engine_Top Rx_Engine (.clk_in(clk_in),
.reset(reset),
.Rx_In(Rx_In), //Global Input -- USB
.Eight(Parity_ops[2]), //Global Input -- Switches
.Parity_En(Parity_ops[1]), //Global Input -- Switches
.oHeL(Parity_ops[0]), //Global Input -- Switches
.read_strobe(read_strobe), //Global Input -- TB
.Rate(B_Rate), //From Baud Decoder
.Port_ID(Port_ID), //Global Input -- TB
.Rx_Rdy(Rx_RS), //To Status & Receive RS
.Parity_Err(PERR), //To Status
.Frame_Err(FERR), //To Status
.Overflow(OVF), //To Status
.Rx_Data_TB(Rx_Data_TB) //Global Output
);
//INPUT: clk_in, reset, R, S;
//OUTPUT: D_out;
RS_Flop Receive_RS (.clk_in(clk_in),
.reset(reset),
.R(Interrupt_Ack),
.S(Rx_RS),
.D_out(Rx_Rdy)
);
//INPUTS: [3:0] Rate_Sel
//OUTPUTS: [18:0] Baud_Rate
Baud_Decoder Baud_Rate (.Rate_Sel(Rate_Sel), //Global Input -- Switches
.Baud_Rate(B_Rate) //To Tx and Rx Engine
);
endmodule

83. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 83
A5. Transmit Engine Top Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module instantiates the Tx Engine together. //
// It connects thes Bit Count, Bit Time Counter, //
// Controller and Shift Register together. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Instantiate all Modules //
// Revision 0.5 - Test Benched //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Tx_Engine_Top(clk_in, reset, ld_in, Baud_Rate, Data_in, Parity_ops,
Tx_Rdy, Tx_Out);
input clk_in, reset, ld_in;
input [18:0] Baud_Rate;
input [7:0] Data_in;
input [2:0] Parity_ops;
output Tx_Rdy, Tx_Out;
wire [7:0] Reg_out;
wire DoIt, done;
wire Load_D1;
wire BTU;
wire [1:0] bit_10_9;
//INPUTS: clk_in, reset, DOIT, BTU
//OUTPUTS: DONE
Bit_Count_Tx Tx_Count (.clk_in(clk_in),
.reset(reset),
.DOIT(DoIt),
.BTU(BTU),
.DONE(done)
);
//INPUTS: clk_in, reset, DOIT, Baud_Rate*
//OUTPUTS: BTU_out
//*[18:0]
Bit_Time_Counter_Tx Tx_Time_Counter (.clk_in(clk_in),
.reset(reset),
.DOIT(DoIt),
.Baud_Rate(Baud_Rate),
.BTU_out(BTU)
);
//INPUTS: clk_in, reset, done, load, Out_Port*
//OUTPUTS: Tx_rdy, Load_D1, DoIt, D_out*

84. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 84
//*[7:0]
Tx_Controller Controller (.clk_in(clk_in),
.reset(reset),
.done(done),
.load(ld_in),
.Out_Port(Data_in),
.Tx_rdy(Tx_Rdy),
.Load_D1(Load_D1),
.DoIt(DoIt),
.D_out(Reg_out)
);
//INPUTS: Reg8_in*, bits_parity_oHeL**
//OUTPUTS: bit_10_9***
//*[7:0] **[2:0] ***[1:0]
Bit_10_9_Decoder Bit_Decoder (.Reg8_in(Reg_out),
.bits_parity_oHeL(Parity_ops),
.bit_10_9(bit_10_9)
);
//INPUTS: clk_in, reset, load, shift_en, S_Data_in, D_in*
//OUTPUTS: SD0
//*[10:0]
Shift_Register_Tx Tx_Shift_Reg (.clk_in(clk_in),
.reset(reset),
.load(Load_D1),
.shift_en(BTU),
.S_Data_in(1'b1),
.D_in({bit_10_9, Reg_out[6:0], 2'b01}),
.SD0(Tx_Out)
);
endmodule

85. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 85
A6. Transmit Bit Count Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module will count the number of times the shift //
// register shifts through. It ensures that the shift //
// register does not shift pass 11 times. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Assign statement & Sequential Logic //
// Revision 0.4 - Test Benched //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Bit_Count_Tx(clk_in, reset, DOIT, BTU, DONE);
input clk_in, reset;
input DOIT, BTU;
output DONE;
reg [3:0] count;
// Pulse when count is 11
assign DONE = (count == 12);
always @(posedge clk_in, posedge reset) begin
if(reset) count <= 4'b0;
else if(DONE) count <= 4'b0;
else
case({DOIT, BTU})
2'b00: count <= 4'b0;
2'b01: count <= 4'b0;
2'b10: count <= count;
2'b11: count <= count + 4'b1;
endcase
end
endmodule

86. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 86
A7. Transmit Bit Time Counter Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The Bit Time Counter determines the speed at which //
// the Transmit Engine will run at. It will continuously //
// count to a given Baud Rate Count and assert its //
// output //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Assign and Always statement //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Bit_Time_Counter_Tx(clk_in, reset, DOIT, Baud_Rate, BTU_out);
input clk_in, reset;
input DOIT;
input [18:0] Baud_Rate;
output wire BTU_out;
reg [18:0] count;
// Pulse when count is 11
assign BTU_out = (count == Baud_Rate);
always @(posedge clk_in, posedge reset) begin
if(reset) count <= 19'b0;
else if(BTU_out) count <= 19'b0; else
case({DOIT, BTU_out})
2'b00: count <= 19'b0;
2'b01: count <= 19'b0;
2'b10: count <= count + 19'b1;
2'b11: count <= 19'b0;
default: count <= count;
endcase
end
endmodule

87. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 87
A8. Transmit Controller Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: Tx_Controller consists of all the necessary flop in //
// order to dictate the Tx Engine's workings. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Sequential Logic for all flops //
// Revision 0.4 - Correction to Tx_Rdy flop //
// Revision 0.5 - Test Benched //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Tx_Controller(clk_in, reset, done, load, Out_Port, Tx_rdy, Load_D1,
DoIt, D_out);
input clk_in, reset, done, load;
input [7:0] Out_Port;
output reg Tx_rdy, Load_D1, DoIt;
output reg [7:0] D_out;
// Tx_rdy RS flop (reverse logic)
always @ (posedge clk_in, posedge reset) begin
if(reset) Tx_rdy <= 1'b1;
else if (load) Tx_rdy <= 1'b0;
else if (done) Tx_rdy <= 1'b1;
else Tx_rdy <= Tx_rdy;
end
// D Flip Flop output to DoIt and Shift Reg
always @ (posedge clk_in, posedge reset) begin
if(reset) Load_D1 <= 1'b0;
else Load_D1 <= load;
end
// DoIt RS flop
always @ (posedge clk_in, posedge reset) begin
if(reset) DoIt <= 1'b0;
else if(done) DoIt <= 1'b0;
else if(Load_D1) DoIt <= 1'b1;
else DoIt <= DoIt;
end
// Out_Port Load Register
always @ (posedge clk_in, posedge reset) begin
if(reset) D_out <= 8'b0;
else if(load) D_out <= Out_Port;
else D_out <= D_out;
end
endmodule

88. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 88
A9. Transmit Bit 10 & 9 Decoder Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This Decoder will determine the values that go into //
// bits 10 and 9, it can be an 8th bit, or a parity //
// depending on the user's input. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Decode Logic //
// Revision 0.4 - Test Benched //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Bit_10_9_Decoder(Reg8_in, bits_parity_oHeL, bit_10_9);
input [7:0] Reg8_in;
input [2:0] bits_parity_oHeL;
output reg [1:0] bit_10_9;
always @ (*) begin
case (bits_parity_oHeL)
3'b000: bit_10_9 <= 2'b11;
3'b001: bit_10_9 <= 2'b11;
3'b010: bit_10_9 <= {1'b1, ^Reg8_in[6:0]};
3'b011: bit_10_9 <= {1'b1, ~^Reg8_in[6:0]};
3'b100: bit_10_9 <= {1'b1, Reg8_in[7]};
3'b101: bit_10_9 <= {1'b1, Reg8_in[7]};
3'b110: bit_10_9 <= {^Reg8_in[7:0], Reg8_in[7]};
3'b111: bit_10_9 <= {~^Reg8_in[7:0], Reg8_in[7]};
default: bit_10_9 <= 2'b11;
endcase
end
endmodule

89. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 89
A10. Transmit Shift Register Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The shift register will take in data from the bit //
// decoder and the controller register and appropriately //
// shift bit outs one by one. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Sequential Logic Design for Shift Register //
// Revision 0.4 - Test Benched //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Shift_Register_Tx(clk_in, reset, load, shift_en, S_Data_in, D_in, SD0);
input clk_in, reset, load, shift_en, S_Data_in;
input [10:0] D_in;
output reg SD0;
reg [10:0] register;
always @ (posedge clk_in, posedge reset) begin
if(reset) begin
register <= 11'h7FF;
SD0 <= 1'b1;
end
else if (load) register <= D_in;
else if (shift_en) begin
register <= {S_Data_in, register[10:1]};
SD0 <= register[0];
end
else begin
register <= register;
SD0 <= SD0;
end
end
endmodule

90. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 90
A11: Receive Engine Top Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module instantiates the Rx Engine together. //
// It connects the Shift Register, State Machine, //
// Controller, Bit Count, Bit Time Counter. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Instantiate Shift Register, State Machine, Controller,//
// - Bit Count and Bit Timer Counter //
// Revision 0.5 - Tx Line fed into Rx Line //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Rx_Engine_Top(clk_in, reset, Rx_In, Eight, Parity_En, oHeL, read_strobe,
Rate, Port_ID, Rx_Rdy, Parity_Err, Frame_Err, Overflow,
Rx_Data_TB);
input clk_in, reset, Rx_In, Eight, Parity_En, oHeL, read_strobe;
input [18:0] Rate;
input [15:0] Port_ID;
output Rx_Rdy, Parity_Err, Frame_Err, Overflow;
output [7:0] Rx_Data_TB;
wire [9:0] Data_Ctrl;
wire BTU, Start;
wire DONE, DOIT;
wire Clear;
assign Clear = read_strobe && (Port_ID == 16'b0000);
//INPUTS: clk_in, reset, BTU, Start, Rx_In, DONE, Eight, Parity_En,
//OUTPUTS: *Data_Ctrl, **Data_TB
//*[9:0], ** [7:0]
Shift_Register_Rx Rx_Shift_Reg (.clk_in(clk_in),
.reset(reset),
.BTU(BTU), //From Bit Time Counter
.Start(Start), //From FSM
.Rx_In(Rx_In), //Global Input
.Eight(Eight), //Global Input
.Parity_En(Parity_En), //Global Input
.Data_Ctrl(Data_Ctrl), //To Controller
.Data_TB(Rx_Data_TB) //Global Out
);
//INPUTS: clk_in, reset, Rx_Line, BTU, DONE;
//OUTPUTS: Start, DOIT
Rx_FSM State_Machine (.clk_in(clk_in),
.reset(reset),
.Rx_Line(Rx_In), //Global Output

91. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 91
.BTU(BTU), //From Bit Time Counter
.DONE(DONE), //From Bit Count
.Start(Start), //To Shift Register and Time Counter
.DOIT(DOIT) //To Bit Count and Bit Time Counter
);
//INPUTS: clk_in, reset, DONE, Clear, Eight, Parity_En, Even, *D_In;
//OUTPUTS: Rx_Rdy, Parity_Err, Frame_Err, Overflow;
//*[9:0]
Rx_Controller Controller(.clk_in(clk_in),
.reset(reset),
.DONE(DONE), //From Bit Count
.Clear(Clear), //Global Input
.Eight(Eight), //Global Input
.Parity_En(Parity_En), //Global Input
.Even(!oHeL), //Global Input
.D_In(Data_Ctrl), //From Shift Register
.Rx_Rdy(Rx_Rdy), //Global Output
.Parity_Err(Parity_Err), //Global Output
.Frame_Err(Frame_Err), //Global Output
.Overflow(Overflow) //Global Output
);
//INPUTS: clk_in, reset, DOIT, BTU, Eight, Parity_En
//OUTPUTS: DONE
bit_count_rx Rx_Count(.clk_in(clk_in),
.reset(reset),
.DOIT(DOIT), //From FSM
.BTU(BTU), //From Bit Time Counter
.Eight(Eight), //Global Input
.Parity_En(Parity_En), //Global Input
.DONE(DONE) //To FSM, Controller,
);
//INPUTS: clk_in, reset, DOIT, Start, Baud_Rate*
//OUTPUTS: BTU
//*[18:0]
bit_time_counter_rx Rx_Time_Counter(.clk_in(clk_in),
.reset(reset),
.DOIT(DOIT), //From FSM
.Start(Start), //From FSM
.Baud_Rate(Rate), //Global Input
.BTU(BTU) //To FSM,SR, Bit Counter
);
endmodule

92. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 92
A12: Receive Shift Register Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module acts as the data receive of the Receive //
// Engine, any data gets shifted into this module before //
// it goes to any other modules //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Create Shift Register Block //
// Revision 0.5 - Create assign statement //
// Revision 0.6 - Changed Combinational Block Behavior //
// Revision 0.7 - Test Benched, Verified //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Shift_Register_Rx(clk_in, reset, BTU, Start, Rx_In, Eight, Parity_En,
Data_Ctrl, Data_TB);
input clk_in, reset, BTU, Start, Rx_In;
input Eight, Parity_En;
output reg [9:0] Data_Ctrl;
output reg [7:0] Data_TB;
reg [9:0] Data_Out;
wire Shift_En;
assign Shift_En = BTU && !Start;
/***Raw Data shifted in***/
always @ (posedge clk_in, posedge reset) begin
if(reset) Data_Out <= 10'b0;
else if (Shift_En) Data_Out <= {Rx_In, Data_Out[9:1]};
else Data_Out <= Data_Out;
end
always @ (*) begin
case ({Eight, Parity_En})
2'b00:{Data_Ctrl, Data_TB} <= {2'b0, Data_Out[9:2], 1'b0, Data_Out[8:2]};
2'b01:{Data_Ctrl, Data_TB} <= {1'b0, Data_Out[9:1], 1'b0, Data_Out[7:1]};
2'b10:{Data_Ctrl, Data_TB} <= {1'b0, Data_Out[9:1], Data_Out[8:1]};
2'b11:{Data_Ctrl, Data_TB} <= {1'b0, Data_Out[8:0], Data_Out[7:0]};
default:{Data_Ctrl, Data_TB} <= Data_Out;
endcase
end
endmodule

93. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 93
A13. Receive State Machine Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module detects the Start bit of the data //
// received and allows the counters to work when it is //
// detected. The state machine will allow the counter to //
// keep counting up until the counter send a signal to //
// signify its completion of data reception. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Create Next State Logic Block //
// Revision 0.5 - Create Present State Combinational Block //
// Revision 0.6 - Changed FSM State Machine to Modified Moore //
// Revision 0.7 - Test Benched, Verified //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Rx_FSM(clk_in, reset, Rx_Line, BTU, DONE, Start, DOIT);
input clk_in, reset;
input Rx_Line, BTU, DONE;
output reg Start, DOIT;
reg [1:0] state, next_state;
reg next_Start, next_DOIT;
parameter IDLE = 0, START = 1, DO_IT = 2;
/***Next State Logic***/
always @ (posedge clk_in, posedge reset) begin
if(reset) begin
state <= IDLE;
Start <= 1'b0;
DOIT <= 1'b0;
end
else begin
state <= next_state;
Start <= next_Start;
DOIT <= next_DOIT;
end
end
/***Present State Logic***/
always @ (*) begin
case (state)
IDLE: begin
if(Rx_Line)
{next_state, next_Start, next_DOIT} = {IDLE, 2'b00};
else
{next_state, next_Start, next_DOIT} = {START, 2'b11};
end
START: begin

94. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 94
if(!Rx_Line && !BTU)
{next_state, next_Start, next_DOIT} = {START, 2'b11};
else if((Rx_Line && BTU) || (Rx_Line && !BTU))
{next_state, next_Start, next_DOIT} = {IDLE, 2'b00};
else
{next_state, next_Start, next_DOIT} = {DO_IT, 2'b01};
end
DO_IT: begin
if(!DONE)
{next_state, next_Start, next_DOIT} = {DO_IT, 2'b01};
else
{next_state, next_Start, next_DOIT} = {IDLE, 2'b00};
end
default: begin
{next_state, next_Start, next_DOIT} = {IDLE, 2'b00};
end
endcase
end
endmodule

95. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 95
A14. Receive Controller Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The controller determines the parity of the data //
// received by the receive engine. At the same time, //
// this module sends a signal to denote that it is ready //
// to receive data. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Create Sequential Logic Blocks for parities //
// Revision 0.5 - Create Combinational Block for parity logic //
// Revision 0.6 - Test Benched, Verified //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Rx_Controller(clk_in, reset, DONE, Clear, Eight, Parity_En, Even, D_In,
Rx_Rdy, Parity_Err, Frame_Err, Overflow);
input clk_in, reset, DONE, Clear, Eight, Parity_En, Even;
input [9:0] D_In;
output reg Rx_Rdy, Parity_Err, Frame_Err, Overflow;
//Parity Error Wiring
wire P_REC, Bit8, P_XOR, P_GEN, GEN_REC, Parity_In;
// Framing Error Wiring
reg F_Check;
wire F_Compare, Frame_In;
// Overflow Wiring
wire Over_In;
// Parity Error Set Logic
assign P_REC = Eight ? D_In[8] : D_In[7];
assign Bit8 = Eight ? D_In[7] : 1'b0;
assign P_XOR = ^{Bit8, D_In[6:0]};
assign P_GEN = Even ? P_XOR : !P_XOR;
assign GEN_REC = ^{P_GEN, P_REC};
assign Parity_In = Parity_En && GEN_REC && DONE;
// Framing Error Set Logic
always @ (*) begin
case ({Eight, Parity_En})
2'b00: F_Check = D_In[7];
2'b01: F_Check = D_In[8];
2'b10: F_Check = D_In[8];
2'b11: F_Check = D_In[9];
default: F_Check = D_In[7];
endcase
end

96. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 96
assign F_Compare = !F_Check;
assign Frame_In = F_Compare && DONE;
// Overflow Set Logic
assign Over_In = DONE && Rx_Rdy;
// Rx Rdy Flop
always @ (posedge clk_in, posedge reset) begin
if (reset) Rx_Rdy <= 1'b0;
else if (Clear) Rx_Rdy <= 1'b0;
else if (DONE) Rx_Rdy <= 1'b1;
else Rx_Rdy <= Rx_Rdy;
end
// Parity Error Flop
always @ (posedge clk_in, posedge reset) begin
if (reset) Parity_Err <= 1'b0;
else if (Clear) Parity_Err <= 1'b0;
else if (Parity_In) Parity_Err <= 1'b1;
else Parity_Err <= Parity_Err;
end
// Framing Error Flop
always @ (posedge clk_in, posedge reset) begin
if (reset) Frame_Err <= 1'b0;
else if (Clear) Frame_Err <= 1'b0;
else if (Frame_In) Frame_Err <= 1'b1;
else Frame_Err <= Frame_Err;
end
// Overflow Flop
always @ (posedge clk_in, posedge reset) begin
if (reset) Overflow <= 1'b0;
else if (Clear) Overflow <= 1'b0;
else if (Over_In) Overflow <= 1'b1;
else Overflow <= Overflow;
end
endmodule

97. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 97
A15: Receive Bit Count Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module counts the bits received by the receive //
// engine, it is all determined by the values set in //
// the eight and parity enable options on the on-board //
// switches. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Create Sequential Logic for Counter //
// Revision 0.5 - Create MUX based on Eight and Parity Enable //
// Revision 0.6 - Modification of MUX values //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module bit_count_rx(clk_in, reset, DOIT, BTU, Eight, Parity_En, DONE);
input clk_in, reset, DOIT, BTU;
input Eight, Parity_En;
output DONE;
reg [3:0] count, bits;
assign DONE = (count == bits);
always @ (posedge clk_in, posedge reset) begin
if (reset) count <= 4'b0;
else if (DONE) count <= 4'b0;
else begin
case ({DOIT, BTU})
2'b00: count <= 4'b0;
2'b01: count <= 4'b0;
2'b10: count <= count;
2'b11: count <= count + 4'b1;
default: count <= count;
endcase
end
end
always @ (*) begin
case ({Eight, Parity_En})
2'b00: bits = 9;
2'b01: bits = 10;
2'b10: bits = 10;
2'b11: bits = 11;
default: bits = 9;
endcase
end
endmodule

98. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 98
A16: Receive Bit Time Counter Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: Similar to the bit time counter of the transmit, this //
// time counter differs by the way it halves its baud //
// rate whenever a Start bit is detected by the state //
// machine, this allows the receive engine to pick up //
// data at the half way mark of each bit. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Wire Declaration //
// Revision 0.4 - Create Sequential Logic Block for Counter //
// Revision 0.5 - Create assign statement to change Baud Rate //
// Revision 1.0 - Ready for Demonstration //
//***********************************************************************//
module bit_time_counter_rx(clk_in, reset, DOIT, Start, Baud_Rate, BTU);
input clk_in, reset, DOIT, Start;
input [18:0] Baud_Rate;
output wire BTU;
reg [18:0] count;
wire [18:0] Rate;
assign BTU = (count == Rate);
assign Rate = Start ? (Baud_Rate >> 1): Baud_Rate;
always @ (posedge clk_in, posedge reset) begin
if (reset) count <= 19'b0;
else if (BTU) count <= 19'b0;
else begin
case ({DOIT, BTU})
2'b00: count <= 19'b0;
2'b01: count <= 19'b0;
2'b10: count <= count + 19'b1;
2'b11: count <= 19'b0;
default: count <= count;
endcase
end
end
endmodule

99. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 99
A17. Baud Rate Decoder Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The Baud Decoder will determine the speed at which //
// the transmit engine will run. The given values will //
// be sent to the Bit Time Counter which dictates the //
// speed. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Decode Logic for Baud Rate //
// Revision 0.4 - Test Benched //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 3.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module Baud_Decoder(Rate_Sel, Baud_Rate);
input [3:0] Rate_Sel;
output reg [18:0] Baud_Rate;
//Decode the Baud Rate
always @ (*) begin
case (Rate_Sel)
4'b0000: Baud_Rate = 333333; //300
4'b0001: Baud_Rate = 83333; //1200
4'b0010: Baud_Rate = 41667; //2400
4'b0011: Baud_Rate = 20833; //4800
4'b0100: Baud_Rate = 10417; //9600
4'b0101: Baud_Rate = 5208; //19200
4'b0110: Baud_Rate = 2604; //38400
4'b0111: Baud_Rate = 1736; //57600
4'b1000: Baud_Rate = 868; //115200
4'b1001: Baud_Rate = 434; //230400
4'b1010: Baud_Rate = 217; //460800
4'b1011: Baud_Rate = 109; //921600
default: Baud_Rate = 0;
endcase
end
endmodule

100. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 100
A18. AISO Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by John Tramel //
// Copyright © 2016 John Tramel. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: AISO known better as Asynchronous In, Synchronous Out //
// will synchronize the reset for all modules so that //
// everything runs at the same time. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Assign and Always statement //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 360 Project 1: Up Down Counter //
// Revision 3.0 - Imported from CECS 460 Project 1: The TramelBlaze //
// Revision 4.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 5.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module AISO(clk_in, reset, sync);
input clk_in, reset;
output sync;
reg [1:0] flop;
assign sync = ~flop[1];
always @ (posedge clk_in, posedge reset) begin
if (reset)
flop <= 2'b0;
else
flop <= {flop[0], 1'b1}; //flop[1] gets flop[0]
end //flop[0] gets 1'b1
endmodule

101. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 101
A19. Pulse Maker Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This module functions to create pulses based on when //
// a debounced mechanical switch is pressed. It consists //
// of two flops that will output a pulse whenever one of //
// the flops is on and the other is off //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// - Creation of two flops and always statement //
// Revision 0.3 - Correction on syntax of register //
// - Syntax Check //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 1: The TramelBlaze //
// Revision 3.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 4.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module pulse_maker(clk_in, reset, D_in, pulse);
input clk_in, reset, D_in;
output pulse;
reg [1:0] flop;
assign pulse = ~flop[1] && flop[0];
always @ (posedge clk_in, posedge reset) begin
if(reset) flop <= 2'b0;
else flop <= {flop[0], D_in};
end
endmodule

102. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 102
A20. RS Flop Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: This Verilog Code models the behavior of a RS Flop. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - Always statement //
// Revision 0.4 - If-Else statement to model RS Flop //
// Revision 0.5 - Syntax Check //
// Revision 1.0 - Ready for Demonstration //
// Revision 2.0 - Imported from CECS 460 Project 1: The TramelBlaze //
// Revision 3.0 - Imported from CECS 460 Project 2: Transmit Engine //
// Revision 4.0 - Imported from CECS 460 Project 3: Full UART //
//***********************************************************************//
module RS_Flop(clk_in, reset, R, S, D_out);
input clk_in, reset, R, S;
output reg D_out;
always @ (posedge clk_in, posedge reset) begin
if (reset) D_out <= 1'b0;
else if (R) D_out <= 1'b0;
else if (S) D_out <= 1'b1;
else D_out <= D_out;
end
endmodule

103. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 103
A21. TSI Source Code
`timescale 1ns / 1ps
//***********************************************************************//
// Created by Phuong Nguyen //
// Copyright © 2016 Phuong Nguyen. All rights reserved. //
// //
// Overview: //
// Target Devices: Artix7 (Digilent Nexys 4) //
// Tool versions: Xilinx ISE Project Navigator 14.7 //
// Description: The TSI handles all the inputs and outputs coming in //
// and out of the Core. //
// //
// Revision History: //
// Revision 0.1 - File Created //
// Revision 0.2 - Variable Declaration //
// Revision 0.3 - IOBUF, IBUF, OBUF, and IBUYF Created //
// Revision 0.4 - Test Benched with Project 3 Code //
// Revision 1.0 - Ready for Demonstration //
//***********************************************************************//
module TSI(clkI, resetI, switchesI,
clk, reset, switches,
Tx, Rx_I,
Tx_O, Rx,
MEM_A, status, mem_clk, CE, WE, OE, ADV, CRE, UB, LB,
MEM_A_O, statusO, mem_clk_O, CE_O, WE_O, OE_O, ADV_O, CRE_O, UB_O, LB_O,
MIB_T, MIB_I, MIB_O, MIB_IO);
//FPGA Inputs
input clkI; //System Clock
input resetI; //Global Reset
input [6:0] switchesI; //Baud Rate & Parity Ops
//Output to Core
output clk;
output reset;
output [6:0] switches;
//UART Interface
input Tx, Rx_I; //Core inputs
output Tx_O, Rx; //FPGA outputs
//Inputs from Core
input [22:0] MEM_A; //Memory Address
input [7:0] status; //Statuses
input mem_clk;
input CE; //Chip Enable
input WE; //Write Enable
input OE; //Output Enable
input ADV;
input CRE;
input UB;
input LB;
//Outputs to FPGA
output [22:0] MEM_A_O;
output [7:0] statusO;
output mem_clk_O;
output CE_O;
output WE_O;

104. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 104
output OE_O;
output ADV_O;
output CRE_O;
output UB_O;
output LB_O;
//dq
input MIB_T;
input [15:0] MIB_I;
output [15:0] MIB_O;
inout [15:0] MIB_IO;
//Dedicated Input Clock Buffer
IBUFG #(
.IOSTANDARD("DEFAULT")
)
Sys_Clk (
.O(clk), //To Core
.I(clkI) //From Top Level Port
);
//System Reset
IBUF #(
.IOSTANDARD("DEFAULT")
)
Sys_Reset(
.O(reset), //To Core
.I(resetI) //From Top Level Port
);
//UART Interface
OBUF #(
.IOSTANDARD("DEFAULT")
)
Transmit(
.O(Tx_O), //To Core
.I(Tx) //From Top Level Port
);
IBUF #(
.IOSTANDARD("DEFAULT")
)
Receive(
.O(Rx), //To Core
.I(Rx_I) //From Top Level Port
);
//Memory Address
OBUF #(
.IOSTANDARD("DEFAULT")
)
MEM_ADDR [22:0](
.O(MEM_A_O[22:0]), //Out to Micron
.I(MEM_A[22:0]) //From Core
);

105. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 105
//Status buffer
OBUF #(
.IOSTANDARD("DEFAULT")
)
Status_LEDs [7:0](
.O(statusO[7:0]), //To FPGA LEDs
.I(status[7:0]) //From Core
);
//Switches buffer
IBUF #(
.IOSTANDARD("DEFAULT")
)
Iswitches [6:0](
.O(switches [6:0]), //To FPGA Switches
.I(switchesI [6:0]) //From Top Level Port
);
OBUF #(
.IOSTANDARD("DEFAULT")
)
mem_clk_out(
.O(mem_clk_O), //Out to Micron
.I(1'b0) //From Core
);
//Memory Signal Interface
OBUF #(
.IOSTANDARD("DEFAULT")
)
CE_LoE(
.O(CE_O), //Out to Micron
.I(CE) //From Core
);
OBUF #(
.IOSTANDARD("DEFAULT")
)
WE_LoE(
.O(WE_O), //Out to Micron
.I(WE) //From Core
);
OBUF #(
.IOSTANDARD("DEFAULT")
)
OE_LoE(
.O(OE_O), //Out to Micron
.I(OE) //From Core
);
OBUF #(
.IOSTANDARD("DEFAULT")
)

106. Prepared by:
Phuong Nguyen
Date:
December 14, 2016
Document Name:
Final Specification
Revision:
4.0
Nguyen 106
ADV_LoE(
.O(ADV_O), //Out to Micron
.I(ADV) //From Core
);
OBUF #(
.IOSTANDARD("DEFAULT")
)
CRE_HiE(
.O(CRE_O), //Out to Micron
.I(CRE) //From Core
);
OBUF #(
.IOSTANDARD("DEFAULT")
)
UB_LoE(
.O(UB_O), //Out to Micron
.I(UB) //From Core
);
OBUF #(
.IOSTANDARD("DEFAULT")
)
LB_LoE(
.O(LB_O), //Out to Micron
.I(LB) //From Core
);
//dq Interface
IOBUF #(.DRIVE(12), //specify the output drive strength
.IOSTANDARD("DEFAULT"), //specify the I/O standard
.SLEW("SLOW") //specify the output slew rate
)
MIB [15:0](
.O(MIB_O[15:0]), //buffer input into the module
.IO(MIB_IO[15:0]), //buffer inout port
.I(MIB_I[15:0]), //output value from the module
.T(MIB_T) //output when T is low
);
endmodule