I discuss the history of my Kestrel home computer project, where it currently stands, and where I'm taking it in the future.

1. KESTREL
PAST, PRESENT, AND FUTURE
Samuel A. Falvo II <kc5tja@arrl.net>
Fri Jun 14 22:04:28 PDT 2013

2. YESTERDAY'S KESTREL

3. KESTREL 1
CPU 65816
CPU Type 16-bit Accumulator CISC
CPU/Bus Speed (MHz) 4 / 4
RAM (Min/Nom/Max, B) 32K / 32K / 32K
RAM Type Asynchronous
ROM —
Performance 1.00

4. KESTREL 1 (CON'T)
Video —
Audio —
Keyboard —
Mouse —
Other I/O 65C22 VIA providing 1 synchronous serial port,
and 16 bi-directional I/O pins.
Timers Two 16-bit count-down (65C22)
System
Software
—

5. KESTREL 1 (CON'T)

7. TODAY'S KESTREL

8. KESTREL 2
CPU S16X4
CPU Type 16-bit non-Forth MISC
CPU/Bus Speed (MHz) 12.5 / 12.5
RAM (Min/Nom/Max, B) 32K / 32K / 52K
RAM Type Asynchronous
ROM —
Performance 6.25

9. KESTREL 2 (CON'T)
Video MGIA (640x200, bitmapped, black and white)
Audio —
Keyboard KIA
Mouse —
Other I/O GPIA provides 32 bits of fixed, unidirectional
I/O (16 inputs, 16 outputs)
Timers —
System
Software
—

10. KESTREL 2 (CON'T)

11. TOMORROW'S KESTREL

12. KESTREL 2
CPU S16X4B
CPU Type 16-bit non-Forth MISC
CPU/Bus Speed (MHz) 12.5 / 12.5
RAM (Min/Nom/Max, B) 32K / 32K / 52K
RAM Type Asynchronous
ROM —
Performance 6.25

13. KESTREL 2 (CON'T)
Video MGIA
Audio 8-voice, 2-channel, SN76489-inspired PSG
Keyboard KIA
Mouse —
Other I/O GPIA provides 32 bits of fixed, unidirectional
I/O (16 inputs, 16 outputs)
Timers At least two, 32-bit count-down.
System
Software
Port of eForth

14. KESTREL 3A
CPU SeP64X11A
CPU Type 64-bit Forth-Optimized MISC
CPU/Bus Speed (MHz) 13.0 / 13.0
RAM (Min/Nom/Max, B) 256KB / 8MB / 264
RAM Type Asynchronous
ROM —
Performance 6.50

15. KESTREL 3A (CON'T)
Video CGIA-1
Audio 8-voice, 2-channel PSG (Kestrel-2 compatible)
8-voice, 2-channel, 16-bit, DMA-fed DACs
Keyboard KIA
Mouse KIA
Other I/O GPIA-2 provides 128 bits of fixed, unidirectional
I/O (64 inputs, 64 outputs)
Timers At least two, 32-bit count-down.
System
Software
Expanded Port of eForth (vocabularies,
multitasking, simple GUI)

16. KESTREL 3B
CPU SeP64X11B
CPU Type 64-bit Forth-Optimized MISC
CPU/Bus Speed (MHz) 50.0 / 50.0
RAM (Min/Nom/Max, KiB) 256 / 8192 / 264
RAM Type Synchronous
ROM —
Performance 25.0

17. KESTREL 3B (CON'T)
Video CGIA-2
Same as CGIA-1 but with support for synchronous RAM
Audio 8-voice, 2-channel PSG (Kestrel-2 compatible)
8-voice, 2-channel, 16-bit, DMA-fed DACs
Keyboard KIA
Mouse KIA
Other I/O GPIA-2 provides 128 bits of fixed, unidirectional
I/O (64 inputs, 64 outputs)
Timers At least two, 32-bit count-down.
System
Software
Expanded Port of eForth (vocabularies,
multitasking, possibly even a GUI)

18. KESTREL 3B (CON'T)
MMU Segmented with Linear
Paging
Virtual / Effective / Real Address
Space
264 / 280 / 223
Page Size 4096 bytes
SLB Refill Method Software
TLB Refill Method Software

19. KESTREL 3B (CON'T)
EXPERIMENTAL SUPPORT IN FORTH
(MICROKERNEL IN FORTH?)
EXPERIMENTAL PORT OF PLAN 9 FROM BELL LABS

20. CGIA BASIC THEORY OF
OPERATION

21. CGIA BASIC THEORY OF
OPERATION
SEPARATE VIDEO MEMORY FETCH FROM VIDEO MEMORY
INTERPRETATION.

22. CGIA BASIC THEORY OF
OPERATION
USE ALTERNATING LINE BUFFERS TO QUEUE RASTER DATA.

23. CGIA BASIC THEORY OF
OPERATION
VIDEO FETCH CAN OCCUR AT MAXIMUM BUS SPEED
INDEPENDENT OF DISPLAY RATE.
(AS LONG AS IT COMPLETES BEFORE THE NEXT SCANLINE DISPLAYS, YOU'RE GOLDEN!)

24. CGIA BASIC THEORY OF
OPERATION
CPU AND OTHER PERIPHERALS GET LEFT-OVER BANDWIDTH.

25. CGIA BASIC THEORY OF
OPERATION
RAW MEMORY BANDWIDTH DETERMINES HORIZONTAL
RESOLUTION AND COLOR DEPTH.
DESIRED CPU PERFORMANCE AND FRAME RATE LARGELY
DETERMINES VERTICAL RESOLUTION.

26. CGIA BASIC THEORY OF
OPERATION
HORIZONTAL RESOLUTION
25MHZ DOT CLOCK: 320, 640, AND MAYBE 1280.
65MHZ DOT CLOCK: 256, 512, AND 1024.

27. CGIA BASIC THEORY OF
OPERATION
COLOR DEPTHS
1, 2, 4, 8, AND 16 BITS/PIXEL.

28. CGIA BASIC THEORY OF
OPERATION
VERTICAL RESOLUTION
25MHZ DOT CLOCK: 200, 240, 400, AND 480 SUPPORTED.
65MHZ DOT CLOCK: 192, 384, 768 SUPPORTED.

29. MMU BASIC THEORY OF
OPERATION

30. MMU BASIC THEORY OF
OPERATION
PROGRAMS RUN INSIDE AN ADDRESS SPACE.

31. MMU BASIC THEORY OF
OPERATION
RANGES OF ADDRESSES CORRESPOND TO SEGMENTS.
FOR EXAMPLE, $0000-$1FFF MIGHT CORRESPOND TO THE FORTH INTERPRETER.

32. MMU BASIC THEORY OF
OPERATION
SEGMENT REGISTERS INFORM THE CPU OF THE PROCESS
ADDRESS MAP.
SEGMENTS MAP INTO AN 80-BIT VIRTUAL ADDRESS SPACE.

33. MMU BASIC THEORY OF
OPERATION
EXTRA ADDRESS BITS USED TO TELL ONE PROGRAM FROM
ANOTHER.
PREVENTS NEED TO FLUSH ALL ADDRESS MAPPING CONFIGURATION ON EVERY TASK SWITCH.

34. MMU BASIC THEORY OF
OPERATION
TRANSLATION REGISTERS INFORM THE CPU WHERE PAGES
OF A SEGMENT RESIDE IN PHYSICAL MEMORY.

35. MMU BASIC THEORY OF
OPERATION
SEGMENT AND TRANSLATION REGISTERS ARE MANAGED BY
SOFTWARE.
PAGE AND SEGMENTATION FAULT HANDLERS MANAGE THESE
REGISTERS ON BEHALF OF THE CURRENTLY RUNNING
PROCESS.

36. MMU BASIC THEORY OF
OPERATION
DURING A TRAP, CPU MUST PRESERVE NOT JUST PC, BUT
ALSO INSTRUCTION PACKET AEDDRESS, FAULTING ADDRESS,
AND INSTRUCTION SLOT NUMBER.

37. PSG BASIC THEORY OF
OPERATION

38. PSG BASIC THEORY OF
OPERATION
8 VOICES
2 CHANNELS
STEREO GOODNESS.

39. PSG BASIC THEORY OF
OPERATION
EACH VOICE A COMPLETE COPY OF THE SAME CIRCUIT.

40. PSG BASIC THEORY OF
OPERATION
SQUARE WAVE AND PRNG NOISE SYNTHESIS ONLY.
I MIGHT INCLUDE PULSE WIDTH CONTROL FOR MORE
INTERESTING SOUND EFFECTS.

41. PSG BASIC THEORY OF
OPERATION
INSPIRED BY TEXAS INSTRUMENTS SN76489
TEXAS INSTRUMENTS TI-99/4A
SEGA MASTER SYSTEM
... COUNTLESS OTHER USES.

42. GITHUB
KC5TJA@ARRL.NET
http://www.github.com/sam-falvo/kestrel

43. THANK YOU!
Q & A