The document outlines the design and functioning of an n-bit parallel adder and subtractor, detailing how full adders sequentially process input bits alongside carry bits to generate sums or perform subtractions using 2's complement. It discusses the advantages of speed and parallel operation as well as the drawbacks of propagation delays and carry waiting times. The document also describes the switch between addition and subtraction modes using an XOR gate based on an input control signal.

1. Parallel Binary Adder/Subtractor
Dr Vikas Maheshwari
Professor, ECE Dept

2. Working of n-bit Parallel Adder
• firstly the full adder FA1 adds A1 and B1 along with the carry
C1 to generate the sum S1 (the first bit of the output sum) and
the carry C2 which is connected to the next adder in chain.
• Next, the full adder FA2 uses this carry bit C2 to add with the
input bits A2 and B2 to generate the sum S2(the second bit of
the output sum) and the carry C3 which is again further
connected to the next adder in chain and so on.
• The process continues till the last full adder FAn uses the
carry bit Cn to add with its input An and Bn to generate the
last bit of the output along last carry bit Cout.

3. N-bit parallel adder

5. N-bit parallel subtractor

6. Working of n-bit Parallel Subtractor
• The parallel binary subtractor is formed by combination of all full
adders with subtrahend complement input.
• This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their subtraction.
• Firstly the 1’s complement of B is obtained by the NOT gate and
1 can be added through the carry to find out the 2’s complement
of B. This is further added to A to carry out the arithmetic
subtraction.
• The process continues till the last full adder FAn uses the carry
bit Cn to add with its input An and 2’s complement of Bn to
generate the last bit of the output along last carry bit Cout.

7. 4 bit parallel subtractor

8. example
• 1010-1001
• 1010
• 1001 0110+(cin)1= 0111
• 1010
• --------------
• 10001

9. Advantages of parallel Adder/Subtractor –
• The parallel adder/subtractor performs the addition operation faster as
compared to serial adder/subtractor.
• Time required for addition does not depend on the number of bits.
• The output is in parallel form i.e all the bits are added/subtracted at the
same time.
• It is less costly.
Disadvantages of parallel Adder/Subtractor –
• Each adder has to wait for the carry which is to be generated from the
previous adder in chain.
• The propagation delay( delay associated with the travelling of carry bit) is
found to increase with the increase in the number of bits to be added.

10. Parallel Adder / Subtractor

11. Working of Parallel Adder / Subtractor
• When M= 1, the circuit is a subtractor and when M=0, the
circuit becomes adder. The Ex-OR gate consists of two
inputs to which one is connected to the B and other to
input M. When M = 0, B Ex-OR of 0 produce B. Then full
adders add the B with A with carry input zero and hence an
addition operation is performed.
• When M = 1, B Ex-OR of 0 produce B complement and
also carry input is 1. Hence the complemented B inputs are
added to A and 1 is added through the input carry, nothing
but a 2’s complement operation. Therefore, the subtraction
operation is performed.

12. IC 7483 full adder

13. IC-7483

15. Cascading of IC-7483