Raparla Mallikarjuna Rao has an M.Tech in Microelectronics from IIT (BHU) Varanasi with a CGPA of 8.84. He has over 6 years of experience in digital VLSI design, memory design, and analog circuit design. His M.Tech project involved developing a power-efficient and process variation tolerant sense amplifier for mixed signal VLSI circuits. He has worked as a teaching assistant for courses in Microelectronics and VLSI design.

1. Raparla Mallikarjuna Rao
M.Tech (Microelectronics), IIT (BHU) Varanasi.
raparla.mallikarjun7@gmail.com, Mobile: 8904715066, 08019620078
Education
Year Examination Institution Board/University CGPA/Percentage
2014
M.Tech IIT(BHU), Varanasi IIT(BHU), Varanasi 8.84
2011 B.E Sir C R Reddy Engg college Andhra University 8.01
2007 Intermediate Gowtham Junior College Board Of Intermediate
Education Andhra Pradesh
92.2
2005 SSC Z.P.H School, Tangeda Board Of Secondary
Education Andhra Pradesh
87.5
Technical Skills
EDA Tools: Cadence virtuoso platform, Xilinx ISE, Synopsys Design compiler, VCS and HSPICE.
Programming Languages: C, PERL scripting and Verilog HDL.
Interests
Digital VLSI Design, Memory Design, Image Processing, Analog Circuit Design, RTL Design,
Timing Analysis and ASIC Design flow.
Projects
1. M.Tech Project:
Process variation tolerant and Power-Efficient Sense Amplifier for Mixed Signal VLSI circuits.
On one hand a conventional latch-type sense amplifier could trigger sensing failure under severe process variation.
On the other hand, a traditional current-mirror sense amplifier could consume excessive power. In this project I have
proposed modified circuits of these sense amplifiers which will consume less power and which are PVT vari ation
tolerant.
2. M.Tech Mini Project: Asynchronous FIFO Design
The scope of this project deals with issues regarding multiple clock designs and provides different design techniques
to transfer two systems, which are operating at different frequencies without any errors. Designs involving single
clock are like a walk in the park but real challenge comes when one has to face more than one clock. Designers are
faced with problems of METASTABILITY, FREQUENCY difference among the clocks involved, performing
asynchronous data transfer.
Experience:
1. Worked as teaching assistant for Microelectronics and LSI/VLSI design Theory courses.
2. Worked as teaching assistant for the Microelectronics and VLSI CAD lab courses.
3. Taking care of tutorial classes of Digital Electronics course for B.Tech 2nd year students.
Achievements
1. Secured an All India Rank of 323 in GATE 2012.
2. Secured First rank in technical test conducted by ISTE student chapter.
3. Secured 99.3% of marks in Intermediate Mathematics and School topper in SSC (10th standard).
Hobbies & Extracurricular Activities
1. Member of ISTE student chapter.
2. Served as a volunteer for Plantation program organized by IIT (BHU) Varanasi.
3. Participated in TEDxIITBHU-2013.
4. Playing outdoor games such as Cricket, Badminton and Listening to Music.
Personal Details
Present Address:
H.no-733, 4th Floor, 12th cross, C.K Nagar,
Hosa Road, Electronic city, Bangalore-560100,
Karnataka, India.
Date of Birth: 20/08/1990.
Languages: English, Telugu, Hindi.
Strengths: Team player, quick leaner, positive attitude, Learn
from previous mistakes.
Declaration
I hereby declare that the particulars of information stated above are true to the best of my knowledge.
(Raparla Mallikarjuna Rao)