Arnold Labares Early Career Notable Projects [downloadable]

1. ARNOLD LABARES
CV supplemental information: EARLY CAREER NOTABLE ENGINEERING PROJECTS
Next-Generation (NG) 14x14mm metal carrier design
[Intel Corp.]
Environment / project scenario
 Flash products Hi-Volume Manufacturing (HVM) environment: Intel Philippines Flash factory yield for package-
on-package stacking was below 93% as of Q1 ’05. Factory and R&D support groups formed a task force (TF)
to achieve target yield. Factory proposed 2 equipment modifications strategies. To attain low cost impact to
manufacturing (with minimal equipment upgrade required), I proposed to design & develop a next-generation
coil-spring-based planar contact stainless steel metal carrier to replace the plan of record (POR) leaf spring-
based metal carrier for stacking module.
Objective
 To increase stack module yield to 99% or better for hi-volume manufacturing (HVM) certification.
Actions / Responsibilities
As the lead mechanical design engineer for this project, I demonstrated my capabilities on:
 identifying existing design shortcomings with systematic application of Failure Mode and Effects Analyses
(FMEA)
 proposing out-of-the-box mechanical solutions with 3D models (with automation as needed)
 initiating design of experiments (DOE) to gather statistical data on new design’s proof of concept
 balancing form, fit and function (3F’s) on product development
 integration of end-user inputs as design matured
 materials specification
 tolerance stack analyses
 engineering drawings generation (and automation as needed)
 quick 3D modeling and short drawing turn-around time for major design direction shifts
 technical and schedule risk assessments and project go-no-go (GnG) decision making
 internal project management
 regularly updating management and stakeholders on design progress
 steady communications with suppliers on cost and timeline targets
 prototyping or mass production buy-off at supplier sites
Project outcome / results
 Prototype testing data showed that not only did the NG metal carrier increase stack module yield from 93% to
99.3%; it also surpassed metal carrier performance in Intel history with its infinite life and maintenance-free
attributes, per my design intent.
 The 12-pocket NG metal carrier has been implemented at Intel Philippines Flash Factory. Its 28-pocket variant
saves Intel $1.2M by elimination of the need to build a new stacking line to support 3.2M units/quarter ramp.
This successful project also became an entry contender at the prestigious Intel Manufacturing Excellence
Conference (IMEC '06).
Technical Environment
 design conceptualization
 Generic Mechanical (GM) drawing automation
 Geometric Dimensioning and Tolerancing (GD&T - ASME Y14.5M-1994)
 sheet metal design
 metal fabrication (stamping, wire forming, machining)
 prototyping & mass production
Duration
 5 months
NOTE: Arnold cannot show geometric and/or design details of the above per Intellectual Property (IP) policy
(Page 1 of 5)

2. ARNOLD LABARES
CV supplemental information: EARLY CAREER NOTABLE ENGINEERING PROJECTS
Generic Mechanical (GM) drawing automations
[Intel Corp.]
Environment / project scenario
 Flash products & substrates mechanical design: Intel Flash factories and substrate suppliers were
heavily dependent on updated Generic Mechanical (GM) drawings for all development products.
With the fast updating of product external form factors and internal design, Intel R&D
departments lagged behind on updating GM drawings for new products. I saw a need to
eliminate this bottleneck through CAD automation.
Objectives
 Decrease GM drawing generation time for (1) flash package design & (2) substrate design.
Actions / Responsibilities
 Reviewed GM drawing database from past to future package and substrate geometries
 Created family tables of part and assembly models for common components/subassemblies
 Applied CAD programming to control geometric interdependencies between product/substrate
components
 Created GM drawing each for (1) flash package & (2) substrate designs based on automated top-
assemblies
 Created detailed documentations and methodologies for even novice software users to replicate
the advanced automation
 Mentored and enabled mechanical designers/draftsmen to automate drawings on Pro/E guided by
detailed documentations
Project outcome / results
 Beta versions of Intel’s first-ever GM drawing automations were successfully launched. Following
detailed methodologies for both drawing automations, Intel mechanical designers/draftsmen
decreased their GM drawing creation throughput time (TPT) from 3 working days to 1.5 hours.
Technical Environment
 Structured parametrization of 3D parts and assemblies
 Assembly-level programming
 Parametric GM drawing automation (using Pro/ENGINEER at Pro/INTRALINK environment)
Duration
 3 months
NOTE: Arnold cannot show geometric and/or design details of the above per Intellectual Property (IP) policy
(Page 2 of 5)

3. ARNOLD LABARES
CV supplemental information: EARLY CAREER NOTABLE ENGINEERING PROJECTS
14x14mm JEDEC tray pocket redesign
[Intel Corp.]
Environment / project scenario
 Flash products Hi-Volume Manufacturing (HVM) environment: Intel Philippines Flash factory
initiated a high management level Material Review Board (MRB) with a major OEM company after
series of customer returns of flash products with fold edge cracks. Problem root cause was
identified as the bumping of units with JEDEC shipping tray pocket ledges during trucking
operations of products to the OEM customer’s plants in China.
Objective
 Adopt new JEDEC tray design that can minimize or eliminate tray impact on package fold at
shipping.
Actions / Responsibilities
 Formulated the (JEDEC tray) industry’s first pocket design concept with chamfer on 3 edges and
wall on one side
 Worked closely with supplier designers and bridged software incompatibilities for optimized
design collaboration
 Integrated module engineering inputs from process to shipping operations
 Did supplier facilities visit to ensure design conformity and tray quality
Project outcome / results
 Per my design intent, the new JEDEC tray reduced product solder mask crack occurrence from
49% to 4.8% (after shock & vibe test). New design was implemented in Intel Philippines and
China sites and brought closure of MRB with the major OEM customer.
Technical Environment
 Tolerance stack analyses
 product life cycle management
 plastic injection molding
 supplier management
Duration
 3 months
NOTE: Arnold cannot show geometric and/or design details of the above per Intellectual Property (IP) policy
(Page 3 of 5)

4. ARNOLD LABARES
CV supplemental information: EARLY CAREER NOTABLE ENGINEERING PROJECTS
Pro/E Part Library Creation and Maintenance
[Astec Power]
Environment / project scenario
 Printed Circuit Board (PCB) mechanical design: With Astec’s migration of MCAD platform from
AutoCAD (R14) to Pro/ENGINEER (v19) in 1999, a need arose to create a standard 3D library of
electronic power supply components for PCB mechanical design engineers to use and reuse for
3D PCB design. I was hired and trained to support this 3D model database.
Objective
 Create, develop and maintain the Pro/E part library for common electronic power supply
components.
Actions / Responsibilities
 Learned solid 3D modeling using Pro/ENGINEER
 Systematically reviewed all GM drawings for each product (i.e. diodes, resistors, capacitors) from
all suppliers for geometric and dimensional commonalities
 Created generic part for each component (per color cosmetic attribute)
 Parametrized all variable dimensions under each generic part and populated family tables using
dimensions from supplier GM drawings
 Constantly updated part numbers database with existing 3D models
 Supplied 10 design teams with 3D component models for PCB mechanical design needs
Project outcome / results
 Pro/E library removed the burden from all PCB mechanical design engineers to create their own
3D model parts for PCB assemblies design and consequently eliminated the need for one more
mechanical design engineer per design team.
 Part Library has been extensively used to this day by Astec R&D-Design operations in the
Philippines, Hong Kong, China, Taiwan and Japan.
Technical Environment
 Parametric parts modeling with extensive use of part-level relations and family tables
Duration
 2.5 years
NOTE: Arnold cannot show geometric and/or design details of the above per Intellectual Property (IP) policy
(Page 4 of 5)

5. ARNOLD LABARES
CV supplemental information: EARLY CAREER NOTABLE ENGINEERING PROJECTS
Integration of Cadence Allegro ECAD & Pro/E MCAD for efficient electrical-
mechanical design of PCB assemblies
[Astec Power]
Environment / project scenario
 Printed Circuit Board (PCB) electro-mechanical design: Importation of Allegro electrical CAD files
into Pro/E occasionally resulted to 90°, 180° & 270° misorientation of components in the 3D PCB.
The need arose to optimize “handshake” of software to eliminate time-consuming modification of
3D PCB for mechanical design.
Objective
 Standardize Allegro export and Pro/E import configurations for precise 3D PCB generation.
Actions / Responsibilities
 Co-headed the combined electrical-mechanical design standardization team
 Integrated and optimized the x- y- z- coordinate system conventions between electrical and
mechanical CAD libraries
 Documented the ECAD importation procedures and proliferated the methodology to design team
mechanical engineers
Project outcome / results
 Combined with full Pro/E implementation, this project cut down overall electronic power supply
design time by 80% by elimination of 3D assemblies rework for PCB mechanical design.
Technical Environment
 Pro/ECAD (Pro/E software module for direct import of electronic CAD files for automated PCB
mechanical modeling for product design)
Duration
 6 months
NOTE: Arnold cannot show geometric and/or design details of the above per Intellectual Property (IP) policy
(Page 5 of 5)