Arnold Labares Engineers Australia CDR

Professional Mechanical Engineer
Competency Demonstration Report

DECLARATION

Passport-size
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All statements of fact in this report are true and correct and I have made
claims of acquired competencies in good faith. The report is my own work
and is a true representation of my personal competence in written English. I
confirm that I understand that members of the engineering team in Australia
are required to display a commitment to exercising professional and ethical
responsibility in all aspects of their work.

Printed Name: ___

Signature: ___

Date: ___

Page 1 of 30 Arnold Labares 30-Aug-07


CURRICULUM VITAE

EXPERIENCE
Feb 1999 – Jul 2001 Astec Power Philippines, Inc. (www.astec.com) Manila, Philippines
Mechanical Design Engineer – Electronic components 3D part library creator and designer of tailor-made
power supply mechanical and thermal components
 Drastically cut down overall electronic power supply design time by 80% by:
1. Integrating Cadence Allegro Electronics CAD (ECAD) export files and Pro/ENGINEER Mechanical CAD
(MCAD) input files to semi-automate Printed Circuit Board (PCB) electrical-mechanical design flow
2. Pioneering mechanical design tool migration from 2D-based AutoCAD to 3D-based Pro/E allowing engineers to
extensively reuse common parametric 3D models
 Single-handedly created, developed and maintained the 3-D solid models Part Library of Electronic Power Supply
Components for automated mechanical design of PCB assemblies
 Part Library now a legacy and extensively used to this day by Astec R&D-Design operations in the Philippines,
Hong Kong, China, Taiwan and Japan
 MCAD support to 10 design teams eliminated the need for 1 mechanical design engineer per team
April 2002 – August 2006 Intel Technology Philippines, Inc. (www.intel.com) Cavite, Philippines
Mechanical Design Lead: Material Handling Media – main (metals and plastics) material handling media
design engineer for Philippines, Malaysia and China operations
 Redesigned top & bottom 48mm copper frame carriers for Front Of Line (FOL) assembly of Folded Stacked – Chip Scale
Package (FS-CSP)
 New design saved Intel US$1.1M per year of implementation
 Brainchild Next-Generation (NG) 14x14mm metal carrier concept with planar package contact emerged as the best concept
among three design and equipment approaches for optimal FS-CSP package stacking
 12-pocket carrier prototypes line testing validated the elimination of substrate wrinkling & package dropping
problems common to previous-generation metal carrier
 28-pocket densified carrier variant prototyping became the Plan of Record (POR) FS-CSP stacking carrier to
support 3.2M units/quarter milestone ramp at Intel Cavite and Shanghai sites
 Authored 4 related Invention Disclosure Forms (IDFs) for possible patent applications
 Released 3 Continuous Improvement Plan (CIP) designs for hi-volume manufacturing of e-spring-type 14x14mm metal
carrier for package stacking
 Rev-4 carrier design received Q2 ’05 Quarterly Recognition Award (QRA) nomination for 99.2% yield
breakthrough from 97.8% of POR carrier
 Designed revolutionary JEDEC tray pocket design tailored for processing and shipping FS-CSP
 Pocket design became one of key solutions for closure of Fold Trace Crack Material Review Board (MRB) with a
major Original Equipment Manufacturer (OEM) customer
 Redesigned top & bottom 72mm frame carriers for FS-CSP FOL assembly process
 Design led to characterization and final selection of a copper alloy over an aluminum alloy as POR material for
72mm frame carriers
 Design increased FS-CSP FOL assembly yield by 35%
 Designed Front of Line (FOL) and End of Line (EOL) variants of 72mm frame carrier extruded aluminum magazines
 Successfully automated Generic Mechanical (GM) drawings creation for package and for substrate design
 Both (beta version) automations drastically cut down GM drawing creation throughput time (TPT) from 3 days to
1.5 hours
 Designed jigs and fixtures for Low Density Interconnect (LDI) Package Validation Laboratory
Sept 2006 – May 2007 Lighthouse Technologies Ltd. (www.lighthouse-tech.com) Shatin, Hong Kong
Sr. Mechanical Engineer – Factory (Huizhou City, Guangdong Province, China) Mechanical Design & Development
Engineering team leader; analyze and solve product issues; responsible for scheduling and commissioning of projects;
develop new technology



CURRICULUM VITAE

SPECIAL SKILLS
 Seven (7) years experience on Research and Development (R&D) with focus on mechanical design

 11900 usage hours on Pro/ENGINEER MCAD software (releases 19, 20, 2000i, 2000i2, 2001, WildFire 1.0,

WildFire 2.0) with the following expertise:
 User defined parameter-controlled dimensioning
 Family Table-driven part library creation
 Part- and assembly-level programming
 Design drawing automations
 Sheet metal design
 Complex metal and plastic parts and assemblies design
 Core design engineer for Intel’s Global Metal Media Working Group (GMMWG)

 Core design engineer for Intel’s Global Plastic Media Working Group (GPMWG)

 Pro/ENGINEER super user and Pro/INTRALINK administrator for Intel Philippines site

 Knowledgeable on:

 semiconductor assembly and test processes and equipment
 printed circuit board mechanical assemblies design
 Geometric Dimensioning and Tolerancing (GD&T - ASME Y14.5M-1994)
 machining, wire forming, metal stamping & injection molding manufacturing processes
 Design for Manufacturability (DFM)
 project management/supplier management
 Failure Mode and Effects Analyses (FMEA)
 Finite Element Analyses (FEA)
 Analysis tools Pro/Mechanica, Flotherm, Icepak, Ansys, Abaqus, Moldflow, CFDesign
 Experienced in a virtual factory and multi-cultural corporate environment

 Experienced on Six Sigma manufacturing environment

PERSONAL TRAITS
 Results- and people-oriented

 Passionate mechanical designer

 Able to work self-directed

 Excellent command of English language; International English Language Testing System (IELTS) certified

 Proven leadership skills

EDUCATION
University of the Philippines, Diliman, Quezon City, Philippines, 1998
o BS Metallurgical Engineering
o National Steel Corporation corporate scholar
o working student Oct ’95 – Oct ‘98

LEADERSHIP IN COLLEGE ORGANIZATIONS
 Tau Alpha Fraternity: Fraternity Head - Grand High Alpha (1997-1998); Formed the 2nd Inter-Fraternity

Council through the U.P. Diliman Accord together with fourteen (14) other fraternities
 International Order of DeMolay: Chapter Vice Head - Senior Councilor (1994); Spearheaded the 1st Luzon-

wide inter-chapter band competition “Bandahan ’94” and successfully solicited prizes from corporate sponsors

INTERESTS
 Military history, military hardware, Tom Clancy, Mario Puzo, practical shooting, airsoft war games, Basketball,

Chess, Badminton, Swimming, gym



CURRICULUM VITAE

TRAININGS

Intel Technology Philippines, Inc.
 Software training: Introduction to ABAQUS, September 13-17, 2004, Intel Cavite, Philippines
 Technical training: Geometric Dimensioning and Tolerancing (ASME Y14.5M-1994) (refresher),
May - June, 2004, Intel Cavite, Philippines
 Technical training: non-CPU Handling Media Design: Plastics, February 2004, Intel Folsom, CA,
USA
 Technical training: CPU Handling Media Design: Metals, October 2003 – January 2004, Intel
Chandler, AZ, USA
 Software training: Pro/ENGINEER (release WildFire 1.0) Update Training, November 19-20, 2003,
Phoenix, AZ, USA
 Software training: Designing Sheet metal products with Pro/ENGINEER (release WildFire 1.0),
November 13-14, 2003, Sunnyvale, CA, USA
 Software training: Fundamentals of Pro/MECHANICA (release 2001) Structure/Thermal, October
20-24, 2003, San Diego, CA, USA
 Non-technical training: Behavioral Interviewing, March 19, 2003, Intel Cavite, Philippines
 Software training: Pro/INTRALINK User and Administrator Training, December 5 – 6, 2002, Intel
Cavite, Philippines
 Technical training: Geometric Dimensioning and Tolerancing (ASME Y14.5M-1994), October 14 –
November 29, 2002, Intel Chandler, AZ, USA
 Technical training: Understanding Mechanical Drawings, October 14, 2002, Intel Chandler, AZ, USA
 Software training: Fundamentals of Drawing using Pro/ENGINEER (release 2001), October 7-11,
2002, El Segundo, CA, USA
 Technical training: Generic Package Mechanical Design, October 14 – November 29, 2002, Intel
Chandler, AZ, USA
 Software training: Fundamentals of Design using Pro/ENGINEER (release 2001), September 30 –
October 4, 2002, El Segundo, CA, USA
 Technical training: Technical Structured Problem Solving, September 29, 2002, Intel Cavite,
Philippines
 Software training: Introduction to Pro/ENGINEER (release 2001), September 23-27, 2002, Intel
Cavite, Philippines
 Non-technical training: Effective Meetings, June 13, 2002, Intel Cavite, Philippines
 Software training: Cadence Advanced Package Designer (release 14.0), May 13-17, 2002, Singapore

Astec Power Philippines, Inc.
 Software training: Total Optimization Packaging Software (TOPS), May 10-12, 2000, Astec Training
Area, Pasig City, Philippines
 Software training: Sheet metal Design using Pro/ENGINEER (release 19), April 24-28, 2000, Astec
Training Area, Pasig City, Philippines
 Technical training: Enhanced Mechanical Engineering Course: METALS AND PLASTICS
module, February 28 – March 1, 2000, Astec Training Area, Pasig City, Philippines
 Technical training: Enhanced Mechanical Engineering Course: HEAT TRANSFER module,
December 6, 8 & 10, 1999, Astec Training Area, Pasig City, Philippines
 Software training: Solid Three-dimensional (3D) Modeling using Pro/ENGINEER (release 19),
February 1999, Astec Training Area, Pasig City, Philippines



CONTINUING PROFESSIONAL DEVELOPMENT

Bulk of my career-enabling trainings is detailed on the 3rd page of my curriculum vitae
(CDR page 4) which I would classify as:
 Job-specific technical trainings
o Understanding Mechanical Drawings
o Geometric Dimensioning and Tolerancing (ASME Y14.5M-1994)
o Generic Package Mechanical Design
o CPU Handling Media Design: Metals
o non-CPU Handling Media Design: Plastics
o Technical Structured Problem Solving
o Enhanced Mechanical Engineering Course: METALS AND PLASTICS module
o Enhanced Mechanical Engineering Course: HEAT TRANSFER module
 Software trainings (for generic mechanical design)
o Introduction to Pro/ENGINEER
o Fundamentals of Design using Pro/ENGINEER
o Fundamentals of Drawing using Pro/ENGINEER
o Designing Sheet Metal products with Pro/ENGINEER
o Pro/ENGINEER (WildFire) Update Training
o Pro/INTRALINK User and Administrator Training
o Total Optimization Packaging Software (TOPS)
 Software trainings (for design simulation)
o Fundamentals of Pro/MECHANICA (release 2001) Structure/Thermal
o Introduction to ABAQUS

For my development of Intel’s Next-Generation Metal Carrier (3rd career episode highlight),
I delivered the following invention disclosures and technical papers:
o Four novel invention disclosures
o Technical paper entries at:
 Intel Assembly Technology Technical Journal (IATTJ ‘05)
 Intel Manufacturing Excellence Conference (IMEC ‘06)

I also gained the following manufacturing facilities exposures on my mechanical design
practice to date:
o Metal parts fabrication facilities (wire forming, stamping, machining operations)
o Plastic molding facilities (integrated tool-making and injection molding facilities)

In my last job, I gained valuable experience as a Senior Mechanical Engineer leading the
mechanical design team of local engineers and technicians in the company’s factory in Huizhou
City, Guangdong Province, China. It was a different facet of my engineering development with me
instilling design basics to my team, coaching the engineers, introducing design continuous
improvement process (CIP) and managing multiple projects to deliver results in a new business
environment and culture that was different from my US-style engineering background.

My career episodes themselves show a systematic and continuous development of my
mechanical design engineering career with my development of 3D modeling competency (1st
episode highlight), mastery of creating 2D drawings from 3D models (2nd career episode highlight)
and utilizing both competencies as fundamental enablers for my delivering integrated design
solutions to a mission-critical corporate challenge (3rd career episode highlight).



CAREER EPISODE 1

CREATION, DEVELOPMENT AND MAINTENANCE OF ASTEC PRO/E PART LIBRARY
OF STANDARD ELECTRONIC POWER SUPPLY COMPONENTS

CE 1.01 Intellectual Property notice: Arnold cannot show geometric images, specs, and
related documents of this subject matter per Astec IP policies.

CE 1.02 A. INTRODUCTION
This career episode spans my entire employment at Astec International Limited
Philippine Branch (formerly Astec Power [Philippines]) in Manila from February 1999 to
July 2001. I started off as a contractual Mechanical Technician and was promoted to a
regular Mechanical Engineer.

CE 1.03 B. BACKGROUND
Nature of overall engineering project
Astec’s business is on design and manufacturing of AC/DC & DC/DC electronic power
supplies (EPS). In 1999, Astec executed its mechanical design process improvement
scheme with tool migration from non-parametric two-dimensional (2D)-based AutoCAD
13 (by Autodesk Inc.) to parametric three-dimensional (3D)-based Pro/ENGINEER 19
(by Parametric Technology Corp.). To reap the full advantages of using and reusing
standardized 3D models to eventually shorten time-to-market, a 3D part library was
essential. Aside from being far more expensive to purchase an off-the-shelf electronic
components mechanical library, libraries then were also not tailor-fit for Astec’s
requirements so management decided to build its part library in-house.

CE 1.04 I was then a fresh BS Metallurgical Engineering graduate having a difficult time getting
a job as local industries and job market were in a slump amid the still-prevailing Asian
financial crisis. Despite being not a Mechanical Engineering graduate, my Engineering
Drawing skills (University of the Philippines – Engineering Science 1 course) landed me
to this Astec job to build a 3D part library. I was happy then to jump-start my
engineering career and put some bucks on my empty pocket.

CE 1.05 Project objectives
Astec engineering initially assessed the Pro/E Part Library creation to be just a single
one-time project. With no long-term employment offer, I was hired as a contractual
Mechanical Technician to:
1. Achieve basic Pro/E user competency and
2. Build the 3D part library of preferred EPS components
Part library scope covered all preferred common-geometry EPS components and
excluded unique-geometry components (i.e. sheet metal and plastic enclosures,
cabling, heat sinks, shipping boxes).

CE 1.06 Statement of duties
I primarily owned the construction, development, updating and maintenance of Astec
Pro/E Part Library. As a Pro/E pioneer, I also co-owned part library proliferation and
Pro/E enabling of mechanical design engineers together with my supervising senior
mechanical engineer.



CAREER EPISODE 1

CE 1.07 Nature of particular work area
My primary mechanical computer-aided design (MCAD) chores were:
 Part modeling of generic models of different classes of common PSU
components
 Parametrization of variable dimensions based on corresponding component
supplier/industry drawing specs
 Populating the Pro/TABLE for each generic model and ensuring successful
regeneration
 Continuous optimization of library generic models for design application
 Constant updating of Pro/E Part Library at intranet engineering database

CE 1.08 Organizational structure chart
I belonged to Advanced Engineering/Technology Core Group (Tech Core) which
benchmarks and certifies design tools, develops methodologies and provides
(electrical, mechanical, thermal) simulation support to product design teams. Please
refer to chart below for details.

CE 1.09 C. PERSONAL WORKPLACE ACTIVITIES
Foundation
My engineering career began with 2-week BASIC 3D MODELING crash-course on-the-
job training from my supervising senior engineer, our most advanced Pro/E user. Day
in day out I learned and practiced doing solid and cut features with protrusions,
revolves, blends, sweeps, helical sweeps, rounds, among others. Then I learned
creation of user-defined parameters for variable dimensions and then creation of
geometry-controlling relations that I used on family tables to create functional generic
models.

CE 1.10 Wizardry
Within a month I literally fell in love with 3D modeling and enthusiastically learned the
wise use of datum planes, curves and axes as feature references, yes-no parameters
on relations and on family tables to show/suppress features (i.e. negative terminals for



CAREER EPISODE 1

cylindrical-shaped electrolytic capacitors). I then applied cosmetics (i.e. application of
color, textures, transparency, reflections, and refractions [for applications like in
cartridge fuses]). I also intensively used simplified reps, patterning (i.e. for leads in IC
packages), grouping of features (i.e. screw head) and sheet metal modeling for
applicable components.

CE 1.11 To boost productivity, I extensively used Pro/E keyboard macros, created my own
config file (MINE.pro) to personalize my Pro/E graphic user interface (GUI), used both
trail files (to update existing generics) and multi-level family tables (i.e. to model sub
variants of variable parameters), used Microsoft Excel to edit Pro/TABLE, developed a
Pro/E sections database of any new geometry that I encountered, a Modeling Request
Form (that I uploaded to our intranet for design engineers to use) and Pro/E template
start part and start assembly files with built-in Astec parameters.

CE 1.12 Passion
Time came when my supervisor could no longer answer some of my advanced
modeling inquiries so I increasingly referred to several Pro/ENGINEER Release 19.0
book manuals that came with our licenses, among which the Fundamentals, Part
Modeling User’s Guide and Assembly Modeling User’s Guide became my
modeling bible.

CE 1.13 Specs- and standard-driven delivery
I coordinated regular updates from our Component Engineering department for new
part numbers in the horizon and religiously referred to the respective Approved
Vendor Specs and our own Part Number Assignment (QP3408), Printed Circuit
Board (PCB) Design Rules, Design for Manufacturability and Workmanship
Standards as library required component geometry configuration as assembled on
PCBs (i.e. radial or tangent mount).

CE 1.14 For my whole Astec employment, I have created a total of 455 generic models (more
than 5000 instances) with realistic cosmetics for Astec Pro/E Part Library of these
preferred electrical and mechanical component classes: insulators, capacitors (film,
ceramic, SMD, electrolytic, polyester), cartridge fuse, ferrite cores, fuse clips,
connectors, plugs, AC receptacles, plastic articles, bushings, transformer
bobbins (plastic), discrete transistors, ICs (different package outlines), diodes
(discrete, chip, LEDs, zener), rectifier packages, optocouplers, resistors (film chip,
metal film), trimming potentiometer, hecnum wires, switches, relays, chokes,
screws, washers, fasteners and miscellaneous metallic parts.

CE 1.15 My career break came when business need compelled management to regularize my
employment, this time, as a mechanical engineer to bridge the Pro/E competency gap
between Tech Core and design team engineers amid Astec’s Pro/E migration program;
most AutoCAD-savvy engineers then still needed skill improvement on Pro/E.



CAREER EPISODE 1

CE 1.16 Rubber meets the road
I constantly updated the library and uploaded to intranet and (later on) to
Pro/INTRALINK (Pro/E CAD database management tool) for use by mechanical
engineers to model PCB assemblies for interference check and thermal simulations
(when needed) on EPS design. Since PCB components comprise more than 90% of any
product Bill of Materials (BOM), the next logical step to design efficiency was to
automate PCB assembly modeling with direct importing of board layout files; a Pro/E
capability with its Pro/ECAD module. So my supervisor and I trialed, mastered and
documented the ECAD 3D PCB Assembly Methodology for proliferation to the design
teams.

CE 1.17 Library crossroads
After doing several PCB ECAD assemblies, I noticed the discrepancy between the MCAD
& ECAD libraries that consistently resulted to 90°, 180° and 270° mis-orientation of
some components that required time-consuming manual assembly modification for
each. Root cause was the different universal coordinate system convention (location
and orientation) for some component classes between MCAD & ECAD libraries. The
ECAD library, developed years ahead, only concerned on electrical properties and
component macros (board footprints – not to be confused with Pro/E keyboard macros)
while the MCAD library concerned the 3D orientation of each component as well.

CE 1.18 I highlighted this synchronization issue to management and as the owner-originator of
the MCAD library, I co-headed the standardization project with the ECAD library team.
After two months of weekly meetings, I released my Standard Macros Configuration
Proposal for Cadence and Pro/E Libraries to standardize x-y-z-coordinate system origin
conventions between the CAD libraries. With management’s approval, it was a bitter
pill for the ECAD team to rework their established library as it benefited the mechanical
design engineers by reducing ECAD PCB assembly time by 80% with elimination
manual rework due to component mis-orientations.

CE 1.19 Evolution
As the part library became a linchpin on Astec’s product mechanical design flow and as
my CAD competency advanced (logging a total of 5174.4 Pro/E usage hours in only 28
months), my tasks developed to:
 Manual or ECAD-automated PCB 3D assemblies creation for the design teams
 Training mechanical engineers on ECAD import for seamless PCB mechanical
modeling
 Coaching of mechanical engineers on Pro/E part and assembly modeling as
succeeding versions (20, 2000i and 2000i2) were released

CE 1.20 Legacy
The Pro/E Part Library that I created has been extensively used to this day by Astec
engineering operations in the Philippines, Hong Kong, China, Taiwan and Japan;
testament to the robustness of my 3D models and the success of this project.



CAREER EPISODE 1

CE 1.21 D. SUMMARY
I not only exceeded management’s expectations of achieving Pro/E competency and
creating the part library but also added value to Astec’s design engineering by:
 Playing a key role on MCAD – ECAD libraries standardization for seamless
downstream design processes;
 Pro/ECAD mastery and subsequent enabling of design engineers and
 Coaching Pro/E to novice users.

CE 1.22 This career milestone made me passionately and confidently pursue mechanical
engineering career path; having equipped me with “very solid” 3D modeling
competency, a mechanical design engineer’s essential skill, the key foundation for my
2nd and 3rd career episodes.



CAREER EPISODE 2

CONCEPTUALIZATION, DEVELOPMENT, DOCUMENTATION AND
PROLIFERATION OF INTEL’S FIRST GENERIC MECHANICAL (GM) DRAWING
AUTOMATION FOR SEMICONDUCTOR SUBSTRATE DESIGN

related documents of this subject matter per Intel IP policies.

I performed this career episode in September and October of 2003 at the Cavite Flash
products factory of Intel Philippines. I was the Package Design Engineer (Mechanical) of
the R&D organization’s Core Competency Group (CCG) supporting Intel’s Flash products
assembly operations in Asia (Philippines & China).

Intel out sources its substrate needs for its Flash memory business. An essential
document needed by subcontractors to manufacture substrates per Intel design intent is
the substrate generic mechanical drawing which, by 2003, has been done using non-
parametric AutoCAD version 14. With every new substrate design, engineers/technicians
either make new drawing or save existing drawing to a new file and make the
modifications across all sheets, which take them three days to finish prior to supplier
release. Given the numerous product lines (each normally having substrate design
iterations) in Intel’s Flash business roadmap, I highlighted this 3-day drawing
creation throughput time (TPT) to management as a process bottleneck that needed
improvement. Knowing the capabilities of Intel’s plan of record (POR) mechanical
computer-aided design (MCAD) tool, Pro/ENGINEER (“Pro/E” version 2001 then), I was
motivated to eliminate the bottleneck through CAD automation.

CE 2.04 Project objectives
To eliminate the 3-day process bottleneck, I instigated a Continuous Improvement
Process (CIP) scheme to:
1. Semi-automate Generic Mechanical (GM) drawings generation with a fully-automated
3D model assembly template
2. Proliferate the automation to the rest of substrate design teams across Intel



CAREER EPISODE 2

After successful Generic Package Mechanical Design corporate training at our R&D
organization’s parent site in Arizona, USA, in 2002, I “own all mechanical design
tasks (generic package mechanical design, tolerance stack analyses, 3D
modeling for FEA simulations, jigs and fixtures design) for all of Intel’s small
form factor (14x14mm or smaller) semiconductor packages being developed
for Flash products operations (Philippines, China)”. This job function is heavily
rooted on my 3D solid modeling skills (1st career episode highlight).

CE 2.06 Organizational structure chart1
Assembly Technology Development – Philippines (ATD-P) was Intel’s R&D group that
developed and certified semiconductor packaging technologies, methodologies and
materials for Flash business operations (Philippines and China). To augment its core
Module Engineering (process development) capability, ATD-P created a Core
Competency Group (CCG) in April 2002 to develop key capabilities for package design
(electrical analyses and design, generic mechanical design, materials engineering,
mechanical [thermal] design, mechanical [structural] design, silicon integration and
substrate integration). I was hired to be ATD-P CCG’s content expert on generic
mechanical design. Please refer to following chart for details.

For this drawing automation project, my MCAD activities involved the following:
 Creation of 2-metal-layer BT substrate template three-dimensional (3D) assembly
using Pro/E
 Parametrization of variable substrate design dimensions into CAD modeling user-



CAREER EPISODE 2

defined parameters
 Working closely with Parametric Technology Corp. (“PTC” – developer of Pro/E)
global technical support teams
 Integration of user-defined parameters into programming scripts both on parts and
assembly levels of substrate template model
 Creation of template drawing optimized to automatically show necessary views and
dimensions of automated 3D substrate model
 Incorporation of corporate-standard Geometric Dimensioning and Tolerancing
(GD&T) schemes on template drawing

Successful automation prototype
During my first corporate training in Arizona in 2002, Intel’s Folsom, California site
MCAD team was automating design of microprocessor test kit components using Pro/E’s
CAD programming module; Pro/PROGRAM. Upon my return to the Philippines, I applied
programming on one of my key deliverables; Flash packages GM drawings generation.
Having no Pro/PROGRAM training, I diligently combed through Pro/E manuals and
sought PTC technical support and successfully programmed dimension parameters pass
down from a complete Flash package 3D assembly to its parts. This subsequently cut my
GM drawing generation TPT by 95% as prerequisite 3D assembly creation became fully-
automated. I documented this package design GM drawing automation and shared to
our design technicians for them to replicate the process. Without much fanfare, this
automation was implemented in our local team. This ‘skunk works’ project gave me
key learnings and high confidence to automate GM drawing creation of substrates with
its intricate geometries.

CE 2.09 Planning and execution
With corporate-wide proliferation as my end in mind, I engineered every aspect of this
automation and easily got my manager’s approval on this “zero budget” substrate
design GM drawing automation project timeline:

CE 2.10 Spec review was my comprehensive review of following corporate governing specs,
among others, to prevent any detail from being overlooked:
 Molded Array Package (MAP) Design Rules for 48.875mm Strip (Document 08-
2108)
 CAD Graphics Requirement Policies and Procedure (Document 15-354)
 Subcontractor Assembly Requirements for Design (Document 08-2045)

CE 2.11 I then did line tours and focus meetings with respective Flash factory end-user module
engineers for process parameters review. I was satisfied that the design rules



CAREER EPISODE 2

covered all details.

CE 2.12 3D modeling is my passion and here I started the exciting ‘Pro/E acrobatics’. Modeling
a 2-metal-layer substrate is child’s play but parametrically regenerating it with all
possible die size-orientation sets is not. This is particularly so for bottom metal
circuitry wherein outermost 0.2mm-wide horizontal copper saw lanes terminate at four
3mm  copper pads at each outer corner of mold panels. The parametric hurdles
were (1) former’s distance from central longitudinal plane is variable while latter’s is
fixed (24.5mm; each 59mm apart) for all designs so (2) outermost saw lanes could fall
below, collinear, or above the pads depending on die matrix, which (3) should also
terminate straight to pads’ center at minimum distance. I overcame these by creating an
intermediate (real number) parameter using relation PERIMETER_OFFSET =
PANEL_UNIT_Y_ARRAY*(UNIT_Y_DIM_IN_PANEL+.3)/2. At pad locations, I then created
identical datum curve features of 3mm circles with two mirrored lines (any angle from
vertical) originating from their centers. These lines terminate to actual location of
outermost saw lanes as shortest “tie lines”. This datum curve became parent feature for
actual tie lines with their creation subject to part-level programming condition:
if PERIMETER_OFFSET:
< 24.5 create feature INTERSECTION_INNER
= 24.5 create feature INTERSECTION_FIXED
> 24.5 create feature INTERSECTION_ANGLED.
Depending on PERIMETER_OFFSET, only one “INTERSECTION” tie line is created; other
two automatically suppressed. The rest of inner saw lanes were easily modeled by
patterning.

CE 2.13 The (copper) top metal circuitry unit identifiers are 1.5mm-height alphanumeric
characters (at strip’s south side) for all die columns and numeric characters (at strip’s
east side) for all die rows. Regardless of die matrix, these identifiers have to be
continuous (i.e. “A to Z”) thus posing a modeling challenge for alphanumeric identifiers
since number of die columns per panel vary in every design. I overcame this by creating
a dedicated array of solid-protrusion alphanumeric identifiers and accompanying
rectangular cut on it to only show necessary identifiers for each panel. I then
parametrized these feature pairs, totaling five, for identifiers to always fall center on
every die column/row.

CE 2.14 To validate model robustness, I created an assembly-level family table with realistic die
size-orientation figures which ran successful regeneration.

CE 2.15 The GM drawing creation I designed on Pro/INTRALINK (data management) session of
Pro/E taking advantage of INTRALINK’s (version 3.1) batch renaming functionality while
maintaining files associativity. The 5-sheet third-angle projection drawing I made:
 came with a drawing set-up file (strip_migration_drawing_setup.dtl) that users
activate to make GD&T schemes automatically conform to corporate specs;
 automatically showed die unit count using assembly relation UNITS_PER_STRIP =
4*(PANEL_UNIT_X_ARRAY*PANEL_UNIT_Y_ARRAY);
 served as automation template with set views updating with every 3D assembly
design modification

CE 2.16 Assembly-level programming was the key enabler for my automation design intent
wherein: (1) substrate designer opens cXXXXX_rYY_bt_strip.drw template drawing in
INTRALINK Workspace then (2) rename it and associated files with entry of
nomenclature parameters PROJECT NUMBER (XXXXX) & REVISION NUMBER (YY). Then



CAREER EPISODE 2

user (3) opens cXXXXX_rYY_bt_strip.asm template assembly and (4) (Regenerate >
Automatic > Enter > Select All > Done Sel) follows each system prompt to enter values
of (real number) parameters STRIP_THICKNESS, UNIT_X_DIM_IN_PANEL,
UNIT_Y_DIM_IN_PANEL, PANEL_UNIT_X_ARRAY, PANEL_UNIT_Y_ARRAY & (yes-no
parameter) LEFT_SIDE_UNIT_FIDUCIALS. The assembly passes down these parameters
to its parts prior to regeneration. Then user (5) shifts back to drawing window to (6)
make finishing touches (i.e. move views, show dimensions, update title block) and
drawing’s done.

CE 2.17 For preliminary documentation, I detailed all pertinent data, guidelines,
methodologies, user capabilities and tools requirements in a document to enable all Intel
substrate designers to execute the automation with emphasis on novice Pro/E users.

CE 2.18 Success indicators
At pilot testing I sought feedbacks from our local design technicians (novice Pro/E
users) and simulated my end in mind: road show demonstration for corporate-wide
proliferation. With my initial guidance plus documentation, they did 10 automation runs
on different die size-orientation sets and (1) averaged 3 hours TPT new drawing
creation for 87.5% TPT cut.

CE 2.19 At final documentation I checked in all automation files to Commonspace and
uploaded (Rev 1) documentation to corporate MCAD intranet; hyperlinked for round-the-
clock accessibility.

CE 2.20 I executed my carefully planned finale, road show demonstration, during my 2nd
corporate technical training at parent R&D site in Arizona that October at separate
sessions. My (2) audience were amazed to witness seamless substrate assembly-to-
parts parameters pass down and (3) none came up with major areas of improvement
that I solicited. Most importantly, (4) the department manager issued me an action
required (AR) item to proliferate this automation with their Pro/E-experienced substrate
team which (5) benchmarked 1 hour (or 96% TPT cut). Mission accomplished!

CE 2.21 D. SUMMARY
With my solicited module and end-users inputs, I single-handedly conceptualized and
developed this automation and systematically executed my aggressive objectives which
quantitatively reduced substrate GM drawing creation throughput time (TPT) by 87.5-
96% during corporate-wide proliferation. Bottom line is this brainchild automation of
mine improved the productivity of Intel’s substrate designers by factor of 8 to 24.

CE 2.22 This drawing automation embodies a successful continuous improvement process (CIP)
project that made obsolete a state-of-the-art technique after delivery of tangible success
indicators, consistent with Intel’s engineering ethos of “challenging the status quo” and
“raising the bar”.



CAREER EPISODE 3

CONCEPTUALIZATION, DESIGN, DEVELOPMENT AND PROTOTYPING OF
INTEL’S NEXT-GENERATION (NG) 14MM METAL CARRIER
FOR PACKAGE STACKING

related documents of this subject matter per Intel IP policies.

I performed this career episode in the middle half of 2005 at the Cavite Flash
products factory of Intel Philippines. I was the R&D group’s Mechanical Design Lead
(Material Handling Media) then supporting Intel’s Flash products assembly operations
in Asia (Philippines & China).

Hi-Volume Manufacturing (HVM) of Folded Stack–Chip Scale Package (FS-CSP)
(commercial name PXA272) applications processor for mobile phones: Intel’s FS-CSP
stacking module yield was below 93% as of Q1 ’05. Production challenge further
heightened when management demanded an output ramp to 3.2 million units/month to
intercept strong sales forecast.



CAREER EPISODE 3

CE 3.04 Objectives and scenario
Intel business process called for kicking off of combined engineering-management Task
Force (TF) to achieve the following by end of Q3 ’05:
1. Yield: Package stacking modules to meet 99% yield for HVM certification
2. Capacity: Combined Philippine – China production to reach 3.2M units/month.
For target volume alone, worst-case solution was simply add two more stacking lines
on available Shanghai floor space; which would cost Intel US$4.8M. Avoidance of this
prohibitive cost has been my underlying goal.

CE 3.05 Our discussions zeroed in on the stacking module, its process equipment (loader, paste
print, stacking, reflow oven, PnP, unloader), the existing metal carrier, up to auditing
of module engineers’ and technicians’ conformance to methodologies. Among the
content experts that flew in were my US and Malaysia counterparts (designers of
incumbent metal carrier).

CE 3.06 I provided our FEA engineers detailed FS-CSP 3D models to simulate substrate denting
at 260°C reflow (then cannot be derived from either production DOEs or thermal lab
experiments due to existing equipment limitations) which gave valuable data to our
FMEAs on yield loss. The metal carrier was identified as top inducer of failures of
substrate denting (due to concentrated contact) and substrate popping out of pockets
(OOP) (both due singly or jointly to unwanted vertical e-spring action and substrate
warpage).

After successful 2nd corporate training at Intel’s Arizona and California campuses in
2003-04, I transitioned to my next mechanical engineering role to “own all metal
and plastic handling media designs for Low Density Interconnect (LDI)
products for Intel’s assembly operations for Asia (Philippines, China)”. Simply
put, I was the focal person for any modification or new design of all handling media
used in Intel’s Flash factories. This role was heavily rooted on, among others, both my
3D solid modeling (CE 1 highlight) and drawing creation (CE 2 highlight) capabilities.

Since a new metal carrier design was subsequently required for this project, my
support necessitated:
 Failure Mode and Effects Analyses (FMEA)
 Finite Element Analyses (FEA)
 Design of Experiments (DOEs)
 3D design conceptualization
 Design for Manufacturability (DFM)
 tolerance stack analyses
 Geometric Dimensioning and Tolerancing (GD&T - ASME Y14.5M-1994)
 sheet metal design
 metal fabrication (stamping, wire forming, machining, welding)
 2D Generic Mechanical (GM) drawing generation
 project and supplier management
 prototyping at supplier site



CAREER EPISODE 3

CE 3.09 Organizational matrix
Assembly Technology Development – Philippines (ATD-P) was Intel’s R&D group that
developed and certified semiconductor packaging technologies, methodologies and
materials for Flash business operations (Philippines and China). Face-to-fact (FtF) and
weekly online virtual factory (VF) meetings with US, China & Malaysia counterparts was
my way of life at Intel.

CE 3.10 Organizational structure chart1



CAREER EPISODE 3

One step ahead
Sensing a carrier densification project, I proactively requested our Industrial
Engineering (IE) team to determine minimum pocket count for Philippine-China
stacking operations to meet target output which they calculated at 26.64. I modeled a
28-pocket carrier per module engineers’ input that PnP capability was only 30/carrier.

CE 3.12 Proposals
Process engineers conceptualized a springless carrier (option 1). Intel Malaysia design
team proposed an adhesive-based carrier (option 2). In one TF meeting, I opined “e-
spring-type metal carrier is the successful status quo configuration for all of
Intel’s microprocessors and chipsets, which use rigid Bismaleimide Triazine
(BT)-cored substrates. Flexible substrate-based FS-CSP’s special handling
requirement was overlooked by designers of existing metal carrier”.

CE 3.13 I argued that spring action was not intrinsically the root cause of substrate denting &
OOP but the concentrated (line) e-spring-substrate contact. Pressure = Force/Area.
I then proposed my Next-Generation metal carrier concept (option 3) to eliminate all
shortcomings of existing carrier without major equipment upgrades required by other
two options. Key enablers were coil spring (for longevity and elimination of OOP-
inducing e-spring torque) and planar package contact ram ([a] minimizes contact
pressure to prevent substrate denting and [b] maintain perpendicular clamping despite
substrate warping).

CE 3.14 I then presented this matrix for risk assessment which fueled our technical
deliberations:
New Carrier Stack module equipment Technical Schedule
Option Originator
Configuration modification risk risk
Philippine process Springless MAJOR – additional
1 HIGH HIGH
engineers (126-pocket) machines to be developed
Malaysia design Resin-type MAJOR – additional
2 MEDIUM HIGH
team (28-pocket) machines to be developed

3 Planar contact MINIMAL – carrier actuator
Arnold Labares LOW LOW
(28-pocket) subassembly modification
Professional challenge aroused from both camps and I exercised objectivity on design
and analyses support since 3rd option was my brainchild. Data-driven concept
supremacy race began.

CE 3.15 Value ads
Intel Flash factories suffered 3/month carrier mortality mainly to e-spring damage. My
carrier concept was maintenance-free (housing component protects spring-ram
subassembly) with infinite life (coil spring stability after 1 million cycles outlives FS-
CSP roadmap).



CAREER EPISODE 3

CE 3.16 Proof of concept
I secured budget for makeshift planar contact carrier design of experiment (DOE) by:
(1) having a spare carrier machined to accommodate a contact ram, (2) designing a
ram and had several fabricated, (3) retrofitting rams on carrier with hi-temp tapes and
(4) running module tests. The result was exactly as I envisioned; zero substrate
denting and OOP. I then (5) documented everything and (6) presented to TF. This
convinced management to prioritize option 3 and issued my much-awaited
authorization to kick-off full-blown design.

CE 3.17 Battle plan
Management approved my lengthy carrier design Gantt charts which I strategized into:
Phase 1: 12-pocket (compatible with existing equipment) to meet 99% yield target
(12 weeks)
Phase 2: 28-pocket to meet 99% yield and 3.2M units/month output (8 weeks).
Common tasks were 3D conceptualization, auto-loader clamper design modification,
tol-stack analyses, drawings generation, design reviews, PR/PO, prototyping and
qualification.

CE 3.18 12-pocket prototype
I came to my elements day in day out doing Pro/E acrobatics with all cylinders firing;
3D modeling being my passion. Top and bottom plates I designed similar as possible to
incumbent’s. After modeling iterations  tolerance setting  design review cycles with
design counterparts, stakeholders and suppliers, I finalized these spring-ram
subassembly components to replace each e-spring: 6.1mm  at 6mm solid height coil
spring (2X), Dowell pins (2X) and M2 screw (2X), machined contact ram (2X) and lock
(2X), and sheet metal housing (1X) and spring divider (1X).

CE 3.19 For parts interaction, I employed Pro/E programming to automate modeling of relax,
open and clamping pocket configurations showing contact rams’ locations with
corresponding springs compressions. 3D models accentuated my TF update
presentations.

CE 3.20 We combed through checklists and corporate specs (Handling Media Process [C55539],
Carrier Design Rules [75-0037] & Carrier Procurement [07-765 R41]) on weekly design
reviews. GD&T technologist-level-trained myself, I finalized tolerance settings together
with corporate expert from Arizona through net meetings before I released final
drawing.

CE 3.21 Material selection
I specified SS304 for sheet metal components, SS301 for machined components and
SS17-7 PH for coil spring for rust-resistance and dimensional integrity at 260°C.

CE 3.22 Design flexibility
I was confident that clamping force would not be critical with planar contact. With no
factory characterization data on optimum FS-CSP clamping force, I designed to screw-
fasten the subassemblies to replace springs for DOEs at 3.23–10.73 Newtons at 1.25N
increments. Welding would replace screws on mass production version to reduce cost.



CAREER EPISODE 3

CE 3.23 Prototyping
Supplier looked forward to mass production to grow business with Intel. I only
proposed 5 prototypes (more would be unnecessary cost at over US$2K each) and
made a weeklong trip to supplier’s Singapore plant to oversee, among others, wire
forming and spring constants characterization in their lab. Intel’s metrology experts
joined in ensuring apple-to-apple setups between ours and supplier’s (contact and
vision) Computerized Measuring Machines (CMMs) for this mission-critical project.

CE 3.24 Milestone success
When prototypes were in house, qualification data revealed my carrier’s exceeding
99% yield target: 0.7% statistical loss on OOP and zero substrate denting. All trialed
springs also worked, proving my assessment right. White paper was approved and the
design was HVM-certified.

CE 3.25 28-pocket prototype
I integrated process engineers’ ergonomic feedbacks by: (1) using least material on
contact ram, (2) extending housing’s lap feature to replace the lock to alleviate carrier
weight increase (operators cart the carriers to and from module equipment) and (3)
adding 2mm external rounds to eliminate sharp corners.

CE 3.26 To optimize carrier ‘real estate’, supplier manufacturability inputs became valuable.
We (1) introduced housing part dovetails (‘male’ extends to adjacent housing’s
‘female’), (2) reduced screws from four to three and (3) designed a transfer jig to
clutch each subassembly prior to under-carrier fastening.

CE 3.27 With more pockets and subassemblies to support, I designed to weld machined bottom
ribbings to maintain 0.25mm bottom plate flatness. Banking on closer relationship with
supplier, I invited their application engineer bi-weekly to my office and fast-tracked
DFM to two weeks.

CE 3.28 Citations
I documented attributes, advantages and limitations of my brainchild design on
corporate specs. Intel carrier drawings have 4 sheets; mine had 11 for 12-pocket and
12 for 28-pocket design detailing spring-ram subassemblies and components (with
sheet metal housing flat views). GMMWG ratified my corporate specs additions and my
design was officially christened as Intel’s Next-Generation (NG) metal carrier.

CE 3.29 I filed four novel invention disclosures for this design development and authored
technical paper entries for Intel Assembly Technology Technical Journal (IATTJ ‘05) and
Intel Manufacturing Excellence Conference (IMEC ‘06).

CE 3.30 Business-driven aftermath
By August ’05, global FS-CSP demand plummeted, rendering Philippine-China Flash
operations over capacity. Intel further moved to spin-off Flash business and halted
corresponding R&D operations including development of 28-pocket NG metal carrier,



CAREER EPISODE 3

Intel’s secret weapon to ramp production to 3.2M units/month without major
equipment upgrades.

CE 3.31 Only the 12-pocket carrier was eventually implemented achieving yield target.
Nevertheless, it was a design win for my brainchild concept which brought closure of
FS-CSP stacking TF.

CE 3.32 D. SUMMARY
I’m the proud originator and developer of Intel’s most sophisticated (in component
count and mechanism) and most ‘product-gentle’ (minimal package contact pressure)
metal carrier which not only exceeded corporate 99% yield target but also raised the
bar of Intel’s carrier technology being the first of its class with infinite life and
maintenance-free properties.

CE 3.33 “Necessity is the mother of inventions” and my brainchild NG metal carrier epitomizes
a compelling design that became the key solution to an industrial challenge. This is my
highest-impact project for Intel and among my best mechanical design achievements
to date; boosting my self-confidence on my chosen profession.



SUMMARY STATEMENT OF COMPETENCY ELEMENTS

SUMMARY STATEMENT OF COMPETENCIES CLAIMED
Career
Competency
How and where demonstrated Episode
Element
reference
My Engineering Drawing skills landed me to this Astec job to build
CE 1.04
the part library.
My employment of part-and assembly-level relations on the 3D CE 2.12 &
modeling & GM drawing creation tasks. CE 2.15
I successfully executed a high-technical risk ‘skunk works’ project to
automatically pass down dimension parameters from a complete
CE 2.08
PE 1.1 Flash package 3D assembly to its parts with CAD programming skill
that I still had to learn from scratch.
I gave my confident professional opinion in a task force meeting on
CE 3.12
the merits and limitations of the existing metal carrier.
I argued that spring action was not intrinsically the root cause of
substrate denting & OOP but the concentrated (line) e-spring- CE 3.13
substrate contact. Pressure = Force/Area.
I identified the root causes of MCAD-ECAD libraries synchronization
CE 1.17 &
issue and proposed corrective actions which successfully eliminated
CE 1.18
the issue.
My highlighting the 3-day drawing creation throughput time
(TPT) to management as a process bottleneck that needed
CE 2.03
improvement given the numerous product lines in Intel’s Flash
business roadmap.
I applied CAD programming to successfully pass down dimension
parameters from a complete Flash package 3D assembly to its parts CE 2.08
and cut subsequent GM drawing generation TPT by 95%.
I diligently reviewed all applicable corporate governing specs to
PE 1.2
prevent any detail from being overlooked before I executed my CE 2.10
favorite ‘Pro/E acrobatics’ part of the project.
I selected appropriate materials for rust-resistance and dimensional
CE 3.21
integrity at 260°C.
CE 3.12
the merits and limitations of the existing metal carrier.
I argued that the concentrated (line) e-spring-substrate contact as
the root cause of substrate denting & OOP then proposed my coil-
spring-based planar package contact metal carrier concept to CE 3.13
eliminate all shortcomings of existing carrier without major
equipment upgrades required by other two options.
I learned and applied all relevant modeling tradecraft to build the CE 1.09 &
part library. CE 1.10
I employed relations, datum curves and part-level programming to
overcome the parametric hurdles of modeling the bottom metal CE 2.12
circuitry.
I systematically developed protrusion-cut feature pairs to satisfy the
continuity requirement of the alphanumeric identifiers of the top CE 2.13
PE 1.3 metal circuitry.
I employed assembly-level family table with all possible die size-
CE 2.14
orientation matrix to successfully verify model robustness.
I designed GM drawing creation on a Pro/INTRALINK session of
Pro/E to take advantage of INTRALINK’s batch renaming CE 2.15
functionality while maintaining critical files associativity.
I systematically employed all applicable modeling tradecraft to make
CE 2.16
my automation design intent work.




My drive to improve substrate drawing process by migrating drawing
CE 2.03
creation from non-parametric AutoCAD to parametric Pro/E.
I conceptualized the 28-pocket carrier solution with feasibility inputs
CE 3.11
from module and industrial engineering teams.
I designed the 12-pocket prototype with screw-fastened housing to
CE 3.22
easily replace coil springs for spring force characterization.
On parts interference, I employed Pro/E programming to automate
PE 1.3
modeling of relax, open and clamping pocket configurations showing CE 3.19
(cont’d)
contact rams’ locations with corresponding springs compressions.
I made a weeklong trip to supplier’s Singapore plant to oversee wire
forming, spring constants characterization and metrology in their CE 3.23
lab.
I did a DOE to simulate a makeshift carrier for my design concept;
result of which convinced management on the soundness of my CE 3.16
concept.
My Engineering Drawing skills enabled me to get a job amid an
industry and job market slump; testament to engineering profession CE 1.04
being an economic driver.
I proactively instigated to automate and proliferate substrate GM
drawing creation process corporate-wide to improve the productivity CE 2.04
of all Intel substrate design engineers.
Supplier looked forward to mass-produce my new metal carrier
PE 1.4 CE 3.23
concept to grow business with Intel.
I was eager to apply my engineering expertise to contribute to the
task force objectives and avoid the prohibitive US$4.8M equipment CE 3.04
upgrades cost for the worst-case solution.
Engineering developments support business needs. I was proud that
CE 3.30 &
my brainchild design concept became the key solution for this
CE 3.31
business challenge.
I kicked-off and co-headed the standardization project with the
ECAD team and came up with solutions that positively impacted the CE 1.18
design teams after implementation.
circuitry.
continuity requirement of the alphanumeric identifiers on the top CE 2.13
metal circuitry.
My GM drawing automation successfully reduced substrate design
PE 2.1 drawing TPT from initial 3 days to 1 hour at proliferation in our CE 2.20 &
parent R&D site or improved the productivity of Intel’s substrate CE 2.21
designers by factor of 8 to 24.
I argued that the concentrated (line) e-spring-substrate contact as
the root cause of substrate denting & OOP then proposed my coil-
spring-based planar package contact metal carrier concept to CE 3.13
eliminate all shortcomings of existing carrier without major
equipment upgrades required by other two options.
From my own (media design) end, I proactively conceptualized the
28-pocket metal carrier as a feasible solution path to the prevailing CE 3.11
factory issue.
My Engineering Drawing skills enabled me to get a job amid an
PE 2.2 industry and job market slump; testament to engineering profession CE 1.04
being an economic driver.




I targeted our parent organization in Chandler, Arizona for
CE 2.04 &
proliferation as it’s this site/org which has the authority for Go-no-
CE 2.20
Go on technical directions like CAD developments.
I did line tours and focus meetings with respective Flash factory end-
CE 2.11
user module engineers to prevent any detail from being overlooked.
Supplier looked forward to mass-produce my new metal carrier
CE 3.23
concept to grow business with Intel.
PE 2.2
I integrated process engineers’ ergonomic feedbacks to alleviate
(cont’d) CE 3.25
the 28-pocket carrier’s weight increase and eliminate sharp corners.
Face-to-fact (FtF) and weekly online virtual factory (VF) meetings CE 3.09
with US, China & Malaysia counterparts was my way of life at Intel. CE 3.10
CE 3.11
I summarized all design proposals in a matrix and presented to
CE 3.14
management for our collective risk assessment.
I proposed my project Gantt chart to my manager which approved
both my project timelines and ultimate end in mind of corporate- CE 2.09
wide proliferation.
I diligently reviewed all applicable corporate governing specs to
prevent any detail from being overlooked before I executed my CE 2.10
favorite ‘Pro/E acrobatics’ part.
I did line tours and focus meetings with respective Flash factory end-
CE 2.11
user module engineers to prevent any detail from being overlooked.
circuitry.
continuity requirement of the alphanumeric identifiers of the top CE 2.13
metal circuitry.
CE 2.14
I sought feedbacks for automation areas for improvement from (1)
CE 2.18 &
our local design technicians during pilot testing and (2) US
CE 2.20
counterparts during road show demonstration.
PE 2.3
I claimed my concept carrier to have “infinite life” as its coil springs
would maintain stability after 1 million cycles, outliving FS-CSP CE 3.15
roadmap it is designed to support.
I proposed my Next-Generation metal carrier concept with coil
spring (for longevity and elimination of OOP-inducing e-spring
torque) and planar package contact ram ([a] minimizes contact CE 3.13
pressure to prevent substrate denting and [b] maintain
perpendicular clamping despite substrate warping) as key enablers.
I was eager to apply my engineering expertise to contribute to the
task force objectives and avoid the prohibitive US$4.8M equipment CE 3.04
upgrades cost for the worst-case solution.
CE 3.14
from module and industrial engineering teams. CE 3.11

CE 3.25
I captured supplier’s manufacturability inputs to maximize carrier
CE 3.26
‘real estate’ and to design a transfer jig for ease of carrier assembly.




I came up with ECAD 3D PCB Assembly Methodology for the
CE 1.16
mechanical design engineers.
I came up with Standard Macros Configuration Proposal for Cadence
and Pro/E Libraries for the ECAD team to synchronize coordinate CE 1.18
system origin with my MCAD library.
I systematically employed all applicable modeling tradecraft to make
CE 2.16
my automation design intent work.
Prior to embarking on this complex SUBSRATE drawing automation,
I have already demonstrated my capability to implement its
automation driver to automatically pass down dimension parameters CE 2.08
from a complete assembly to its parts by successful execution of my
‘skunk works’ PACKAGE drawing automation project.
I detailed all pertinent data, guidelines, methodologies, user
capabilities and tools requirements in a document to enable all Intel
CE 2.17
substrate designers to execute the automation with emphasis on
novice Pro/E users.
I diligently combed through Pro/E manuals and sought PTC technical
support on Pro/PROGRAM to successfully pass down dimension CE 2.08
parameters from assembly to parts.
PE 2.4 CE 2.14
Management approved my lengthy design project proposal Gantt
CE 3.17
charts with detailed tasks.
CE 3.14
from module and industrial engineering teams. CE 3.11

CE 3.25
I captured supplier’s manufacturability inputs to maximize carrier
CE 3.26
‘real estate’ and to design a transfer jig for ease of carrier assembly.
I considered flexibility on my design to allow screw-fastening for the
prototype and welding for the mass production version to reduce CE 3.22
cost.
Carrier metrology entailed contact- and vision-system CMMs to
validate both basic and critical to function dimensions per corporate CE 3.23
procurement spec.
from module and industrial engineering teams to meet the CE 3.11
32M/month output.
As the MCAD library originator, I kicked off and co-headed the CAD
libraries standardization project with the ECAD team and came up CE 1.17 &
with proposal that positively impacted the design teams after CE 1.18
implementation.
I proposed my project Gantt chart to my manager which approved
PE 2.5 both my project timelines and ultimate end in mind of corporate- CE 2.09
wide proliferation.
I detailed all pertinent data, guidelines, methodologies, user
CE 2.17
novice Pro/E users.




I did a DOE to simulate a makeshift carrier for my design concept;
result of which convinced management on the soundness of my CE 3.16
concept.
PE 2.5
(cont’d) CE 3.17
I filed four novel invention disclosures and two technical papers for
CE 3.29
my design development.
My buying in and commitment to execute Astec’s part library project
CE 1.04
as part of its mechanical design process improvement scheme.
My understanding and appreciation of business need to regularize
CE 1.15
my employment given my sought-after MCAD skills.
I targeted our parent organization in Chandler, Arizona for
CE 2.04 &
proliferation as it’s this site/org which has the authority for Go-no-
CE 2.20
Go on technical directions like CAD developments.
I executed this “zero budget” project per task and timeline of my
CE 2.09
Gantt chart.
I was motivated to positively impact Intel’s Flash business
CE 2.03
substrates outsourcing process by CAD automation.
PE 2.6 I was in my elements with my support interdependency matrix
CE 3.10
during my third career episode.
CE 3.17
Avoidance of US$4.8M cost prohibitive cost has been my underlying
CE 3.04
goal in formulating my design concept.
I only proposed 5 prototypes as more would be unnecessary cost at
CE 3.23
over US$2K each.
Given potential business impact of yield and volume issues, Intel
business process called for kicking off of combined engineering-
CE 3.04
management Task Force (TF) to come up with realistic solution paths
with measurable results.
I clearly conveyed the details of libraries synchronization issue which
CE 1.18
prompted management to execute a standardization project.
I accomplished the final road show demonstration task for
CE 2.20
corporate proliferation.
CE 2.18 &
CE 2.20
CE 3.14
My detailed documentation of my DOE and clear results presentation
PE 3.1
to task force convinced management to prioritize proposal 3 and CE 3.16
issued my much-awaited authorization to kick-off full-blown design.
3D models accentuated my TF update presentations. CE 3.19
I combed through checklists and corporate specs on weekly design
CE 3.20
reviews with stakeholders.
I articulated my professional opinion in a task force meeting on the
CE 3.12
merits and limitations of the existing metal carrier.
I argued that spring action was not intrinsically the root cause of
substrate contact. Pressure = Force/Area.
I employed appropriate internal and external manuals, specs and CE 1.12 &
PE 3.2
standards as guide materials to correctly execute my project. CE 1.13




CE 1.08
My panache on MS PowerPoint to convey organization charts. CE 2.06
CE 3.10
My panache on MS Word to create well-formatted documentations. whole CDR
I came up with ECAD 3D PCB Assembly Methodology for the
CE 1.16
mechanical design engineers.
I came up with Standard Macros Configuration Proposal for Cadence
and Pro/E Libraries for the ECAD team to synchronize coordinate CE 1.18
system origin with my MCAD library.
I did a comprehensive review of applicable corporate governing
CE 2.10
specs to prevent any detail from being overlooked.
My dexterity on MS Project to come up with working Gantt to seek
CE 2.09
my manager’s approval for my project proposal.
PE 3.2
(cont’d) I detailed all pertinent data, guidelines, methodologies, user
CE 2.17
novice Pro/E users.
Intel carrier drawings have 4 sheets; mine had 11 for 12-pocket and
12 for 28-pocket design detailing spring-ram subassemblies and CE 3.28
components (with sheet metal housing flat views).
My detailed documentation of my DOE and clear results presentation
to task force convinced management to prioritize proposal 3 and CE 3.16
issued my much-awaited authorization to kick-off full-blown design.
I documented attributes, advantages and limitations of my brainchild
CE 3.28
design on existing corporate specs which the GMMWG ratified.
We combed through checklists and corporate specs on weekly design
CE 3.20
reviews.
I identified the root and underlying causes of CAD libraries
synchronization issues and proposed a “bitter pill” modification on CE 1.17 &
the established ECAD library that eliminated occurrence of mis- CE 1.18
orientation in downstream mechanical design processes.
I highlighted the 3-day substrate drawing creation time to
CE 2.03 &
management as a process bottleneck and instigated a Continuous
CE 2.04
Improvement Process (CIP) using CAD automation.
I applied CAD programming on Flash packages GM design drawings
creation after learning of this efficient technique being used on other CE 2.08
design applications by my US counterpart teams.
PE 3.3 the merits and limitations of the existing metal carrier and further,
argued that spring action was not intrinsically the root cause of CE 3.12 &
substrate contact and proposed my Next-Generation metal carrier
concept to eliminate all shortcomings of existing carrier.
I creatively designed an inexpensive makeshift contact ram that I
resourcefully fastened on the machined carrier with hi-temp tapes on CE 3.16
my DOE for my proof of concept.
Our discussions zeroed in on the stacking module, its process
equipment (loader, paste print, stacking, reflow oven, PnP,
CE 3.05
unloader), the existing metal carrier, up to auditing of module
engineers’ and technicians’ conformance to methodologies.




I provided our FEA guys detailed FS-CSP 3D models to simulate
substrate denting at 260°C reflow (then cannot be derived from
either production DOEs or thermal lab experiments due to existing CE 3.06
equipment limitations) which gave valuable data to our FMEAs on
yield loss.
CE 3.11
PE 3.3
(cont’d) CE 3.20
reviews.
GD&T technologist-level-trained myself, I finalized tolerance settings
together with corporate expert from Arizona through net meetings CE 3.20
before I released final drawing.
I easily welcomed Intel’s cancellation of 28-pocket variant of my NG
CE 3.30 &
metal carrier development knowing that my HVM-certified 12-pocket
CE 3.31
original design would make it to implementation.
CE 1.01
PE 3.4 My commitment to company intellectual property policy. CE 2.01
CE 3.01
On top of routine part library additions and maintenance, I
demonstrated my Pro/E panache by mentoring design engineers on
CE 1.19
PCB assemblies creation and coaching them on part- and assembly-
modeling as the software versions advanced.
I mentored both local and US colleagues at pilot testing & road
CE 2.18 &
show demonstration respectively for them to replicate and reap
CE 2.20
the advantages of my automation project.
Professional challenge aroused from originators of other proposals
and I exercised objectivity on design and analyses support since CE 3.14
competing proposal was my brainchild.
CE 3.14
PE 3.5 CE 3.20
reviews.
Banking on closer relationship with supplier, I invited their
application engineer bi-weekly to my office and fast-tracked DFM to CE 3.27
two weeks.
As Intel Philippines’ Pro/E super user and Pro/INTRALINK
CE 3.10
administrator, I was the focal person for all MCAD support and
(note 2)
enquiries from different departments.
I was an active attendee to the bimonthly net meetings of our global
CE 3.10
Mechanical/Thermal Tools Standards Committee to share CAD best
(note 3)
known methods (BKMs), among others.
GD&T technologist-level-trained myself, I finalized tolerance settings
together with corporate expert from Arizona through net meetings CE 3.20
before I released final drawing.
I sought guidance both from my technical superior and on the
CE 1.12
software user manuals to constantly develop my modeling skills.
Having had no training on crucial CAD programming skill for this
project, I diligently combed through Pro/E manuals and sought PTC
CE 2.08
PE 3.6 technical support on Pro/PROGRAM to successfully pass down
dimension parameters from assembly to parts.
CE 2.18 &
CE 2.20


Arnold Labares Engineers Australia CDR

Arnold Labares Engineers Australia CDR

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Arnold Labares Engineers Australia CDR