This document contains a set of questions related to computer science topics like automata theory, programming languages, computer architecture, operating systems, and algorithms. There are 38 multiple choice questions testing knowledge of topics such as regular expressions, finite automata, Turing machines, context-free grammars, complexity classes, computer hardware components, paging, virtual memory, file systems, and page replacement algorithms. The questions range from basic definitions to analyzing algorithms and data structures.
final Year Projects, Final Year Projects in Chennai, Software Projects, Embedded Projects, Microcontrollers Projects, DSP Projects, VLSI Projects, Matlab Projects, Java Projects, .NET Projects, IEEE Projects, IEEE 2009 Projects, IEEE 2009 Projects, Software, IEEE 2009 Projects, Embedded, Software IEEE 2009 Projects, Embedded IEEE 2009 Projects, Final Year Project Titles, Final Year Project Reports, Final Year Project Review, Robotics Projects, Mechanical Projects, Electrical Projects, Power Electronics Projects, Power System Projects, Model Projects, Java Projects, J2EE Projects, Engineering Projects, Student Projects, Engineering College Projects, MCA Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, Wireless Networks Projects, Network Security Projects, Networking Projects, final year projects, ieee projects, student projects, college projects, ieee projects in chennai, java projects, software ieee projects, embedded ieee projects, "ieee2009projects", "final year projects", "ieee projects", "Engineering Projects", "Final Year Projects in Chennai", "Final year Projects at Chennai", Java Projects, ASP.NET Projects, VB.NET Projects, C# Projects, Visual C++ Projects, Matlab Projects, NS2 Projects, C Projects, Microcontroller Projects, ATMEL Projects, PIC Projects, ARM Projects, DSP Projects, VLSI Projects, FPGA Projects, CPLD Projects, Power Electronics Projects, Electrical Projects, Robotics Projects, Solor Projects, MEMS Projects, J2EE Projects, J2ME Projects, AJAX Projects, Structs Projects, EJB Projects, Real Time Projects, Live Projects, Student Projects, Engineering Projects, MCA Projects, MBA Projects, College Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, M.Sc Projects, Final Year Java Projects, Final Year ASP.NET Projects, Final Year VB.NET Projects, Final Year C# Projects, Final Year Visual C++ Projects, Final Year Matlab Projects, Final Year NS2 Projects, Final Year C Projects, Final Year Microcontroller Projects, Final Year ATMEL Projects, Final Year PIC Projects, Final Year ARM Projects, Final Year DSP Projects, Final Year VLSI Projects, Final Year FPGA Projects, Final Year CPLD Projects, Final Year Power Electronics Projects, Final Year Electrical Projects, Final Year Robotics Projects, Final Year Solor Projects, Final Year MEMS Projects, Final Year J2EE Projects, Final Year J2ME Projects, Final Year AJAX Projects, Final Year Structs Projects, Final Year EJB Projects, Final Year Real Time Projects, Final Year Live Projects, Final Year Student Projects, Final Year Engineering Projects, Final Year MCA Projects, Final Year MBA Projects, Final Year College Projects, Final Year BE Projects, Final Year BTech Projects, Final Year ME Projects, Final Year MTech Projects, Final Year M.Sc Projects, IEEE Java Projects, ASP.NET Projects, VB.NET Projects, C# Projects, Visual C++ Projects, Matlab Projects, NS2 Projects, C Projects, Microcontroller Projects, ATMEL Projects, PIC Projects, ARM Projects, DSP Projects, VLSI Projects, FPGA Projects, CPLD Projects, Power Electronics Projects, Electrical Projects, Robotics Projects, Solor Projects, MEMS Projects, J2EE Projects, J2ME Projects, AJAX Projects, Structs Projects, EJB Projects, Real Time Projects, Live Projects, Student Projects, Engineering Projects, MCA Projects, MBA Projects, College Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, M.Sc Projects, IEEE 2009 Java Projects, IEEE 2009 ASP.NET Projects, IEEE 2009 VB.NET Projects, IEEE 2009 C# Projects, IEEE 2009 Visual C++ Projects, IEEE 2009 Matlab Projects, IEEE 2009 NS2 Projects, IEEE 2009 C Projects, IEEE 2009 Microcontroller Projects, IEEE 2009 ATMEL Projects, IEEE 2009 PIC Projects, IEEE 2009 ARM Projects, IEEE 2009 DSP Projects, IEEE 2009 VLSI Projects, IEEE 2009 FPGA Projects, IEEE 2009 CPLD Projects, IEEE 2009 Power Electronics Projects, IEEE 2009 Electrical Projects, IEEE 2009 Robotics Projects, IEEE 2009 Solor Projects, IEEE 2009 MEMS Projects, IEEE 2009 J2EE P
This document is a 3 page exam for a course on TCP/IP programming. It contains 7 questions testing knowledge of IP addressing classes, TCP connection termination, writing client-server programs in C, Unix commands, ARP, differentiating network concepts, FTP protocol attributes, IP and TCP header fields, socket descriptors, and the purpose of the MIME protocol. Students are required to answer question 1 and any 3 other questions.
This document contains 3 sample exam papers for the subject Microprocessor and Programming. The papers include questions to test students' knowledge of 8085 and 8086 microprocessors, assembly language programming concepts, and instructions. Some example questions are on addressing modes, flags, registers, memory segmentation, minimum and maximum modes, and assembly directives. The papers provide a mix of short answer, explanation, code writing and diagram questions to evaluate students' understanding of the microprocessor fundamentals and ability to program in assembly language.
The document discusses the architecture and assembly language programming of PIC18 microcontrollers. It covers topics such as:
- PIC18 microcontrollers use a Harvard architecture with separate memory for instructions and data. They have a program memory, data memory, I/O ports, and support devices like timers.
- The PIC18 architecture is based on an advanced RISC design. Key components include registers like WREG for temporary data storage. Special function registers and general purpose registers are used to access I/O ports and timers.
- Assembly language instructions like MOVLW, ADDLW, and MOVWF are used to move data between program memory, registers and I/O ports. The
This document contains the contents and program descriptions for various programs to be completed as part of a Microprocessor Lab course. There are 23 interfacing programs and 20 8085 microprocessor programs described, including programs to transfer data blocks with and without overlap, add/multiply/divide numbers, implement counters, check codes, and interface with keyboards, displays, and other peripherals.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document describes overhead bytes in the Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) protocols. It explains that certain bytes, such as J0 and B1, are used for regenerator section trace and byte interleaved parity to ensure connection integrity and identify individual signals after multiplexing. Other bytes, like D1-D3 and E1, are used for embedded operations channels and orderwires. The document also describes pointer bytes H1-H3 that indicate the offset of the synchronous payload envelope and compensate for timing variations, and Maintenance overhead bytes like B2, K1-K2, and S1 that provide automatic protection switching, additional data communications, and
This document provides an overview of microcontroller architecture and assembly language programming. It discusses the following key points in 3 sentences:
The document introduces PIC microcontrollers and assembly language, noting that assembly language uses mnemonic instructions that must be translated to machine code by an assembler. It explains the assembling and linking process used to convert assembly code to machine code that can be burned into the PIC's program memory. Various PIC assembly language instructions are also described, including MOVLW, MOVWF, logic instructions, and bit manipulation instructions to set and clear bits on I/O ports.
final Year Projects, Final Year Projects in Chennai, Software Projects, Embedded Projects, Microcontrollers Projects, DSP Projects, VLSI Projects, Matlab Projects, Java Projects, .NET Projects, IEEE Projects, IEEE 2009 Projects, IEEE 2009 Projects, Software, IEEE 2009 Projects, Embedded, Software IEEE 2009 Projects, Embedded IEEE 2009 Projects, Final Year Project Titles, Final Year Project Reports, Final Year Project Review, Robotics Projects, Mechanical Projects, Electrical Projects, Power Electronics Projects, Power System Projects, Model Projects, Java Projects, J2EE Projects, Engineering Projects, Student Projects, Engineering College Projects, MCA Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, Wireless Networks Projects, Network Security Projects, Networking Projects, final year projects, ieee projects, student projects, college projects, ieee projects in chennai, java projects, software ieee projects, embedded ieee projects, "ieee2009projects", "final year projects", "ieee projects", "Engineering Projects", "Final Year Projects in Chennai", "Final year Projects at Chennai", Java Projects, ASP.NET Projects, VB.NET Projects, C# Projects, Visual C++ Projects, Matlab Projects, NS2 Projects, C Projects, Microcontroller Projects, ATMEL Projects, PIC Projects, ARM Projects, DSP Projects, VLSI Projects, FPGA Projects, CPLD Projects, Power Electronics Projects, Electrical Projects, Robotics Projects, Solor Projects, MEMS Projects, J2EE Projects, J2ME Projects, AJAX Projects, Structs Projects, EJB Projects, Real Time Projects, Live Projects, Student Projects, Engineering Projects, MCA Projects, MBA Projects, College Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, M.Sc Projects, Final Year Java Projects, Final Year ASP.NET Projects, Final Year VB.NET Projects, Final Year C# Projects, Final Year Visual C++ Projects, Final Year Matlab Projects, Final Year NS2 Projects, Final Year C Projects, Final Year Microcontroller Projects, Final Year ATMEL Projects, Final Year PIC Projects, Final Year ARM Projects, Final Year DSP Projects, Final Year VLSI Projects, Final Year FPGA Projects, Final Year CPLD Projects, Final Year Power Electronics Projects, Final Year Electrical Projects, Final Year Robotics Projects, Final Year Solor Projects, Final Year MEMS Projects, Final Year J2EE Projects, Final Year J2ME Projects, Final Year AJAX Projects, Final Year Structs Projects, Final Year EJB Projects, Final Year Real Time Projects, Final Year Live Projects, Final Year Student Projects, Final Year Engineering Projects, Final Year MCA Projects, Final Year MBA Projects, Final Year College Projects, Final Year BE Projects, Final Year BTech Projects, Final Year ME Projects, Final Year MTech Projects, Final Year M.Sc Projects, IEEE Java Projects, ASP.NET Projects, VB.NET Projects, C# Projects, Visual C++ Projects, Matlab Projects, NS2 Projects, C Projects, Microcontroller Projects, ATMEL Projects, PIC Projects, ARM Projects, DSP Projects, VLSI Projects, FPGA Projects, CPLD Projects, Power Electronics Projects, Electrical Projects, Robotics Projects, Solor Projects, MEMS Projects, J2EE Projects, J2ME Projects, AJAX Projects, Structs Projects, EJB Projects, Real Time Projects, Live Projects, Student Projects, Engineering Projects, MCA Projects, MBA Projects, College Projects, BE Projects, BTech Projects, ME Projects, MTech Projects, M.Sc Projects, IEEE 2009 Java Projects, IEEE 2009 ASP.NET Projects, IEEE 2009 VB.NET Projects, IEEE 2009 C# Projects, IEEE 2009 Visual C++ Projects, IEEE 2009 Matlab Projects, IEEE 2009 NS2 Projects, IEEE 2009 C Projects, IEEE 2009 Microcontroller Projects, IEEE 2009 ATMEL Projects, IEEE 2009 PIC Projects, IEEE 2009 ARM Projects, IEEE 2009 DSP Projects, IEEE 2009 VLSI Projects, IEEE 2009 FPGA Projects, IEEE 2009 CPLD Projects, IEEE 2009 Power Electronics Projects, IEEE 2009 Electrical Projects, IEEE 2009 Robotics Projects, IEEE 2009 Solor Projects, IEEE 2009 MEMS Projects, IEEE 2009 J2EE P
This document is a 3 page exam for a course on TCP/IP programming. It contains 7 questions testing knowledge of IP addressing classes, TCP connection termination, writing client-server programs in C, Unix commands, ARP, differentiating network concepts, FTP protocol attributes, IP and TCP header fields, socket descriptors, and the purpose of the MIME protocol. Students are required to answer question 1 and any 3 other questions.
This document contains 3 sample exam papers for the subject Microprocessor and Programming. The papers include questions to test students' knowledge of 8085 and 8086 microprocessors, assembly language programming concepts, and instructions. Some example questions are on addressing modes, flags, registers, memory segmentation, minimum and maximum modes, and assembly directives. The papers provide a mix of short answer, explanation, code writing and diagram questions to evaluate students' understanding of the microprocessor fundamentals and ability to program in assembly language.
The document discusses the architecture and assembly language programming of PIC18 microcontrollers. It covers topics such as:
- PIC18 microcontrollers use a Harvard architecture with separate memory for instructions and data. They have a program memory, data memory, I/O ports, and support devices like timers.
- The PIC18 architecture is based on an advanced RISC design. Key components include registers like WREG for temporary data storage. Special function registers and general purpose registers are used to access I/O ports and timers.
- Assembly language instructions like MOVLW, ADDLW, and MOVWF are used to move data between program memory, registers and I/O ports. The
This document contains the contents and program descriptions for various programs to be completed as part of a Microprocessor Lab course. There are 23 interfacing programs and 20 8085 microprocessor programs described, including programs to transfer data blocks with and without overlap, add/multiply/divide numbers, implement counters, check codes, and interface with keyboards, displays, and other peripherals.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document describes overhead bytes in the Synchronous Optical Networking (SONET) and Synchronous Digital Hierarchy (SDH) protocols. It explains that certain bytes, such as J0 and B1, are used for regenerator section trace and byte interleaved parity to ensure connection integrity and identify individual signals after multiplexing. Other bytes, like D1-D3 and E1, are used for embedded operations channels and orderwires. The document also describes pointer bytes H1-H3 that indicate the offset of the synchronous payload envelope and compensate for timing variations, and Maintenance overhead bytes like B2, K1-K2, and S1 that provide automatic protection switching, additional data communications, and
This document provides an overview of microcontroller architecture and assembly language programming. It discusses the following key points in 3 sentences:
The document introduces PIC microcontrollers and assembly language, noting that assembly language uses mnemonic instructions that must be translated to machine code by an assembler. It explains the assembling and linking process used to convert assembly code to machine code that can be burned into the PIC's program memory. Various PIC assembly language instructions are also described, including MOVLW, MOVWF, logic instructions, and bit manipulation instructions to set and clear bits on I/O ports.
eBPF has 64-bit general purpose registers, therefore 32-bit architectures normally need to use register pair to model them and need to generate extra instructions to manipulate the high 32-bit in the pair. Some of these overheads incurred could be eliminated if JIT compiler knows only the low 32-bit of a register is interested. This could be known through data flow (DF) analysis techniques. Either the classic iterative DF analysis or "path-sensitive" version based on verifier's code path walker.
In this talk, implementations for both versions of DF analyzer will be presented. We will see how a def-use chain based classic eBPF DF analyser looks first, and will see the possibility to integrate it with previous proposed eBPF control flow graph framework to make a stand-alone eBPF global DF analyser which could potentially serve as a library. Then, another "path-sensitive" DF analyser based on the existing verifier code path walker will be presented. We will discuss how function calls, path prune, path switch affect the implementation. Finally, we will summarize pros and cons for each, and will see how could each of them be adapted to 64-bit and 32-bit architecture back-ends.
Also, eBPF has 32-bit sub-register and ALU32 instructions associated, enable them (-mattr=+alu32) in LLVM code-gen could let the generated eBPF sequences carry more 32-bit information which could potentially easy flow analyser. This will be briefly discussed in the talk as well.
Lec6 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Instruction...Hsien-Hsin Sean Lee, Ph.D.
This document discusses techniques for improving instruction fetch throughput in superscalar processors. It begins by explaining that fetch throughput defines the maximum performance and that superscalar processors need to supply more than one instruction per cycle. It then describes some challenges to high bandwidth instruction fetching including misaligned instructions, changes in control flow, and memory latency/bandwidth limitations. The document proceeds to discuss specific techniques like aligned fetching, split cache line access, predication, collapsing buffers, trace caches, and issues related to indexing and redundancy in trace caches.
This document contains questions for a mid-term exam on various topics related to soft computing.
The questions are divided into three sections:
Section A contains 4 multiple choice questions related to fuzzy set theory and operations. Section B contains 3 short answer questions on fuzzy sets, membership functions, and fuzzification.
Section C contains 2 longer theoretical questions, one involving sketching membership functions and defining 1-cut sets, and another involving fuzzy relations composition and cut sets.
The document provides guidance on answering questions from each section and notes that parts of questions should be answered together and diagrams can be used when needed. It also mentions that missing data can be assumed with justification.
This document discusses various arithmetic and logical instructions in 8051 microcontroller including ADD, SUBB, MUL, DIV, INC, DEC, DA, flags, logical operations, rotate instructions, swap instruction, and comparison operations. It provides examples to explain the working of instructions and how they affect the flag registers. It also summarizes the topics discussed in the lecture on arithmetic and logical operations in 8051 microcontroller.
The document describes an implementation of an LDPC decoder for IEEE 802.11n wireless networks using Vivado High-Level Synthesis. It implemented the decoder as a C program using Vivado HLS directives to optimize parallelism and throughput. The implementation achieved throughputs of over 1 Gbps and error correction performance comparable to an RTL implementation but with higher productivity due to the higher level of abstraction of C compared to RTL.
This document discusses turbo codes, which are a type of error correction code built by parallel concatenating two convolutional code blocks. It focuses on investigating the iterative decoding of turbo codes. The bit error rate is calculated over multiple iterations of decoding and plotted against signal to noise ratio. Quadratic permutation polynomial and random interleavers are analyzed. Results show turbo codes with a memory of 3 and 1280 bit interleaver achieve the best performance, reaching a bit error rate of 10-5 at -1.2 dB after 10 iterations of decoding.
This document provides an overview of the x86 microprocessor architecture. It discusses the history of x86 processors from the 8086 to modern Pentium and Intel 64-bit processors. It then describes the internal structure of the 8088/8086, including the bus interface unit, execution unit, registers, and flag register. It introduces assembly language programming and common instructions like MOV and ADD. It explains the code, data, stack, and extra segments and how logical addresses map to physical addresses. Memory allocation in IBM PCs is also summarized.
Microprocessor and Microcontroller Lab Manual!PRABHAHARAN429
The document describes experiments to be performed on an 8-bit microprocessor and microcontroller. It includes aims, block diagrams, flowcharts and assembly language programs for arithmetic operations, sorting an array, and interfacing experiments. Experiments cover topics like addition, subtraction, multiplication, division, ascending/descending order, maximum/minimum values, and interfacing components like ADCs, DACs, stepper motors. Similar experiments are outlined for an 8-bit microcontroller.
This document contains question banks for the subject VLSI Design (IV/I) covering 6 units:
1. MOS transistor fabrication and operation
2. Layout design rules and techniques
3. Scaling, delays, and logic implementation
4. Sequential circuits and subsystem design
5. Testing strategies and standard cell design
6. VHDL modeling and simulation
It provides over 150 questions ranging from conceptual explanations to circuit implementations to test verification strategies to assess student understanding of VLSI design principles and practices.
Static scheduling machines like VLIW move instruction scheduling from hardware to compiler by packing multiple operations into single instructions. This simplifies hardware but requires compilers to explicitly represent dependencies. The Intel Itanium ISA follows the VLIW philosophy, using instruction bundles containing up to 3 operations. Itanium 2 improved on the original design with an 8-stage pipeline and register renaming to boost performance. Itanium supports both control and data speculation via techniques like speculative loads and the Advanced Load Address Table.
This document introduces TensorFlow Lite for Microcontrollers (TF Micro) which brings machine learning to microcontroller applications. It discusses porting TF Micro to platforms like Arduino, converting TensorFlow models to a C array format compatible with MCUs, and using the TF Micro C++ API and interpreter to perform inference on embedded devices with limited memory and compute. Examples are provided of applying TF Micro to applications like speech recognition on microcontrollers.
The document summarizes the branch group instructions of the 8085 microprocessor. It describes jump instructions like JMP, conditional jump instructions, and the PCHL instruction. It also covers CALL and return instructions like CALL, RET, and conditional call and return instructions. Finally, it discusses restart instructions like RST that can be used as software interrupts to transfer program execution to specific restart locations.
1) A half-adder and full-adder are used to perform binary addition. A half-adder has two inputs and two outputs while a full-adder has three inputs and two outputs. Full-adders can be combined into a parallel adder to add binary numbers with multiple bits.
2) Comparators compare the magnitudes of two binary numbers and output signals to indicate if the numbers are equal, if the first is larger, or if the second is larger. Decoders detect a specific binary input code and output a signal. Common decoder uses include binary-to-decimal conversion and driving seven segment displays.
3) Integrated circuits like the 74LS47 BCD-to-seven segment decoder/driver
This document describes the architecture of the SAP-2 microprocessor. It has 16-bit address and data buses that can address 64K of memory space. The memory space includes 2K of ROM from addresses 0000H to 07FFH and 62K of RAM from 0800H to FFFFH. It has 8-bit registers including the accumulator, instruction register, flags, and temporary, B, and C registers. It supports common instructions like LDA, STA, MVI, ADD, SUB, logical operations, jumps, calls, inputs, outputs and rotations. The controller sequencer generates microinstructions to control the execution of up to 256 instructions, of which only 42 are implemented.
The document describes the Simple-As-Possible (SAP-1) computer. SAP-1 is a simple 8-bit computer designed to introduce fundamental computer concepts. It has 16 bytes of memory, 5 instructions, and components like an accumulator, registers, and an adder/subtractor connected via an 8-bit bus. The document explains the operation of each component and how they work together to execute instructions like load, add, subtract, output and halt.
This document contains model question papers for the 6th semester BE (CBCS) EC/TC course Digital Communication (15EC61). It includes 10 sample questions divided into 5 modules. Each question has 3 parts with marks allocated for each part. The questions test various topics related to digital communication systems including Hilbert transforms, line codes, orthogonal signals, probability of error, modulation techniques like PSK, QAM, FSK and demodulation. It also includes questions on channel equalization, spread spectrum, channel coding and error control coding.
8085 stack & machine control instructionprashant1271
The document describes the stack and machine control group of instructions for the 8085 microprocessor. It includes instructions for pushing/popping registers onto/from the stack, loading the stack pointer, exchanging registers with the stack pointer, no operation, halting the processor, enabling/disabling interrupts, and setting/reading the interrupt mask. Examples are provided for each instruction.
The document contains chapters from a digital fundamentals textbook covering topics such as combinational logic circuits, Karnaugh maps, universal gates, and pulsed waveforms. It provides examples of implementing sum-of-products expressions using AND-OR gates, converting circuits to NAND or NOR form, reading logic expressions from Karnaugh maps, and analyzing the output of combinational circuits with pulsed inputs. It also contains several practice problems with answers.
IFSM 310 Software and Hardware Infrastructure ConceptsComputer.docxscuttsginette
IFSM 310 Software and Hardware Infrastructure Concepts
Computer and Number Systems
1.
(10 pt)
You have been hired to develop a website-based sales system for a large international retail firm. List and describe at least four features that are specific to the Web design of your system and customer service important to consider if your system is to be successful at attracting and keeping customers living outside of the US. Include not only characteristics of the user interface, but those issues that must be uniquely addressed to successfully service your non-US customers.
2.
(2.5 pt each)
In order to receive credit for these problems, you must show all of the steps you took to arrive at your answers.
(c) Convert the following decimal number to binary:
21842
(d) Convert the following binary number to decimal:
11000111011.101
(c) Convert the following hexadecimal number to decimal:
CA97
(d) Convert the following binary number to hexadecimal:
1110011111011010100
CPU and Memory
3.
(10 pt)
ASCII, Unicode, and EBCDIC are, of course, not the only numeric / character codes. The Sophomites from the planet Collegium use the rather strange code shown in the Figure below. There are only thirteen characters in the Sophomite alphabet, and each character uses a 5-bit code. In addition, there are four numeric digits, since the Sophomites use base 4 for their arithmetic. Given the following Sophomite sequence, what is the corresponding binary message being sent by the Sophomites?
(HINT: Decode the sequence reading from left to right then write the corresponding binary sequence, leaving a space between each binary sequence.)
4.
(10 pt)
Define memory cache write-through and write-back techniques and describe the advantages and disadvantages of each.
Input / Output
5. Answer the follow questions about interrupts.
a.
(5 pt)
Describe in detail the steps that occur when a system receives an interrupt.
b.
(5 pt)
Describe how these steps differ in the case when a system receives multiple interrupts
Computer Systems
6. Answer the following questions about clusters.
a.
(5 pt)
Describe how you might use a cluster to provide fault-tolerant computing
b.
(5 pt)
Describe how you might use a cluster architecture to provide rapid scalability for a Web-based company experiencing rapid growth.
Networks
7. Answer the following questions about communication protocols.
a.
(5 pt)
Using the operations of UDP (User Datagram Protocol) and TCP (Transmission Control Protocol) as a basis, carefully explain the difference between connectionless and connection-oriented communication.
b.
(5 pt)
If you were ordering a number of items from an online seller, such as amazon.com, which Protocol (TCP or UDP) would you recommend and explain why
.
8. In the context of network security,
a.
(3 pt)
exp.
This exam includes multiple choice and "mark all that apply" questions worth a total of 100 points. There are also two essay questions for extra credit. Students have three hours to complete the closed-book exam. They must put away all books, notes, and electronic devices. The proctor cannot answer questions during the exam.
This document contains the questions and answers for an ECET 330 final exam. It includes 10 multiple choice questions covering topics like dynamic memory, von Neumann architecture, assembly language instructions, and bit manipulation. It also includes 5 programming questions involving manipulating values in memory locations and registers using assembly language and C on an HCS12 microcontroller. The document encourages purchasing access to exam solutions and course materials from an online test preparation website.
This document contains the questions and answers for an ECET 330 final exam. It includes 10 multiple choice questions covering topics like dynamic memory, von Neumann architecture, CodeWarrior assembler, HCS12 instruction set, BCD conversion, and creating pulse waves. It also includes 5 questions asking to write code sequences or programs to perform tasks like adding values from two memory locations, counting even/odd numbers in an array, and repeatedly writing values to locations with delays. The document provides a way to purchase access to solutions for exams, courses, and homework assignments.
eBPF has 64-bit general purpose registers, therefore 32-bit architectures normally need to use register pair to model them and need to generate extra instructions to manipulate the high 32-bit in the pair. Some of these overheads incurred could be eliminated if JIT compiler knows only the low 32-bit of a register is interested. This could be known through data flow (DF) analysis techniques. Either the classic iterative DF analysis or "path-sensitive" version based on verifier's code path walker.
In this talk, implementations for both versions of DF analyzer will be presented. We will see how a def-use chain based classic eBPF DF analyser looks first, and will see the possibility to integrate it with previous proposed eBPF control flow graph framework to make a stand-alone eBPF global DF analyser which could potentially serve as a library. Then, another "path-sensitive" DF analyser based on the existing verifier code path walker will be presented. We will discuss how function calls, path prune, path switch affect the implementation. Finally, we will summarize pros and cons for each, and will see how could each of them be adapted to 64-bit and 32-bit architecture back-ends.
Also, eBPF has 32-bit sub-register and ALU32 instructions associated, enable them (-mattr=+alu32) in LLVM code-gen could let the generated eBPF sequences carry more 32-bit information which could potentially easy flow analyser. This will be briefly discussed in the talk as well.
Lec6 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- Instruction...Hsien-Hsin Sean Lee, Ph.D.
This document discusses techniques for improving instruction fetch throughput in superscalar processors. It begins by explaining that fetch throughput defines the maximum performance and that superscalar processors need to supply more than one instruction per cycle. It then describes some challenges to high bandwidth instruction fetching including misaligned instructions, changes in control flow, and memory latency/bandwidth limitations. The document proceeds to discuss specific techniques like aligned fetching, split cache line access, predication, collapsing buffers, trace caches, and issues related to indexing and redundancy in trace caches.
This document contains questions for a mid-term exam on various topics related to soft computing.
The questions are divided into three sections:
Section A contains 4 multiple choice questions related to fuzzy set theory and operations. Section B contains 3 short answer questions on fuzzy sets, membership functions, and fuzzification.
Section C contains 2 longer theoretical questions, one involving sketching membership functions and defining 1-cut sets, and another involving fuzzy relations composition and cut sets.
The document provides guidance on answering questions from each section and notes that parts of questions should be answered together and diagrams can be used when needed. It also mentions that missing data can be assumed with justification.
This document discusses various arithmetic and logical instructions in 8051 microcontroller including ADD, SUBB, MUL, DIV, INC, DEC, DA, flags, logical operations, rotate instructions, swap instruction, and comparison operations. It provides examples to explain the working of instructions and how they affect the flag registers. It also summarizes the topics discussed in the lecture on arithmetic and logical operations in 8051 microcontroller.
The document describes an implementation of an LDPC decoder for IEEE 802.11n wireless networks using Vivado High-Level Synthesis. It implemented the decoder as a C program using Vivado HLS directives to optimize parallelism and throughput. The implementation achieved throughputs of over 1 Gbps and error correction performance comparable to an RTL implementation but with higher productivity due to the higher level of abstraction of C compared to RTL.
This document discusses turbo codes, which are a type of error correction code built by parallel concatenating two convolutional code blocks. It focuses on investigating the iterative decoding of turbo codes. The bit error rate is calculated over multiple iterations of decoding and plotted against signal to noise ratio. Quadratic permutation polynomial and random interleavers are analyzed. Results show turbo codes with a memory of 3 and 1280 bit interleaver achieve the best performance, reaching a bit error rate of 10-5 at -1.2 dB after 10 iterations of decoding.
This document provides an overview of the x86 microprocessor architecture. It discusses the history of x86 processors from the 8086 to modern Pentium and Intel 64-bit processors. It then describes the internal structure of the 8088/8086, including the bus interface unit, execution unit, registers, and flag register. It introduces assembly language programming and common instructions like MOV and ADD. It explains the code, data, stack, and extra segments and how logical addresses map to physical addresses. Memory allocation in IBM PCs is also summarized.
Microprocessor and Microcontroller Lab Manual!PRABHAHARAN429
The document describes experiments to be performed on an 8-bit microprocessor and microcontroller. It includes aims, block diagrams, flowcharts and assembly language programs for arithmetic operations, sorting an array, and interfacing experiments. Experiments cover topics like addition, subtraction, multiplication, division, ascending/descending order, maximum/minimum values, and interfacing components like ADCs, DACs, stepper motors. Similar experiments are outlined for an 8-bit microcontroller.
This document contains question banks for the subject VLSI Design (IV/I) covering 6 units:
1. MOS transistor fabrication and operation
2. Layout design rules and techniques
3. Scaling, delays, and logic implementation
4. Sequential circuits and subsystem design
5. Testing strategies and standard cell design
6. VHDL modeling and simulation
It provides over 150 questions ranging from conceptual explanations to circuit implementations to test verification strategies to assess student understanding of VLSI design principles and practices.
Static scheduling machines like VLIW move instruction scheduling from hardware to compiler by packing multiple operations into single instructions. This simplifies hardware but requires compilers to explicitly represent dependencies. The Intel Itanium ISA follows the VLIW philosophy, using instruction bundles containing up to 3 operations. Itanium 2 improved on the original design with an 8-stage pipeline and register renaming to boost performance. Itanium supports both control and data speculation via techniques like speculative loads and the Advanced Load Address Table.
This document introduces TensorFlow Lite for Microcontrollers (TF Micro) which brings machine learning to microcontroller applications. It discusses porting TF Micro to platforms like Arduino, converting TensorFlow models to a C array format compatible with MCUs, and using the TF Micro C++ API and interpreter to perform inference on embedded devices with limited memory and compute. Examples are provided of applying TF Micro to applications like speech recognition on microcontrollers.
The document summarizes the branch group instructions of the 8085 microprocessor. It describes jump instructions like JMP, conditional jump instructions, and the PCHL instruction. It also covers CALL and return instructions like CALL, RET, and conditional call and return instructions. Finally, it discusses restart instructions like RST that can be used as software interrupts to transfer program execution to specific restart locations.
1) A half-adder and full-adder are used to perform binary addition. A half-adder has two inputs and two outputs while a full-adder has three inputs and two outputs. Full-adders can be combined into a parallel adder to add binary numbers with multiple bits.
2) Comparators compare the magnitudes of two binary numbers and output signals to indicate if the numbers are equal, if the first is larger, or if the second is larger. Decoders detect a specific binary input code and output a signal. Common decoder uses include binary-to-decimal conversion and driving seven segment displays.
3) Integrated circuits like the 74LS47 BCD-to-seven segment decoder/driver
This document describes the architecture of the SAP-2 microprocessor. It has 16-bit address and data buses that can address 64K of memory space. The memory space includes 2K of ROM from addresses 0000H to 07FFH and 62K of RAM from 0800H to FFFFH. It has 8-bit registers including the accumulator, instruction register, flags, and temporary, B, and C registers. It supports common instructions like LDA, STA, MVI, ADD, SUB, logical operations, jumps, calls, inputs, outputs and rotations. The controller sequencer generates microinstructions to control the execution of up to 256 instructions, of which only 42 are implemented.
The document describes the Simple-As-Possible (SAP-1) computer. SAP-1 is a simple 8-bit computer designed to introduce fundamental computer concepts. It has 16 bytes of memory, 5 instructions, and components like an accumulator, registers, and an adder/subtractor connected via an 8-bit bus. The document explains the operation of each component and how they work together to execute instructions like load, add, subtract, output and halt.
This document contains model question papers for the 6th semester BE (CBCS) EC/TC course Digital Communication (15EC61). It includes 10 sample questions divided into 5 modules. Each question has 3 parts with marks allocated for each part. The questions test various topics related to digital communication systems including Hilbert transforms, line codes, orthogonal signals, probability of error, modulation techniques like PSK, QAM, FSK and demodulation. It also includes questions on channel equalization, spread spectrum, channel coding and error control coding.
8085 stack & machine control instructionprashant1271
The document describes the stack and machine control group of instructions for the 8085 microprocessor. It includes instructions for pushing/popping registers onto/from the stack, loading the stack pointer, exchanging registers with the stack pointer, no operation, halting the processor, enabling/disabling interrupts, and setting/reading the interrupt mask. Examples are provided for each instruction.
The document contains chapters from a digital fundamentals textbook covering topics such as combinational logic circuits, Karnaugh maps, universal gates, and pulsed waveforms. It provides examples of implementing sum-of-products expressions using AND-OR gates, converting circuits to NAND or NOR form, reading logic expressions from Karnaugh maps, and analyzing the output of combinational circuits with pulsed inputs. It also contains several practice problems with answers.
IFSM 310 Software and Hardware Infrastructure ConceptsComputer.docxscuttsginette
IFSM 310 Software and Hardware Infrastructure Concepts
Computer and Number Systems
1.
(10 pt)
You have been hired to develop a website-based sales system for a large international retail firm. List and describe at least four features that are specific to the Web design of your system and customer service important to consider if your system is to be successful at attracting and keeping customers living outside of the US. Include not only characteristics of the user interface, but those issues that must be uniquely addressed to successfully service your non-US customers.
2.
(2.5 pt each)
In order to receive credit for these problems, you must show all of the steps you took to arrive at your answers.
(c) Convert the following decimal number to binary:
21842
(d) Convert the following binary number to decimal:
11000111011.101
(c) Convert the following hexadecimal number to decimal:
CA97
(d) Convert the following binary number to hexadecimal:
1110011111011010100
CPU and Memory
3.
(10 pt)
ASCII, Unicode, and EBCDIC are, of course, not the only numeric / character codes. The Sophomites from the planet Collegium use the rather strange code shown in the Figure below. There are only thirteen characters in the Sophomite alphabet, and each character uses a 5-bit code. In addition, there are four numeric digits, since the Sophomites use base 4 for their arithmetic. Given the following Sophomite sequence, what is the corresponding binary message being sent by the Sophomites?
(HINT: Decode the sequence reading from left to right then write the corresponding binary sequence, leaving a space between each binary sequence.)
4.
(10 pt)
Define memory cache write-through and write-back techniques and describe the advantages and disadvantages of each.
Input / Output
5. Answer the follow questions about interrupts.
a.
(5 pt)
Describe in detail the steps that occur when a system receives an interrupt.
b.
(5 pt)
Describe how these steps differ in the case when a system receives multiple interrupts
Computer Systems
6. Answer the following questions about clusters.
a.
(5 pt)
Describe how you might use a cluster to provide fault-tolerant computing
b.
(5 pt)
Describe how you might use a cluster architecture to provide rapid scalability for a Web-based company experiencing rapid growth.
Networks
7. Answer the following questions about communication protocols.
a.
(5 pt)
Using the operations of UDP (User Datagram Protocol) and TCP (Transmission Control Protocol) as a basis, carefully explain the difference between connectionless and connection-oriented communication.
b.
(5 pt)
If you were ordering a number of items from an online seller, such as amazon.com, which Protocol (TCP or UDP) would you recommend and explain why
.
8. In the context of network security,
a.
(3 pt)
exp.
This exam includes multiple choice and "mark all that apply" questions worth a total of 100 points. There are also two essay questions for extra credit. Students have three hours to complete the closed-book exam. They must put away all books, notes, and electronic devices. The proctor cannot answer questions during the exam.
This document contains the questions and answers for an ECET 330 final exam. It includes 10 multiple choice questions covering topics like dynamic memory, von Neumann architecture, assembly language instructions, and bit manipulation. It also includes 5 programming questions involving manipulating values in memory locations and registers using assembly language and C on an HCS12 microcontroller. The document encourages purchasing access to exam solutions and course materials from an online test preparation website.
This document contains the questions and answers for an ECET 330 final exam. It includes 10 multiple choice questions covering topics like dynamic memory, von Neumann architecture, CodeWarrior assembler, HCS12 instruction set, BCD conversion, and creating pulse waves. It also includes 5 questions asking to write code sequences or programs to perform tasks like adding values from two memory locations, counting even/odd numbers in an array, and repeatedly writing values to locations with delays. The document provides a way to purchase access to solutions for exams, courses, and homework assignments.
This document contains the questions and answers for an ECET 330 final exam. It includes 10 multiple choice questions covering topics like dynamic memory, von Neumann architecture, CodeWarrior assembler, HCS12 instruction set, BCD conversion, and creating pulse waves. It also includes 5 questions asking to write code sequences or programs to perform tasks like adding values from two memory locations, counting even/odd numbers in an array, and repeatedly writing values to locations with delays. The document provides a way to purchase access to solutions for exams, courses, and homework assignments.
The document contains a practice quiz for the CCNA certification. It includes 35 multiple choice questions covering topics like:
- Network layer protocols like IP, TCP, UDP
- Ethernet standards and speeds
- Router and switch functions like MAC address tables, VLANs, trunking
- IP addressing schemes including public/private addressing, subnetting, CIDR notation
The quiz questions test knowledge of networking concepts, protocols, hardware functions and configurations, and IP addressing fundamentals.
I am Frank Allen. I am a Computer Architecture Assignment Expert at architectureassignmenthelp.com. I hold a Master's in Computer Architecture from, Ontario Tech University, Canada. I have been helping students with their assignments for the past 10 years. I solve assignments related to Computer Architecture.
Visit architectureassignmenthelp.com or email info@architectureassignmenthelp.com. You can also call on +1 678 648 4277 for any assistance with Computer Architecture Assignments.
This document contains a quiz on digital forensics and embedded systems. It includes 43 multiple choice questions covering topics like digital evidence collection, drive slack, Windows registry, microcontrollers, RISC vs CISC architectures, VME bus, embedded system design constraints, assembly language, AVR registers and program counter. The questions test knowledge of technical concepts and terminology in these subject areas.
This document contains 15 multiple choice questions related to assembly language programming on 8086 microprocessor. The questions cover various assembly language instructions like conditional jumps, arithmetic operations, stack operations, bit manipulation instructions and their output for different operand values.
Digital Electronics & Computer Oraganisation
We Also Provide SYNOPSIS AND PROJECT.
Contact www.kimsharma.co.in for best and lowest cost solution or
Email: amitymbaassignment@gmail.com
Call: 9971223030
The document contains 10 multiple choice questions about the control unit of a computer. It tests knowledge about the basic functions of the control unit, including that it coordinates and synchronizes the activities of other parts of the CPU. It ensures the sequential execution of instructions by fetching instructions from memory, decoding them, and generating control signals to direct the flow of data between ALU, registers and memory.
This document contains a quiz on VLSI design and EDA tools. It includes multiple choice questions on topics like VHDL modeling types, sequential circuits, boundary scan testing, nMOS devices, CMOS logic design, programmable logic devices and FPGAs. Some key points covered are the basic uses of EDA tools for simulation and synthesis, different types of modeling in VHDL like behavioral and structural, memory elements like flip-flops used in sequential circuits, and factors that influence speed in CMOS logic gates.
The ADD instruction performs 32-bit addition of two register operands and stores the result in a third register. It updates the N, C, Z, and V flags based on the result. There are no limitations. Examples demonstrate adding two values and storing the result in a third register.
The document contains a sample test for the CDAC Common Admission Test (C-CAT) consisting of 3 sections with a total of 49 multiple choice questions covering topics such as English, programming, computer networks, operating systems, data structures, object-oriented programming, digital logic, and computer architecture. The test is assessing fundamental knowledge expected of candidates applying for admission to CDAC programs.
This document contains 60 multiple choice questions related to embedded instrumentation systems, operating systems, and computer security. The questions cover topics such as real-time systems, scheduling, inter-process communication, virtual memory, deadlocks, and cryptography. Answers or explanations are not provided.
Multiprogramming allows multiple programs to share processor resources while multi-threading allows a program to split itself into multiple, simultaneously executing threads. Assembly language should generally be avoided but may be useful for performance-critical code or when close interaction with hardware is needed. Compiled languages have performance advantages over interpreted languages but interpreted languages are more portable and allow for interactive development. Superscalar processing improves performance over scalar pipelines by allowing multiple instructions to execute simultaneously through parallel pipelines while superpipelining breaks instructions into smaller sub-parts to reduce idle times between instructions.
The document provides an introduction to microcontrollers, DTMF receivers, and assembly language programming as relevant to a project interfacing a microcontroller with a DTMF receiver. It describes the key components, including the AT89C51 microcontroller's features like 4K bytes of flash memory, ports, timers/counters, serial port, and power saving modes. It also covers the DTMF receiver's use of dual tones to generate digits 0-9, and how the microcontroller will receive and process these codes.
The document contains multiple choice questions related to microprocessors and microcontrollers. It covers topics like 8085 architecture, 8051 architecture, 8051 registers and SFRs, addressing modes, 8086 assembly language instructions, and their operation. Some questions test understanding of interrupt priorities, I/O addressing, stack operations, arithmetic and logical instructions on 8-bit and 16-bit processors.
LAB3/Lab 3 Answer Sheet(1).docx
Liberty University
CSIS331
Lab 3 Answer Sheet
Submit this completed document with your completed and saved packet tracer in the link provided in Blackboard.
Part 1: Questions.
Step 1:
a. Which command displays the statistics for all interfaces configured on a router?
b. Which command displays the information about the Serial 0/0/0 interface only?
c. 1) What is the IP address configured on R1?
c. 2) What is the bandwidth on the Serial 0/0/0 interface?
d. 1) What is the IP address on R1?
d. 2) What is the MAC address of the GigabitEthernet 0/0 interface?
d. 3) What is the bandwidth on the GigabitEthernet 0/0 interface?
Step 2. Questions.
a. Which command displays a brief summary of the current interfaces, statuses, and IP addresses assigned to them?
b. 1) How many serial interfaces are there on R1 and R2?
b. 2) How many Ethernet interfaces are there on R1 and R2?
b. 3) Are all the Ethernet interfaces on R1 the same? If no, explain the difference(s).
Step 3: Display the routing table on R1.
a. What command displays the content of the routing table?
b. 1) How many connected routes are there (uses the C code)?
b. 2) Which route is listed?
b. 3) How does a router handle a packet destined for a network that is not listed in the routing table?
Part 2 Step 3
a. What command did you use?
Part 3 Step 1
a. 1) How many interfaces on R1 and R2 are configured with IP addresses and in the “up” and “up” state?
a. 2) What part of the interface configuration is NOT displayed in the command output?
a. 3) What commands can you use to verify this part of the configuration?
b. 1) How many connected routes (uses the C code) do you see on each router?
b. 2) How many EIGRP routes (uses the D code) do you see on each router?
b. 3) If the router knows all the routes in the network, then the number of connected routes and dynamically learned routes (EIGRP) should equal the total number of LANs and WANs. How many LANs and WANs are in the topology?
b. 4) Does this number match the number of C and D routes shown in the routing table?
Ping Table:
Ping From Device IP
Ping to Device IP
Results
PC1
PC4
R2
PC2
__MACOSX/LAB3/._Lab 3 Answer Sheet(1).docx
LAB3/Lab 3.pka
__MACOSX/LAB3/._Lab 3.pka
LAB3/Lab 3 Instructions(1).docx
Liberty University CSIS331
Liberty University
CSIS 331
Lab 3 Instructions
Packet Tracer:
[Adapted from Cisco Networking Academy Intro to Networking 6.4.3.3]
Overview
In this activity, you will use various show commands to display the current state of the router. You will then use the Addressing Table to configure router Ethernet interfaces. Finally, you will use commands to verify and test your configurations.
Note: The routers in this activity are partially configured. Some of the configurations are not covered in this course, but are provided to assist you in using verification commands.
Part 1: Display Router Information
Step 1: Display interface information on R1. ...
Real JN0-280 Dumps (V8.02) - Help You Crack JN0-280 Exam Quickly.pdfyarusun
By cracking the JN0-280 exam, you put your career on the right track and achieve your objectives in a short period. With the help of DumpsBase real JN0-280 dumps, you can make the Data Center, Associate (JNCIA-DC) preparation simple and successful. The JN0-280 exam dumps (V8.02) are verified by experienced and qualified experts. These updated JN0-280 practice questions provide you with everything that you need to crack the JN0-280 exam quickly. #Real JN0-280 Dumps #DumpsBase
ISO/IEC 27001, ISO/IEC 42001, and GDPR: Best Practices for Implementation and...PECB
Denis is a dynamic and results-driven Chief Information Officer (CIO) with a distinguished career spanning information systems analysis and technical project management. With a proven track record of spearheading the design and delivery of cutting-edge Information Management solutions, he has consistently elevated business operations, streamlined reporting functions, and maximized process efficiency.
Certified as an ISO/IEC 27001: Information Security Management Systems (ISMS) Lead Implementer, Data Protection Officer, and Cyber Risks Analyst, Denis brings a heightened focus on data security, privacy, and cyber resilience to every endeavor.
His expertise extends across a diverse spectrum of reporting, database, and web development applications, underpinned by an exceptional grasp of data storage and virtualization technologies. His proficiency in application testing, database administration, and data cleansing ensures seamless execution of complex projects.
What sets Denis apart is his comprehensive understanding of Business and Systems Analysis technologies, honed through involvement in all phases of the Software Development Lifecycle (SDLC). From meticulous requirements gathering to precise analysis, innovative design, rigorous development, thorough testing, and successful implementation, he has consistently delivered exceptional results.
Throughout his career, he has taken on multifaceted roles, from leading technical project management teams to owning solutions that drive operational excellence. His conscientious and proactive approach is unwavering, whether he is working independently or collaboratively within a team. His ability to connect with colleagues on a personal level underscores his commitment to fostering a harmonious and productive workplace environment.
Date: May 29, 2024
Tags: Information Security, ISO/IEC 27001, ISO/IEC 42001, Artificial Intelligence, GDPR
-------------------------------------------------------------------------------
Find out more about ISO training and certification services
Training: ISO/IEC 27001 Information Security Management System - EN | PECB
ISO/IEC 42001 Artificial Intelligence Management System - EN | PECB
General Data Protection Regulation (GDPR) - Training Courses - EN | PECB
Webinars: https://pecb.com/webinars
Article: https://pecb.com/article
-------------------------------------------------------------------------------
For more information about PECB:
Website: https://pecb.com/
LinkedIn: https://www.linkedin.com/company/pecb/
Facebook: https://www.facebook.com/PECBInternational/
Slideshare: http://www.slideshare.net/PECBCERTIFICATION
How to Build a Module in Odoo 17 Using the Scaffold MethodCeline George
Odoo provides an option for creating a module by using a single line command. By using this command the user can make a whole structure of a module. It is very easy for a beginner to make a module. There is no need to make each file manually. This slide will show how to create a module using the scaffold method.
বাংলাদেশের অর্থনৈতিক সমীক্ষা ২০২৪ [Bangladesh Economic Review 2024 Bangla.pdf] কম্পিউটার , ট্যাব ও স্মার্ট ফোন ভার্সন সহ সম্পূর্ণ বাংলা ই-বুক বা pdf বই " সুচিপত্র ...বুকমার্ক মেনু 🔖 ও হাইপার লিংক মেনু 📝👆 যুক্ত ..
আমাদের সবার জন্য খুব খুব গুরুত্বপূর্ণ একটি বই ..বিসিএস, ব্যাংক, ইউনিভার্সিটি ভর্তি ও যে কোন প্রতিযোগিতা মূলক পরীক্ষার জন্য এর খুব ইম্পরট্যান্ট একটি বিষয় ...তাছাড়া বাংলাদেশের সাম্প্রতিক যে কোন ডাটা বা তথ্য এই বইতে পাবেন ...
তাই একজন নাগরিক হিসাবে এই তথ্য গুলো আপনার জানা প্রয়োজন ...।
বিসিএস ও ব্যাংক এর লিখিত পরীক্ষা ...+এছাড়া মাধ্যমিক ও উচ্চমাধ্যমিকের স্টুডেন্টদের জন্য অনেক কাজে আসবে ...
Strategies for Effective Upskilling is a presentation by Chinwendu Peace in a Your Skill Boost Masterclass organisation by the Excellence Foundation for South Sudan on 08th and 09th June 2024 from 1 PM to 3 PM on each day.
The simplified electron and muon model, Oscillating Spacetime: The Foundation...RitikBhardwaj56
Discover the Simplified Electron and Muon Model: A New Wave-Based Approach to Understanding Particles delves into a groundbreaking theory that presents electrons and muons as rotating soliton waves within oscillating spacetime. Geared towards students, researchers, and science buffs, this book breaks down complex ideas into simple explanations. It covers topics such as electron waves, temporal dynamics, and the implications of this model on particle physics. With clear illustrations and easy-to-follow explanations, readers will gain a new outlook on the universe's fundamental nature.
Exploiting Artificial Intelligence for Empowering Researchers and Faculty, In...Dr. Vinod Kumar Kanvaria
Exploiting Artificial Intelligence for Empowering Researchers and Faculty,
International FDP on Fundamentals of Research in Social Sciences
at Integral University, Lucknow, 06.06.2024
By Dr. Vinod Kumar Kanvaria
Executive Directors Chat Leveraging AI for Diversity, Equity, and InclusionTechSoup
Let’s explore the intersection of technology and equity in the final session of our DEI series. Discover how AI tools, like ChatGPT, can be used to support and enhance your nonprofit's DEI initiatives. Participants will gain insights into practical AI applications and get tips for leveraging technology to advance their DEI goals.
How to Fix the Import Error in the Odoo 17Celine George
An import error occurs when a program fails to import a module or library, disrupting its execution. In languages like Python, this issue arises when the specified module cannot be found or accessed, hindering the program's functionality. Resolving import errors is crucial for maintaining smooth software operation and uninterrupted development processes.
1. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
Section – A
1. Which of the following regular expressions describes the language- the set of
all strings over {0, 1} containing at least two 1’s?
A. (0+1)*11(0+1)*
B. 0*110*
C. 0*10*10*
D. (0+1)*1(0+1)*1(0+1)*
2. Which of the following is / are regular language(s) ?
I. { am
bn
| m , n ≥0}
II. {w є {a, b}*| has equal number of a’ s and b’ s}
III. {am
bn
| m>n}
IV. {w є {a , b}* w has even number of a’ s}
A. Only
B. And only
C. And only
D. Only
3. Which of the following is true?
A. For every NFA there is an equivalent PDA.
B. Nondeterministic TMs are more powerful than deterministic TMs.
C. DPDAs and NPDAs are equivalent in power.
D. NFAs accept the class of CFLs.
4. Let L be a CFL. Then L’ must be
A. CFL but not regular.
B. Recursive.
C. Recursively Enumerable but not Recursive.
D. Regular but not CFL.
5. Which of the following is FALSE?
A. CFLs are closed under union but not closed under complement.
B. Regular sets are closed under intersection and Kleene Closure.
C. Recursive languages are closed under intersection but not closed under
complement.
D. Recursively enumerable languages are closed under union and
intersection.
2. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
6. Which of the following is NOT POSSIBLE?
A. Finding out a minimal DFA for any arbitrary regular language.
B. Constructing a deterministic TM for any arbitrary CFL.
C. Determining whether two CFGs generate the same language.
D. Given an arbitrary TM M (which halts on all inputs) whether the
complement of the language accepted by M is recursive.
7. Which of the following is FALSE?
A. Regular expressions and DFAs are equivalent.
B. A DPDA cannot accept by any arbitrary CFL.
C. The language accept by any TMs is a CFL.
D. Complement of every regular language is CFL.
8. Consider the languages L1 and L2 given below.
L1= {<M1, M2>| M1 and M2 are NFAs and L (M1 )= L (M2)}
L2= {<M1, M2>| M1 and M2 are TMs and L (M1 )= L (M2)}
Which of the following is true?
A. L1 is undecidable but L2 is decidable.
B. L2 is undecidable but L1 is decidable.
C. Both L1 and L2 are undecidable.
D. Both L1 and L2 are decidable.
Let A and B be languages corresponding to two decision problems A and B
respectively. Let A be NP – complete problem, then hat would not B NP.
Which of the following is true?
10. if there is a polynomial time algorithm for an NP- complete problem, then that
would not imply which of t he following:
A. P = NP
B. NP = Co- NP
C. P = NP ∩ Co-NP
D. P NP
3. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
11. A 1KB RAM can be organized as an 8 K bit RAM.
A. Using a 1 to 8 line demultiplexer.
B. Using an 8 to 1 multiplexer.
C. Using an 8 – input OR gate.
D. None of the above.
12. A 2 KB RAM can be economically organized using-
A. 64 numbers of 256 bit RAM chip and a 1/8 line decoder.
B. 64 numbers of 256 bit RAM chip and a 1/64 line decoder.
C. 8 numbers of 256 bit RAM chips and a 1/8 line decoder.
D. 8 numbers of 256 bit RAM chips and a 1/64 line decoder
13. With reference to RETURN instruction, which of the following statement is /
are true?
1. The instruction can be used only to take the flow of control back to the
program from which it initially jumped.
2.The instruction retrieves the address using the current stack pointer from
the stack and alters the control to the program pointed to by it.
3. The instruction works only if the registers used in the main program have
been pushed and later popped before its execution.
4.The instruction can be used only in conjunction with the call instruction.
A. 1st
and 2nd
B. 2nd
only
C. 1st
, 2nd
and 3rd
only
D. All the statement are true
14. In an n- CPU shared bus system, if is the probability that any CPU requests
the bus in a given cycle, the probability that only one CPU uses the bus is
given by-
A. Nz(1-z)(n-1)
B. Z(1-z)(n-1)
C. N(1-z)n
D. (N-1)z(1-z)n
4. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
15. A variable X has been assigned fresh values in statements numbered 6, 9 and
12 in a 25- statement program which does not have any jump instructions.
This variable is used in statements numbered 7, 8, 10, 16 and 17.the statement
range where the register, used by the variable X, could be assigned to some
other variable are-
A. 8-9, 10- 12, 17- 25
B. 11, 18-25
C. 17-25
D. Non of the above
16. If the Intel Pentium processors, was not made compatible to programs written
for its predecessor, it could have been designed to be a faster processor.
A. The statement is true
B. The statement is false
C. The speed cannot be predicted.
D. Speed has nothing to do with the compatibility.
17. A certain snooping cache an snoop only an address lines. Which of the
following is true?
A. This would adversely affect the system if the write through protocol is
used.
B. This would run well if the write through protocol is used.
C. Data snooping is mandatory.
D. None of the above.
18. Repeated occurrence of identical interrupt during execution of this service
routine can result in-
A. Program error.
B. Stack overflow.
C. Hardware error.
D. None of the above.
19. Micro programmed control is not fit for RISC architectures because-
A. It tends to slow down the processor.
B. It consumes more chips area.
C. Handling a large number of registers is impossible in micro programmed
systems.
D. The 1 instruction / cycle timing requirement for RISC is difficult to
achieve for all instructions.
5. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
20. A certain RISC processor has 12register windows and 16 global registers.
Each window has 8 input, 16 local and 8 output registers. The total number of
registers in the processor is –
A. 312
B. 320
C. 296
D. 304
21. In a certain system the main memory access time is 1000 ns. The cache
memory is 10 times faster then the main memory uses the write through protocol.
If the hit ratio for read request is 0.92 and 85% of the memory requests generated
by the CPU are for the read, the remaining being for write, then the average time
considering both read and write request is –
A. 14.62 ns
B. 348.47 ns
C. 29.62 ns
D. 296.2 ns
22. Shown below are segments of a code run on a CISC and a RISC architecture
separately.
CISC RISC
MOV AX, 05 MOV AX, 00
MOV BX, 06 MOV BX, 05
MUL AX, BX; Multiply AX with BX MOV CX, 06
START: ADD AX, BX
LOOP START ; loop till
CX=0
If the MUL instruction takes 402 clock cycles, which of the following statement is
true?
A. The CISC code will faster by a factor of 1.8.
B. The RISC code will run aster by a factor of 2.8.
C. The CISC code will faster by a factor of 0.025.
D. The RISC code will run aster by a factor of 40.
6. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
23. The frequent of different types of instructions executed by a machine is
tabulated below.
Operand Accessing Mode Frequency in %
register 30
Immediate 20
Direct 22
Memory indirect 17
Index 11
Assuming two cycles are consumed for an operand to be read from the memory,
one cycle for index arithmetic computations and zero cycles if operands are
available in registers or with in instruction itself, the average operand fetch rate of
the machine is-
A. 1.45
B. 2.45
C. 2.67
D. 2.34
24. A 1 ns cycles time unpipeline processor consumes 4 cycles for ALU operations,3
cycles for branches and 5 for memory operations. The relative frequencies of these
operations are 45%, 15% and 40% respectively. What is the speedup in the
instruction execution rate if the same were pipelined? Assume a 0.4 ns overhead
consumed in setup and clock skew taken together.
A. 4.25
B. 3.04
C. 3.85
D. 3.44
25. the range of intigers that one can represent using an n –bit 2s complement number
system is –
A. -2(n-1)
to (2n
-1)
B. -2(n-1)
to (2(n-1)
-1)
C. -2n
to(2n
-1)
D. -2n
+1 to (2(n-1)
-1)
26. the octal representation of the number (1FO)16 is-
A. (760)8
B. (13300)8
C. (170)8
D. (180)8
7. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
27.
The minimized function f obtained from the K-map given above is –
a) C’E’+A’BCE+BCD’E
b) B’C’E’+A’BCE+ABCD’E+BC’E’
c) C’E’+A’BCE+BCDE
d) B’C’E+A’BCE+ABCD’E+BC’E
28. The standard sum of products of the function f = A+B’c is expressed as-
A. ∑m(1, 4, 5, 6, 7) + d(0, 2, 3)
B. ∑m(1, 4, 5, 6, 7)
C. ∑m(0, 2, 3) + d(1, 4, 5, 6, 7)
D. ∏M (1, 4, 5, 6, 7)
29. hazards in combinational circuits are removed by-
A. Enclosing the minterms that cause the hazard with a product term that overlaps
both groupings.
B. Using NOT gates at all inputs.
C. Using NOT gates at all outputs.
D. None of the above.
8. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
30. four D – type flip flops are connected in such a manner that output Qi of one is
connected to the D input of the next flip flop.the input to the initial D-flip flop is
given by
D1 =Q3 XOR Q 4
All flip flops are clocked synchronously. Which of the following statements is /are
true?
i. D1 is ahead of Qi by one clock pulse.
ii. The circuit outputs the sequence 100010011010111 along all Qi ‘s
A. Only (i) is true
B. Only (ii) is true
C. Both (i) and (ii) are true
D. None of the statement is true.
31. Three is NOT gates are cascaded and the out put of the third provides input to the
first. Which of the following statements is true?
A. The connection from the output to the will lead to contention and hence damage
the circuit on power on.
B. The output is unpredictable making the circuit useless.
C. The output will be uniformly held at either logic 0 and logic 1.
D. The out put will alternate between logic 0 and logic 1 continuously.
32. A certain device dumps data into its interface register every 200 ns. The main
memory access time is 50 ns. If the CPU were interfaced to his device in cycle
stealing mode, what percentage of time does the CPU be in hold state?
A. 20
B. 25
C. 50
D. None of these
33. If a disc has a rotation speed of R rpm and track storage capacity of C bits, the data
transfer rate of the drive is defined as-
A. R/C bits/min
B. C/R bits/min
C. 0.5(R*C) bits/min
D. R*C bits/min
9. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
34. In the NONIX operating system, the time required for various file read operations are
given below:
Disk seek time: 25 msec
Disk latency time: 8 msec
Disk transfer time: 1 msec/Kbyte
Operating system overheads: 1 mse/Kbyte + 10 msec.
What is the time required to retrieve a block of Kbytes?
A. 45 msec
B. 47 msec
C. 90 msec
D. 94 msec
35. Which of t he following page replacement method guarantee the minimum number of
page faults?
A. Replace the page whose next reference will be the farthest in future.
B. Replace the page whose next reference will be the nearest in future.
C. Replace the page whose most recent reference was the nearest in past.
D. Replace the page whose most recent reference was the farthest in past
36. Which of the following statement is/are true about paging?
P: it divides memory into units of equal size.
Q: it permits implementation of virtual memory.
R: it suffers from internal fragmentation.
A. P only
B. Q only
C. R only
D. P and Q only
37. The sequence of page addresses generated by program is 1, 2, 2, 1, 3, 4, 2, 1, 3, 4.
This program is run on a system with main memory size equal to 3 pages. Which
pages are in the memory just before 5th
page fault, if least recently used page
replacement is followed?
A. 1, 2, 3
B. 1, 2, 4
C. 1, 3, 4
D. 2, 3, 4
10. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
38. Assume that the following jobs are to be executed on a single processor system.
Job id CPU burst time
1 3
2 4
3 5
4 1
Assume that the jobs are arrived at time 0* and in the 1, 2, 3, 4. for round robin
scheduling with time slice 1, what is the completion time for the jobs 2?
A. 7
B. 8
C. 9
D. 11
39. Consider the following jobs given below:
Job id arrival time CPU time
1 0 4
2 3 7
3 7 4
4 1 1
Shat is the average turnaround time with non- preemptive shortest job first scheduling
algorithm?
A. 2.75
B. 5.75
C. 6.5
D. 8.5
40. which of the following statement is /are TRUE about thrashing?
P: implies excessive page faults.
Q: CPU utilization decreases
R: implies less page faults.
A. P only
B. Q only
C. P and Q only
D. Q and R only
41. a computer system has 9 printers, with a processes competing for them. Each process
needs 3 printers. What is the maximum value of n for the system to be deadlock free?
A. 3
B. 4
C. 5
D. 6
11. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
42. A counting semaphore was initialized to eight. Then four P (wait) operations and six
V (signal) operations are performed on the semaphore. What is the resulting value of
the semaphore?
A. 0
B. 8
C. 10
D. 12
43. A computer system uses the Banker’s algorithm to deal with deadlocks its current
state is shown in the table below, where P0, P1, P2 and P4 are processes and A, B, and
C are resources types.
Maximum
A B C
P0 6 5 4
P1 3 4 2
P2 1 0 4
P3 3 2 5
Allocated
A B C
P0 0 3 4
P1 2 1 2
P2 0 0 2
P3 1 2 1
Available
A B C
4 3 1
Which of t he following is/are safe sequences?
P: P1, P0, P2, P3
Q: P1, P2, P0, P3
R: P1, P3, P0, P4
A. P and Q only
B. P and R only
C. Q and R only
D. All P, Q and R.
44. Which of the following most appropriately describes the language generated by the
grammer: S aSa| bSb | ε
A. The set of string over {a, b} that begin and end with the same symbol.
B. The set of palindromes over {a, b}.
C. The set of string over {a, b}with equal number of a’s and b’s.
D. The set of even length palindromes over {a, b}.
12. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
45. Consider the rule of the C programming language –“every variable must be declared
before its use.” in which of the following phase of the compiler will an error violating
this rule be detected?
A. Code generation
B. Lexical analysis
C. Syntax analysis
D. Semantic analysis.
46. Find the best match between the element of Group-1 and Group -2 given below.
Group-1 Group -2
P. Dataflow analysis 1. Lexical analysis
Q: Regular expression 2. Semantic analysis
R: Type Checking 3.Parsing
S: Pushdown Automata 4. Code optimization
A. P-4, Q-1, R-3, S-2
B. P-2, Q-1, R-4, S-3
C. P-1, Q-4, R-2, S-3
D. P-4, Q-1, R-2, S-3
47. Consider the grammar: S L= R | R
L * R | id
R L
Which of the following set of LR (0) items definitely does not represent a valid state
of an LR (0) parser?
A. S L =∙R, R ∙L
B. L id.
C. S L∙ = R, R L∙
D. R L∙
48. Which of the following is/are true?
i. A left – recursive grammar cannot be LL( 1 ).
ii. A right – recursive gammar cannot be LR(1).
iii. Every grammar that can be parsed by a canonical LR parser can also be
parser by some SLR parser.
A. I and II only
B. I only
C. II only
D. I,II and III
13. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
49. Consider a state of an LR ( 0) parser containing the following two items only.
A → abB∙
C → a∙b
Which of the following CAN NOT be deducted from the information provided
above?
A. There is shift – reference conflict in the parsing table.
B. The given grammar is not LR(0).
C. There is reduce – reference conflict in the parsing table.
D. The goto function for this state on symbol b must lead to some state.
50. Who developed the original version of SQL?
A. Oracle
B. IBM
C. mySQL AB
D. Microsoft
51 for the relational schema RK1K2 are the only candidate keys. R has a functional
dependency X A where X is a set of attributes and A is an attribute. It is known
that A K1 and A K2 and X is not a superkey. Which of the following is true?
A. R should be in BCNF.
B. R is not surely in BCNF, but could be in 3NF
C. R is not surely in 3NF, but could be in 2NF
D. R is not surely in 2NF, but could be in 1NF
52. R is a rational schema with the following functional dependencies.
A DC B A C E E BD
Which of the following is not a candidate key of R.
A. AD
B. BE
C. CD
D. AB
53. If the following elements are inserted in the given order into initially empty B+tree in
which each node can hold at most 4 pointers, what will be the number of leaf nodes in
the B+ tree at the end of the insertions?
1 3 5 6 7 8 14 22 32 33 37
A. 4
B. 5
C. 6
D. 7
54. In the following, T1 and T2 are transactions and A is an object. Which of the
following has the potential of making T2 irrecoverable?
A. T2 writes A after T1 wrote A; T1 is uncommitted
B. T2 reads A after T1 wrote A ; T1 is uncommitted
C. T2 writes A after T1 wrote A ; T1 is committed
D. T2 reads A after T1 wrote A; T1 is uncommitted
14. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
55. Which of the following is impossibility?
A. A sparse primary index
B. A sparse secondary index
C. A dense primary index
D. A dense secondary index
56. RDBMS QUERY
57.RDBMS Query
58.DBMS Query
59. Arrange the following functions in increasing asymptotic order
(P)√ (log2n) (Q)√ n (R) 2 (
log2n / log2 log2n)
/*power of 2(then log part) */
(S) log2 log2(n!)
A)PQSR
B)PQRS
C)PSRQ
D)SPQR
60.Which of the following is false?
A) the aveg case time complexities of quick sort and heap sort are O(nlogn).
B) the worst case time complexities of quick sort and heap sort are O(n2
).
C) the aveg case time complexities of merge sort and insertion sort are O(n2
).
D) the worst case time complexities of quick sort and merge sort are O(nlogn).
61.Which of the following exemplifies Divide and conquer?
A)Heapsort
B)Insertion sort
C)Bubble sort
D)Merge sort.
62.Consider a sequence A of length n which is sorted except for one item that appears
out of order.Which of the following can sort the sequence in O(n) time?
A)Heapsort
B)Quick sort
C)Merge sort
D)Insertion sort.
63.If T(n)= 3T(n/2)+n, if n>1. T(1)=1. Then T(n)=?
A)Θ(n)
B) Θ(n (
log2
3
) ) { n to the power log23}
C)Θ(n 3/2
)
D) Θ(n (
log2
3
) log2
n
)
15. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
64.Let S1= ∑nr/2r
(r=0 to logn-1) .S2= ∑r2r
(r=0 to logn-1)
Which of the following is true?
A)S1= Θ(nlogn),S2= Θ(nlogn)
B) S1= Θ(n),S2= Θ(nlogn)
C) S1= Θ(nlogn),S2= Θ(n)
D) S1= Θ(n),S2= Θ(n)
65.Question based on Dynamic programming with memorization. Complexity is asked
for a function.
66. To remove recursion from a program we have to use the following data structure:
A. array
B stack
C queue
D list
67. Absence of terminating condition in a recursive program causes the following run
time error:
A) array out of bounds
b) stack overflow
c) null ptr access
d) division by zero
68.On a set of n elements linear search is preferred over binary search when there are :
a)Ω(log n) queries
b) O(log2
n) queries
c) o(log n) queries
d) Θ(log2
n) queries
69.#include <stdio.h>
Void main() {
Int a=4,b=5,c=6;
C+=a++ + ++b;
Printf(“a=%d,b=%d,c=%d, n”,a,b,c);
}
What is the o/p of the above c program:
a) 5 6 17
b) 56 18
c) 5 5 16
d) 5 6 16
16. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
70.what is the max size of the operator stack during the conversion of the infix exp
A+B*C-D/E to postfix?
A)1
B)2
c)3
D)4
71. what is the max size of the operand stack while evaluating the postfix exp
6 2 3 + - 3 8 2 / + * ?
A)1
B)2
c)3
D)4
72. binary search can be carried out on the set of ordered out on a set of ordered data
items stored in a:
A. array
B stack
C queue
D list
73. To o/p a binary tree level by level we have to use the following data structure
A. array
B stack
C queue
D list
74. Which one of the following arrays satisfies max-heap property?
A) 16,10,12,8,3,5
B)16,8,5,10,12,3
c)16,12,8,3,5,10
D)10,16,12,8,5,3
75.The max number of comparisons required to sort 5 elements is
a) 4
B) 5
c) 6
d)7
76 The worst case time complexity of quicksort for n elements when the median is
selected as the pivot element is :
a)Θ (n2
)
b) O(n2
)
c)Θ (n log n)
d) o( n log n)
17. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
77.The number of null links in a binary tree with n nodes is :
a) n-1
b) n
c) n+1
d) 2n
78.What is the max possible height of an AVL tree with 20 nodes ?
a)4
B) 5
c) 6
d)7
79.let T be a B-tree of order m and height h. If n is the no of key elements in T then the
max value of n is :
a)(m-1) h
-1
b)(m-1) h-1
+1
C) m h
-1
D) m h-1
+1
80. Adjacency list is preferred over adjacency matrix when the graph is :
a)Planar
B) Dense
c) Clique
D) None of the above
81.A binary tree can be uniquely reconstructed from the following traversal(s):
A) preorder
B) postorder
c) preorder and postorder
d) inorder and preorder
82. In a simple connected undirected graph with n nodes (n>=2) the max number of
nodes with distinct degrees is
a) n-1
b)n-2
c) n-3
d)2
83. The max number of edge disjoint cut sets in a simple graph with n nodes is:
a) n
b)
c)2 n
d)n-1
18. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
84.If an undirected graph has Hamiltonian cycle then it is definitely :
a) tree
b) clique
c) Bi-connected
d) Tri-connected
85.If an undirected graph doesn’t have an odd cycle , then it is:
A)tree
b)planer
c)Bi-partite
d) clique
86. To color a cycle of length 9, max number of colors required is :
a)2
b)3
c)4
d)5
87.what is the number of edge disjoint Hamiltonian cycles in a complete graph G=(V,E),
where |v|=n and n is odd?
a)n
b)┌ n/2 ┐
c(n-1)/2
d) n 2
88. Given a set of n elements not all distinct, the majority element is one with freq>=n/2.
So the majority elements is always the
A) max element
B) minimum element
C) mean element
D) median element
89.Let 01111 be the frame delimiter flag in a data link protocol. What is the transmitted
bit sequence for the data 0111110111011110 using the bit stuffing method?
a) 0111110111011110
b) 011101101110111010
c) 01111011011100111010
d) 011100110111001110010
19. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
90. A frame 110010111001 is to be transmitted using the CRC with generating poly
x3
+x+1 to protect it from errors. What is the transmitted frame?
a)1101011001010
b)1111010110010
c)1110110110101
d)1110111010111
91.The distance between two microwave towers, with link capacity 100Mbps, is 24km
and the speed of the signal is 3X108
m/s. If the frame size is 16kb in the stop and wait
protocol, what is the approx link utilization ? assume that the ack packets are negligible
in size and there are no errors during comm..
A)33%
B)50%
C)66%
D) 75%
92.Two ground stations r connected by a 10Mbps Sat link. The altitude of the satellite is
36000km and the speed of the signal is 3X108
m/s.What shd be the packet size for the
channel utilization of 50% using go-back-100 sliding window protocol? assume that the
ack packets are negligible in size and there are no errors during comm..
a) 1.5Kbytes
b)3 Kbytes
c)4.5 Kbytes
d)6 Kbytes
93.Match the following
I data link layer P. POP3
II network layer Q. UDP
III Transport layer R. RARP
IV App layer S. PPP
A) I-P, II-Q, III-R ,IV-S
B) I-P, II-R, III-Q ,IV-S
C) I-S, II-Q, III-R ,IV-P
D) I-S, II-R, III-Q ,IV-S
20. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
94.The sound trip propagation delay for 100Mbps Ethernet having 48-bit jamming signal
is 64 μs .What is the minimum frame size?
A) 400 bytes
B)600 bytes
C)800 bytes
D) 1400 bytes
95. Match the following
I 802.3 P. wireless LAN
II 802.11 Q. Bluetooth
III 802.15 R. Ethernet
IV 802.16 S. wireless MAN
a) I-R, II-P, III-Q ,IV-S
b) I-R, II-P, III-S ,IV-Q
c) I-R, II-Q, III-P ,IV-S
d) I-P, II-R, III-S ,IV-Q
96.Match the following
I GATEWAY P. PHYSICAL LAYER
II SWITCH Q. DATA LINK LAYER
III ROUTER R. NETWORK LAYER
IV HUB S. TRANSPORT LAYER
a) I-S, II-P, III-R ,IV-Q
b) I-S, II-R, III-Q ,IV-P
c) I-R, II-Q, III-S ,IV-P
d) I-S, II-Q, III-R ,IV-P
21. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
97. which of the following statements is/r true about datagram subnet?
P: each packet contains the full source and destination addresses.
Q: Two packets b/n source and destination can follow diff. paths.
a) P only
b) Q only
c) Both P and Q
d) Neither P nor Q.
98.A computer on a 6Mbps network is regulated by a token bucket.The token bucket is
filled at a rate of 2Mbps.It is initially filled to a full capacity of 8Mb.How long can the
computer transmit at the full 6Mbps?
a)1.3sec
b)1.6 sec
c)1.9 sec
d)2sec
99.The routing table of a router is shown below
Destination Subnet mask interface
132.81.0.0
132.81.64.0
132.81.68.0
132.81.68.64
255.255.0.0
255.255.224.0
255.255.255.0
255.255.255.224
Eth0
Eth1
Eth2
Eth3
A packet bearing a destination address 132.81.68.132 arrives at router. On which
interface will it be forwarded?
a)Eth0
b)Eth1
c)Eth2
d)Eth3
22. 2:34:34 AM 5/16/2009 DRDO CS PAPER 2008
FOR DRDO SET 2009 ORKUT COMMUNITY
http://www.orkut.co.in/Main#Community.aspx?cmm=87239458
100.which of the following statements is /are True about IP address?
P: IP address 128.128.255.255 is used for broadcasting on class B network.
Q: IP address 127.127.255.255 is used for loopback testing.
A)P only
B)Q only
C)Both P and Q
D)Neither P nor Q.
If any one has doubts about any question then send a mail to aksmails@gmail.com
GOODLUCK TO ALL
AJAY SINGH