This paper describes an adaptation of a polar code decoding technique in favor of the extended Golay code. Based on the bridge provided by a permutation matrix between the code words of these two classes of codes, the Golay code can be decoded by any polar code technique. Contrary to the successive-cancellation list technique which is characterized by a serial estimation of the bits, we propose in this work an adaptation of the simplified successive-cancellation list technique to polar codes equivalent to the Golay code. The simulations have achieved the performance of a maximum likelihood decoding, with the low decoding complexity of polar codes, compared to one of the universal decoders of linear codes most known in the literature.
Improving The Performance of Viterbi Decoder using Window System IJECEIAES
An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
Investigative Compression Of Lossy Images By Enactment Of Lattice Vector Quan...IJERA Editor
In the digital era we live in, efficient representation of data generated by a discrete source and its reliable transmission are unquestionable need. In this work we have focused on source coding taking image as source. Lattice Vector Quantization (LVQ) can be used for source coding as well as for channel coding. (LVQ) with Generator Matrix (GM) and codebook is implemented. When implementation using codebook is done, two codebooks are constructed, one with 256 lattice points that are closest to (0,0,0,0) and another with 256 lattice points that are closest to (1,0,0,0). Energy for both the codes is calculated. When we compare the energy of both the codes we find that codes centered at a non lattice point is lower energy code.
Reliability Level List Based Iterative SISO Decoding Algorithm for Block Turb...TELKOMNIKA JOURNAL
An iterative Reliability Level List (RLL) based soft-input soft-output (SISO) decoding algorithm has been proposed for Block Turbo Codes (BTCs). The algorithm ingeniously adapts the RLL based decoding algorithm for the constituent block codes, which is a soft-input hard-output algorithm. The extrinsic information is calculated using the reliability of these hard-output decisions and is passed as soft-input to the iterative turbo decoding process. RLL based decoding of constituent codes estimate the optimal transmitted codeword through a directed minimal search. The proposed RLL based decoder for the constituent code replaces the Chase-2 based constituent decoder in the conventional SISO scheme. Simulation results show that the proposed algorithm has a clear advantage of performance improvement over conventional Chase-2 based SISO decoding scheme with reduced decoding latency at lower noise levels.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Study of the operational SNR while constructing polar codes IJECEIAES
Channel coding is commonly based on protecting information to be communicated across an unreliable medium, by adding patterns of redundancy into the transmission path. Also referred to as forward error control coding (FECC), the technique is widely used to enable correcting or at least detecting bit errors in digital communication systems. In this paper we study an original FECC known as polar coding which has proven to meet the typical use cases of the next generation mobile standard. This work is motivated by the suitability of polar codes for the new coming wireless era. Hence, we investigate the performance of polar codes in terms of bit error rate (BER) for several codeword lengths and code rates. We first perform a discrete search to find the best operational signal-to-noise ratio (SNR) at two different code rates, while varying the blocklength. We find in our extensive simulations that the BER becomes more sensitive to operational SNR (OSNR) as long as we increase the blocklength and code rate. Finally, we note that increasing blocklength achieves an SNR gain, while increasing code rate changes the OSNR domain. This trade-off sorted out must be taken into consideration while designing polar codes for high-throughput application.
This paper introduces a Simulink model design for a modified fountain code. The code is a new version of the traditional Luby transform (LT) codes.
The design constructs the blocks required for generation of the generator matrix of a limited-degree-hopping-segment Luby transform (LDHS-LT) codes. This code is especially designed for short length data files which have assigned a great interest for wireless sensor networks. It generates the degrees in a predetermined sequence but random generation and partitioned the data file in segments. The data packets selection has been made serialy according to the integer generated from both degree and segment generators. The code is tested using Monte Carlo simulation approach with the conventional code generation using robust soliton distribution (RSD) for degree generation, and the simulation results approve better performance with all testing parameter.
Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Improving The Performance of Viterbi Decoder using Window System IJECEIAES
An efficient Viterbi decoder is introduced in this paper; it is called Viterbi decoder with window system. The simulation results, over Gaussian channels, are performed from rate 1/2, 1/3 and 2/3 joined to TCM encoder with memory in order of 2, 3. These results show that the proposed scheme outperforms the classical Viterbi by a gain of 1 dB. On the other hand, we propose a function called RSCPOLY2TRELLIS, for recursive systematic convolutional (RSC) encoder which creates the trellis structure of a recursive systematic convolutional encoder from the matrix “H”. Moreover, we present a comparison between the decoding algorithms of the TCM encoder like Viterbi soft and hard, and the variants of the MAP decoder known as BCJR or forward-backward algorithm which is very performant in decoding TCM, but depends on the size of the code, the memory, and the CPU requirements of the application.
Investigative Compression Of Lossy Images By Enactment Of Lattice Vector Quan...IJERA Editor
In the digital era we live in, efficient representation of data generated by a discrete source and its reliable transmission are unquestionable need. In this work we have focused on source coding taking image as source. Lattice Vector Quantization (LVQ) can be used for source coding as well as for channel coding. (LVQ) with Generator Matrix (GM) and codebook is implemented. When implementation using codebook is done, two codebooks are constructed, one with 256 lattice points that are closest to (0,0,0,0) and another with 256 lattice points that are closest to (1,0,0,0). Energy for both the codes is calculated. When we compare the energy of both the codes we find that codes centered at a non lattice point is lower energy code.
Reliability Level List Based Iterative SISO Decoding Algorithm for Block Turb...TELKOMNIKA JOURNAL
An iterative Reliability Level List (RLL) based soft-input soft-output (SISO) decoding algorithm has been proposed for Block Turbo Codes (BTCs). The algorithm ingeniously adapts the RLL based decoding algorithm for the constituent block codes, which is a soft-input hard-output algorithm. The extrinsic information is calculated using the reliability of these hard-output decisions and is passed as soft-input to the iterative turbo decoding process. RLL based decoding of constituent codes estimate the optimal transmitted codeword through a directed minimal search. The proposed RLL based decoder for the constituent code replaces the Chase-2 based constituent decoder in the conventional SISO scheme. Simulation results show that the proposed algorithm has a clear advantage of performance improvement over conventional Chase-2 based SISO decoding scheme with reduced decoding latency at lower noise levels.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
Study of the operational SNR while constructing polar codes IJECEIAES
Channel coding is commonly based on protecting information to be communicated across an unreliable medium, by adding patterns of redundancy into the transmission path. Also referred to as forward error control coding (FECC), the technique is widely used to enable correcting or at least detecting bit errors in digital communication systems. In this paper we study an original FECC known as polar coding which has proven to meet the typical use cases of the next generation mobile standard. This work is motivated by the suitability of polar codes for the new coming wireless era. Hence, we investigate the performance of polar codes in terms of bit error rate (BER) for several codeword lengths and code rates. We first perform a discrete search to find the best operational signal-to-noise ratio (SNR) at two different code rates, while varying the blocklength. We find in our extensive simulations that the BER becomes more sensitive to operational SNR (OSNR) as long as we increase the blocklength and code rate. Finally, we note that increasing blocklength achieves an SNR gain, while increasing code rate changes the OSNR domain. This trade-off sorted out must be taken into consideration while designing polar codes for high-throughput application.
This paper introduces a Simulink model design for a modified fountain code. The code is a new version of the traditional Luby transform (LT) codes.
The design constructs the blocks required for generation of the generator matrix of a limited-degree-hopping-segment Luby transform (LDHS-LT) codes. This code is especially designed for short length data files which have assigned a great interest for wireless sensor networks. It generates the degrees in a predetermined sequence but random generation and partitioned the data file in segments. The data packets selection has been made serialy according to the integer generated from both degree and segment generators. The code is tested using Monte Carlo simulation approach with the conventional code generation using robust soliton distribution (RSD) for degree generation, and the simulation results approve better performance with all testing parameter.
Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.
An efficient reconfigurable code rate cooperative low-density parity check co...IJECEIAES
In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz.
Hamming net based Low Complexity Successive Cancellation Polar DecoderRSIS International
This paper aims to implement hybrid based Polar
encoder using the knowledge of mutual information and channel
capacity. Further a Hamming weight successive cancellation
decoder is simulated with QPSK modulation technique in
presence of additive white gaussian noise. The experimentation
performed with the effect of channel polarization has shown that
for 256- bit data stream, 30% channels has zero bit and 49%
channels are with a one bit capacity. The decoding complexity is
reduced to almost half as compared to conventional successive
cancellation decoding algorithm. However, the required SNR of
7 dB is achieved at the targeted BER of 10 -4. The penalty paid is
in terms of training time required at the decoding end.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N VLSICS Design
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
MDCT audio coding with pulse vector quantizersEricsson
This paper describes a novel audio coding algorithm that is a building block in the recently standardized 3GPP EVS codec. The presented scheme operates in the Modified Discrete Cosine Transform (MDCT) domain and deploys a Split-PVQ pulse coding quantizer, a noise-fill, and a gain control optimized for the quantizer’s properties. A complexity analysis in terms of WMOPS is presented to illustrate that the proposed Split-PVQ concept and dynamic range optimized MPVQ-indexing are suitable for real-time audio coding.
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...IOSR Journals
Abstract: In this paper we have designed and implemented(15, k) a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organized into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form up to k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 code word. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 13.3. BCH encoders are conventionally implemented by linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fan out, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. Also a comparative performance based on synthesis & simulation on FPGA is presented. Keywords: BCH, BCH Encoder, FPGA, VHDL, Error Correction, AWGN, LFSR cyclic redundancy checking, fan out .
An Efficient Interpolation-Based Chase BCH Decoderijsrd.com
Error correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. Bose,Ray Chaudhuri, Hocquenghem (BCH)codes are one of the error correcting codes. The BCH decoder consists of four blocks namely syndrome block, chien search block and error correction block. This paper describes a new method for error detection in syndrome and chien search block of BCH decoder. The proposed syndrome block is used to reduce the number of computation by calculating the even number syndromes from the corresponding odd number syndromes.
An Efficient Fault Tolerance System Design for Cmos/Nanodevice Digital MemoriesIJERA Editor
Targeting on the future fault-prone hybrid CMOS/Nanodevice digital memories, this paper present two faulttolerance
design approaches the integrally address the tolerance for defect and transient faults. These two
approaches share several key features, including the use of a group of Bose-Chaudhuri- Hocquenghem (BCH)
codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic
logical-to-physical address mapping. Thus, a new model of BCH decoder is proposed to reduce the area and
simplify the computational scheduling of both syndrome and chien search blocks without parallelism leading to
high throughput.The goal of fault tolerant computing is improve the dependability of systems where
dependability can be defined as the ability of a system to deliver service at an acceptable level of confidence in
either presence or absence falult.ss The results of the simulation and implementation using Xilinx ISE software
and the LCD screen on the FPGA’s Board will be shown at last.
Non-binary codes approach on the performance of short-packet full-duplex tran...IJECEIAES
This paper illustrates the enhancement of the performance of short-packet full-duplex (FD) transmission by taking the approach of non-binary low density parity check (NB-LDPC) codes over higher Galois field. For the purpose of reducing the impacts of self-interference (SI), high order of modulation, complexity, and latency decoder, a blind feedback process composed of channels estimation and decoding algorithm is implemented. In particular, this method uses an iterative process to simultaneously suppress SI component of FD transmission, estimate intended channel, and decode messages. The results indicate that the proposed technique provides a better solution than both the NB-LDPC without feedback and the binary LDPC feedback algorithms. Indeed, it can significantly improve the performance of overall system in two important factors, which are bit-error-rate (BER) and mean square error (MSE), especially in high order of modulation. The suggested algorithm also shows a robustness in reliability and power consumption for both short-packet FD transmissions and high order modulation communications.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
n this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
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Lightweight hamming product code based multiple bit error correction coding s...journalBEEI
In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.
An efficient reconfigurable code rate cooperative low-density parity check co...IJECEIAES
In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz.
Hamming net based Low Complexity Successive Cancellation Polar DecoderRSIS International
This paper aims to implement hybrid based Polar
encoder using the knowledge of mutual information and channel
capacity. Further a Hamming weight successive cancellation
decoder is simulated with QPSK modulation technique in
presence of additive white gaussian noise. The experimentation
performed with the effect of channel polarization has shown that
for 256- bit data stream, 30% channels has zero bit and 49%
channels are with a one bit capacity. The decoding complexity is
reduced to almost half as compared to conventional successive
cancellation decoding algorithm. However, the required SNR of
7 dB is achieved at the targeted BER of 10 -4. The penalty paid is
in terms of training time required at the decoding end.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
Abstract - High speed low power viterbi decoders for trellis code modulation is well known for the delay consumption in underwater communication. In transmission system wireless communication is the transfer of information between two or more points that are not connected by an electrical conductor. WiMAX is the wireless communication standard designed to provide 30 to 40 Mega bits per second data rates. WiMAX as a standards based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. WiMAX can provide at home or mobile internet access across whole cities or countries. The address generation of WiMAX is carried out by interleaver and deinterleaver. Interleaving is used to overcome correlated channel noise such as burst error or fading. The interleaver/deinterleaver rearranges input data such that consecutive data are spaced apart. The interleaved memory is to improve the speed of access to memory. The viterbi technique reduces the bit error rate and delay using wimax.
REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N VLSICS Design
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at 301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
MDCT audio coding with pulse vector quantizersEricsson
This paper describes a novel audio coding algorithm that is a building block in the recently standardized 3GPP EVS codec. The presented scheme operates in the Modified Discrete Cosine Transform (MDCT) domain and deploys a Split-PVQ pulse coding quantizer, a noise-fill, and a gain control optimized for the quantizer’s properties. A complexity analysis in terms of WMOPS is presented to illustrate that the proposed Split-PVQ concept and dynamic range optimized MPVQ-indexing are suitable for real-time audio coding.
Design and Implementation of Encoder for (15, k) Binary BCH Code Using VHDL a...IOSR Journals
Abstract: In this paper we have designed and implemented(15, k) a BCH Encoder on FPGA using VHDL for reliable data transfers in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive polynomial x4+x+1 is organized into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form up to k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 code word. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 13.3. BCH encoders are conventionally implemented by linear feedback shift register architecture. Encoders of long BCH codes may suffer from the effect of large fan out, which may reduce the achievable clock speed. The data rate requirement of optical applications require parallel implementations of the BCH encoders. Also a comparative performance based on synthesis & simulation on FPGA is presented. Keywords: BCH, BCH Encoder, FPGA, VHDL, Error Correction, AWGN, LFSR cyclic redundancy checking, fan out .
An Efficient Interpolation-Based Chase BCH Decoderijsrd.com
Error correction codes are the codes used to correct the errors occurred during the transmission of the data in the unreliable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if some errors occur due to noise in the channel, the data can be correctly received at the destination end. Bose,Ray Chaudhuri, Hocquenghem (BCH)codes are one of the error correcting codes. The BCH decoder consists of four blocks namely syndrome block, chien search block and error correction block. This paper describes a new method for error detection in syndrome and chien search block of BCH decoder. The proposed syndrome block is used to reduce the number of computation by calculating the even number syndromes from the corresponding odd number syndromes.
An Efficient Fault Tolerance System Design for Cmos/Nanodevice Digital MemoriesIJERA Editor
Targeting on the future fault-prone hybrid CMOS/Nanodevice digital memories, this paper present two faulttolerance
design approaches the integrally address the tolerance for defect and transient faults. These two
approaches share several key features, including the use of a group of Bose-Chaudhuri- Hocquenghem (BCH)
codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic
logical-to-physical address mapping. Thus, a new model of BCH decoder is proposed to reduce the area and
simplify the computational scheduling of both syndrome and chien search blocks without parallelism leading to
high throughput.The goal of fault tolerant computing is improve the dependability of systems where
dependability can be defined as the ability of a system to deliver service at an acceptable level of confidence in
either presence or absence falult.ss The results of the simulation and implementation using Xilinx ISE software
and the LCD screen on the FPGA’s Board will be shown at last.
Non-binary codes approach on the performance of short-packet full-duplex tran...IJECEIAES
This paper illustrates the enhancement of the performance of short-packet full-duplex (FD) transmission by taking the approach of non-binary low density parity check (NB-LDPC) codes over higher Galois field. For the purpose of reducing the impacts of self-interference (SI), high order of modulation, complexity, and latency decoder, a blind feedback process composed of channels estimation and decoding algorithm is implemented. In particular, this method uses an iterative process to simultaneously suppress SI component of FD transmission, estimate intended channel, and decode messages. The results indicate that the proposed technique provides a better solution than both the NB-LDPC without feedback and the binary LDPC feedback algorithms. Indeed, it can significantly improve the performance of overall system in two important factors, which are bit-error-rate (BER) and mean square error (MSE), especially in high order of modulation. The suggested algorithm also shows a robustness in reliability and power consumption for both short-packet FD transmissions and high order modulation communications.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the
use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual
and relative performances of the algorithms. Thus there is no performance loss, and sometimes a
significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms
is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system
implementation. In addition, we have found that the processing complexity of the non-statistical algorithms
is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for
the LDPC codes over all of the channels
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
n this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding
algorithms for the three currently most important error-correcting codes: the low-density parity-check
(LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using
an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these
non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the
Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER
performances of the corresponding statistical decoding algorithms for the three codes and channels. In all
cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or
slightly better than that of the statistical algorithms.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Similar to Decoding of the extended Golay code by the simplified successive-cancellation list decoder adapted to multi-kernel polar codes (20)
Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
Design and simulation an optimal enhanced PI controller for congestion avoida...TELKOMNIKA JOURNAL
In this paper, snake optimization algorithm (SOA) is used to find the optimal gains of an enhanced controller for controlling congestion problem in computer networks. M-file and Simulink platform is adopted to evaluate the response of the active queue management (AQM) system, a comparison with two classical controllers is done, all tuned gains of controllers are obtained using SOA method and the fitness function chose to monitor the system performance is the integral time absolute error (ITAE). Transient analysis and robust analysis is used to show the proposed controller performance, two robustness tests are applied to the AQM system, one is done by varying the size of queue value in different period and the other test is done by changing the number of transmission control protocol (TCP) sessions with a value of ± 20% from its original value. The simulation results reflect a stable and robust behavior and best performance is appeared clearly to achieve the desired queue size without any noise or any transmission problems.
Improving the detection of intrusion in vehicular ad-hoc networks with modifi...TELKOMNIKA JOURNAL
Vehicular ad-hoc networks (VANETs) are wireless-equipped vehicles that form networks along the road. The security of this network has been a major challenge. The identity-based cryptosystem (IBC) previously used to secure the networks suffers from membership authentication security features. This paper focuses on improving the detection of intruders in VANETs with a modified identity-based cryptosystem (MIBC). The MIBC is developed using a non-singular elliptic curve with Lagrange interpolation. The public key of vehicles and roadside units on the network are derived from number plates and location identification numbers, respectively. Pseudo-identities are used to mask the real identity of users to preserve their privacy. The membership authentication mechanism ensures that only valid and authenticated members of the network are allowed to join the network. The performance of the MIBC is evaluated using intrusion detection ratio (IDR) and computation time (CT) and then validated with the existing IBC. The result obtained shows that the MIBC recorded an IDR of 99.3% against 94.3% obtained for the existing identity-based cryptosystem (EIBC) for 140 unregistered vehicles attempting to intrude on the network. The MIBC shows lower CT values of 1.17 ms against 1.70 ms for EIBC. The MIBC can be used to improve the security of VANETs.
Conceptual model of internet banking adoption with perceived risk and trust f...TELKOMNIKA JOURNAL
Understanding the primary factors of internet banking (IB) acceptance is critical for both banks and users; nevertheless, our knowledge of the role of users’ perceived risk and trust in IB adoption is limited. As a result, we develop a conceptual model by incorporating perceived risk and trust into the technology acceptance model (TAM) theory toward the IB. The proper research emphasized that the most essential component in explaining IB adoption behavior is behavioral intention to use IB adoption. TAM is helpful for figuring out how elements that affect IB adoption are connected to one another. According to previous literature on IB and the use of such technology in Iraq, one has to choose a theoretical foundation that may justify the acceptance of IB from the customer’s perspective. The conceptual model was therefore constructed using the TAM as a foundation. Furthermore, perceived risk and trust were added to the TAM dimensions as external factors. The key objective of this work was to extend the TAM to construct a conceptual model for IB adoption and to get sufficient theoretical support from the existing literature for the essential elements and their relationships in order to unearth new insights about factors responsible for IB adoption.
Efficient combined fuzzy logic and LMS algorithm for smart antennaTELKOMNIKA JOURNAL
The smart antennas are broadly used in wireless communication. The least mean square (LMS) algorithm is a procedure that is concerned in controlling the smart antenna pattern to accommodate specified requirements such as steering the beam toward the desired signal, in addition to placing the deep nulls in the direction of unwanted signals. The conventional LMS (C-LMS) has some drawbacks like slow convergence speed besides high steady state fluctuation error. To overcome these shortcomings, the present paper adopts an adaptive fuzzy control step size least mean square (FC-LMS) algorithm to adjust its step size. Computer simulation outcomes illustrate that the given model has fast convergence rate as well as low mean square error steady state.
Design and implementation of a LoRa-based system for warning of forest fireTELKOMNIKA JOURNAL
This paper presents the design and implementation of a forest fire monitoring and warning system based on long range (LoRa) technology, a novel ultra-low power consumption and long-range wireless communication technology for remote sensing applications. The proposed system includes a wireless sensor network that records environmental parameters such as temperature, humidity, wind speed, and carbon dioxide (CO2) concentration in the air, as well as taking infrared photos.The data collected at each sensor node will be transmitted to the gateway via LoRa wireless transmission. Data will be collected, processed, and uploaded to a cloud database at the gateway. An Android smartphone application that allows anyone to easily view the recorded data has been developed. When a fire is detected, the system will sound a siren and send a warning message to the responsible personnel, instructing them to take appropriate action. Experiments in Tram Chim Park, Vietnam, have been conducted to verify and evaluate the operation of the system.
Wavelet-based sensing technique in cognitive radio networkTELKOMNIKA JOURNAL
Cognitive radio is a smart radio that can change its transmitter parameter based on interaction with the environment in which it operates. The demand for frequency spectrum is growing due to a big data issue as many Internet of Things (IoT) devices are in the network. Based on previous research, most frequency spectrum was used, but some spectrums were not used, called spectrum hole. Energy detection is one of the spectrum sensing methods that has been frequently used since it is easy to use and does not require license users to have any prior signal understanding. But this technique is incapable of detecting at low signal-to-noise ratio (SNR) levels. Therefore, the wavelet-based sensing is proposed to overcome this issue and detect spectrum holes. The main objective of this work is to evaluate the performance of wavelet-based sensing and compare it with the energy detection technique. The findings show that the percentage of detection in wavelet-based sensing is 83% higher than energy detection performance. This result indicates that the wavelet-based sensing has higher precision in detection and the interference towards primary user can be decreased.
A novel compact dual-band bandstop filter with enhanced rejection bandsTELKOMNIKA JOURNAL
In this paper, we present the design of a new wide dual-band bandstop filter (DBBSF) using nonuniform transmission lines. The method used to design this filter is to replace conventional uniform transmission lines with nonuniform lines governed by a truncated Fourier series. Based on how impedances are profiled in the proposed DBBSF structure, the fractional bandwidths of the two 10 dB-down rejection bands are widened to 39.72% and 52.63%, respectively, and the physical size has been reduced compared to that of the filter with the uniform transmission lines. The results of the electromagnetic (EM) simulation support the obtained analytical response and show an improved frequency behavior.
Deep learning approach to DDoS attack with imbalanced data at the application...TELKOMNIKA JOURNAL
A distributed denial of service (DDoS) attack is where one or more computers attack or target a server computer, by flooding internet traffic to the server. As a result, the server cannot be accessed by legitimate users. A result of this attack causes enormous losses for a company because it can reduce the level of user trust, and reduce the company’s reputation to lose customers due to downtime. One of the services at the application layer that can be accessed by users is a web-based lightweight directory access protocol (LDAP) service that can provide safe and easy services to access directory applications. We used a deep learning approach to detect DDoS attacks on the CICDDoS 2019 dataset on a complex computer network at the application layer to get fast and accurate results for dealing with unbalanced data. Based on the results obtained, it is observed that DDoS attack detection using a deep learning approach on imbalanced data performs better when implemented using synthetic minority oversampling technique (SMOTE) method for binary classes. On the other hand, the proposed deep learning approach performs better for detecting DDoS attacks in multiclass when implemented using the adaptive synthetic (ADASYN) method.
The appearance of uncertainties and disturbances often effects the characteristics of either linear or nonlinear systems. Plus, the stabilization process may be deteriorated thus incurring a catastrophic effect to the system performance. As such, this manuscript addresses the concept of matching condition for the systems that are suffering from miss-match uncertainties and exogeneous disturbances. The perturbation towards the system at hand is assumed to be known and unbounded. To reach this outcome, uncertainties and their classifications are reviewed thoroughly. The structural matching condition is proposed and tabulated in the proposition 1. Two types of mathematical expressions are presented to distinguish the system with matched uncertainty and the system with miss-matched uncertainty. Lastly, two-dimensional numerical expressions are provided to practice the proposed proposition. The outcome shows that matching condition has the ability to change the system to a design-friendly model for asymptotic stabilization.
Implementation of FinFET technology based low power 4×4 Wallace tree multipli...TELKOMNIKA JOURNAL
Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.
Evaluation of the weighted-overlap add model with massive MIMO in a 5G systemTELKOMNIKA JOURNAL
The flaw in 5G orthogonal frequency division multiplexing (OFDM) becomes apparent in high-speed situations. Because the doppler effect causes frequency shifts, the orthogonality of OFDM subcarriers is broken, lowering both their bit error rate (BER) and throughput output. As part of this research, we use a novel design that combines massive multiple input multiple output (MIMO) and weighted overlap and add (WOLA) to improve the performance of 5G systems. To determine which design is superior, throughput and BER are calculated for both the proposed design and OFDM. The results of the improved system show a massive improvement in performance ver the conventional system and significant improvements with massive MIMO, including the best throughput and BER. When compared to conventional systems, the improved system has a throughput that is around 22% higher and the best performance in terms of BER, but it still has around 25% less error than OFDM.
Reflector antenna design in different frequencies using frequency selective s...TELKOMNIKA JOURNAL
In this study, it is aimed to obtain two different asymmetric radiation patterns obtained from antennas in the shape of the cross-section of a parabolic reflector (fan blade type antennas) and antennas with cosecant-square radiation characteristics at two different frequencies from a single antenna. For this purpose, firstly, a fan blade type antenna design will be made, and then the reflective surface of this antenna will be completed to the shape of the reflective surface of the antenna with the cosecant-square radiation characteristic with the frequency selective surface designed to provide the characteristics suitable for the purpose. The frequency selective surface designed and it provides the perfect transmission as possible at 4 GHz operating frequency, while it will act as a band-quenching filter for electromagnetic waves at 5 GHz operating frequency and will be a reflective surface. Thanks to this frequency selective surface to be used as a reflective surface in the antenna, a fan blade type radiation characteristic at 4 GHz operating frequency will be obtained, while a cosecant-square radiation characteristic at 5 GHz operating frequency will be obtained.
Reagentless iron detection in water based on unclad fiber optical sensorTELKOMNIKA JOURNAL
A simple and low-cost fiber based optical sensor for iron detection is demonstrated in this paper. The sensor head consist of an unclad optical fiber with the unclad length of 1 cm and it has a straight structure. Results obtained shows a linear relationship between the output light intensity and iron concentration, illustrating the functionality of this iron optical sensor. Based on the experimental results, the sensitivity and linearity are achieved at 0.0328/ppm and 0.9824 respectively at the wavelength of 690 nm. With the same wavelength, other performance parameters are also studied. Resolution and limit of detection (LOD) are found to be 0.3049 ppm and 0.0755 ppm correspondingly. This iron sensor is advantageous in that it does not require any reagent for detection, enabling it to be simpler and cost-effective in the implementation of the iron sensing.
Impact of CuS counter electrode calcination temperature on quantum dot sensit...TELKOMNIKA JOURNAL
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
A progressive learning for structural tolerance online sequential extreme lea...TELKOMNIKA JOURNAL
This article discusses the progressive learning for structural tolerance online sequential extreme learning machine (PSTOS-ELM). PSTOS-ELM can save robust accuracy while updating the new data and the new class data on the online training situation. The robustness accuracy arises from using the householder block exact QR decomposition recursive least squares (HBQRD-RLS) of the PSTOS-ELM. This method is suitable for applications that have data streaming and often have new class data. Our experiment compares the PSTOS-ELM accuracy and accuracy robustness while data is updating with the batch-extreme learning machine (ELM) and structural tolerance online sequential extreme learning machine (STOS-ELM) that both must retrain the data in a new class data case. The experimental results show that PSTOS-ELM has accuracy and robustness comparable to ELM and STOS-ELM while also can update new class data immediately.
Electroencephalography-based brain-computer interface using neural networksTELKOMNIKA JOURNAL
This study aimed to develop a brain-computer interface that can control an electric wheelchair using electroencephalography (EEG) signals. First, we used the Mind Wave Mobile 2 device to capture raw EEG signals from the surface of the scalp. The signals were transformed into the frequency domain using fast Fourier transform (FFT) and filtered to monitor changes in attention and relaxation. Next, we performed time and frequency domain analyses to identify features for five eye gestures: opened, closed, blink per second, double blink, and lookup. The base state was the opened-eyes gesture, and we compared the features of the remaining four action gestures to the base state to identify potential gestures. We then built a multilayer neural network to classify these features into five signals that control the wheelchair’s movement. Finally, we designed an experimental wheelchair system to test the effectiveness of the proposed approach. The results demonstrate that the EEG classification was highly accurate and computationally efficient. Moreover, the average performance of the brain-controlled wheelchair system was over 75% across different individuals, which suggests the feasibility of this approach.
Adaptive segmentation algorithm based on level set model in medical imagingTELKOMNIKA JOURNAL
For image segmentation, level set models are frequently employed. It offer best solution to overcome the main limitations of deformable parametric models. However, the challenge when applying those models in medical images stills deal with removing blurs in image edges which directly affects the edge indicator function, leads to not adaptively segmenting images and causes a wrong analysis of pathologies wich prevents to conclude a correct diagnosis. To overcome such issues, an effective process is suggested by simultaneously modelling and solving systems’ two-dimensional partial differential equations (PDE). The first PDE equation allows restoration using Euler’s equation similar to an anisotropic smoothing based on a regularized Perona and Malik filter that eliminates noise while preserving edge information in accordance with detected contours in the second equation that segments the image based on the first equation solutions. This approach allows developing a new algorithm which overcome the studied model drawbacks. Results of the proposed method give clear segments that can be applied to any application. Experiments on many medical images in particular blurry images with high information losses, demonstrate that the developed approach produces superior segmentation results in terms of quantity and quality compared to other models already presented in previeous works.
Automatic channel selection using shuffled frog leaping algorithm for EEG bas...TELKOMNIKA JOURNAL
Drug addiction is a complex neurobiological disorder that necessitates comprehensive treatment of both the body and mind. It is categorized as a brain disorder due to its impact on the brain. Various methods such as electroencephalography (EEG), functional magnetic resonance imaging (FMRI), and magnetoencephalography (MEG) can capture brain activities and structures. EEG signals provide valuable insights into neurological disorders, including drug addiction. Accurate classification of drug addiction from EEG signals relies on appropriate features and channel selection. Choosing the right EEG channels is essential to reduce computational costs and mitigate the risk of overfitting associated with using all available channels. To address the challenge of optimal channel selection in addiction detection from EEG signals, this work employs the shuffled frog leaping algorithm (SFLA). SFLA facilitates the selection of appropriate channels, leading to improved accuracy. Wavelet features extracted from the selected input channel signals are then analyzed using various machine learning classifiers to detect addiction. Experimental results indicate that after selecting features from the appropriate channels, classification accuracy significantly increased across all classifiers. Particularly, the multi-layer perceptron (MLP) classifier combined with SFLA demonstrated a remarkable accuracy improvement of 15.78% while reducing time complexity.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
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Decoding of the extended Golay code by the simplified successive-cancellation list decoder adapted to multi-kernel polar codes
1. TELKOMNIKA Telecommunication Computing Electronics and Control
Vol. 21, No. 3, June 2023, pp. 477~485
ISSN: 1693-6930, DOI: 10.12928/TELKOMNIKA.v21i3.23360 477
Journal homepage: http://telkomnika.uad.ac.id
Decoding of the extended Golay code by the simplified
successive-cancellation list decoder adapted to multi-kernel
polar codes
Driss Khebbou1
, Idriss Chana2
, Hussain Ben-Azza1
1
Ecole Nationale Supérieure d’Arts et Métiers, Moulay Ismail University of Meknès, Meknès, Morocco
2
Ecole Supérieure de Technologie, Moulay Ismail University of Meknès, Meknès, Morocco
Article Info ABSTRACT
Article history:
Received Feb 15, 2022
Revised Nov 10, 2022
Accepted Nov 26, 2022
This paper describes an adaptation of a polar code decoding technique in
favor of the extended Golay code. Based on the bridge provided by a
permutation matrix between the code words of these two classes of codes,
the Golay code can be decoded by any polar code technique. Contrary to the
successive-cancellation list technique which is characterized by a serial
estimation of the bits, we propose in this work an adaptation of the
simplified successive-cancellation list technique to polar codes equivalent to
the Golay code. The simulations have achieved the performance of a
maximum likelihood decoding, with the low decoding complexity of polar
codes, compared to one of the universal decoders of linear codes most
known in the literature.
Keywords:
Binary linear block code
Coding theory
Error-correcting code
Golay code
Multi-kernel polar code This is an open access article under the CC BY-SA license.
Corresponding Author:
Driss Khebbou
Ecole Nationale Supérieure d’Arts et Métiers, Moulay Ismail University of Meknès
Meknès, Morocco
Email: khebbou.driss@gmail.com
1. INTRODUCTION
One of the pioneers of existing error correction theory is the Golay code, which first appeared in the
late 1940s [1]. It has a multitude of uses in communication, storage, and imaging systems [2]–[4]. In literature,
a multitude of algebraic [5] and soft decision decoders [6]–[8] have been proposed. Golay code has gotten a
lot of attention since its discovery because of its attractive structure and practical characteristics, and several
construction methods have been presented over the years [9].
On the other hand, a class of error-correcting codes was discovered in 2009 by Arikan [10] called polar
codes, allowing to reach, in a proven way, the channel capacity as it was described by Shannon [11] in his
founder article. In addition, these codes have low encoding/decoding complexity using successive-cancellation
(SC) decoding technique, which has made them a competitive coding scheme in modern wireless
communication systems. Their constructions are inspired by the phenomenon of polarization using the Arikan
kernel 𝑇2 = [
1 0
1 1
], which consists in transforming the channels into two categories: extremely unreliable
channels used to forward the redundant part frozen at 0 and extremly reliable channels used to forward
information. Their construction has been the source of inspiration for new construction of good binary linear
codes [12], [13].
To improve binary linear block codes decoding by utilizing low complexity polar code decoding
algorithms, some works in the literature have focused on the bridge between linear codes and the structure of polar
codes. In Lin et al. [14] and Khebbou et al. [15] have proposed a transformation of some binary linear block codes,
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478
namely extended Bose, Ray-Chaudhuri and Hocquenghem (EBCH), low density parity check (LDPC), and
Golay codes, into polar codes with dynamic frozen bits (PCDF) [16], [17] for decoding them by the
successive-cancellation list (SCL) technique, but the latter is hampered by SC decoding’s serial structure, i.e.,
the estimation of a bit depends on the estimation of the bits that precede it. To remedy this problem,
an adaptation of the simplified-SCL technique to PCDF equivalent to EBCH and LDPC codes has been
proposed in [18], but the proposed adaptation is limited to binary linear block codes whose length is
𝑁 = 2𝑚
where 𝑚 is positive integer. In this work, to validate the simplified-SCL technique for binary linear
codes of arbitrary length, an adaptation of the simplified-SCL decoding technique to the benefit of the
extended [24,12,8] Golay code whose length 𝑁 ≠ 2𝑚
, by transforming it into a polar code with frozen
dynamic bits based on multi-kernels.
The rest of this paper is structured as: section 2 introduces the preliminary concepts of this work.
In section 3, a description of the proposed decoding method. Before concluding, in section 4 simulation and
an interpretation of the results obtained using the method described in section 3 are presented.
2. PRELIMINARIES
2.1. Golay code
Golay initially introduced the Golay code as [23,12,7] code, which is a perfect code with length 23,
dimension 𝑘 = 12, and minimum distance 𝑑𝑚𝑖𝑛 = 7. By extending the code, a [24,12,8] quasi-perfect self-dual
binary linear code (extended Golay code) will be obtained; it encodes 12 bits of information in a 24-bit codeword.
In Berlekamp [19], it has been revealed that the Golay code is a quadratic residue code in addition to being a cyclic
Bose-Chaudhuri-Hocquenghem (BCH) code. By definition of a BCH code, we have the inequality 2𝑡 + 1 ≤ 𝑡,
where 𝑡 is the number of altered symbols in a codeword. So that any error of three bits can be rectified.
2.2. Polar code
The notation 𝛲(𝑁, 𝐾, 𝐹) denotes a polar code with length 2𝑛
where 𝑛 ≥ 1, dimension 𝐾 and a set of
frozen bits 𝐹. The elements of 𝐹 represent the positions of the 𝑁 − 𝐾 less reliable channels, and the remaining
𝐾 bits comprise the more reliable bit channels. When the positions of the frozen bits are fixed to 0, and the
source information bits are organized in the remaining positions, to form the source vector 𝑢. The source
codeword 𝑥 is obtained via the encoding process applied on 𝑢 by: 𝑥 = 𝑢 ⋅ 𝐺𝑝, so that 𝐺𝑝 is the kronecker
product of order 𝑙𝑜𝑔2(𝑁) of the Arikan kernel, as a generator matrix of 𝛲.
(a) (b)
Figure 1. Decoding tree of (8,4, {0,1,2,4}) polar code: (a) decoding tree and (b) binary variable exchanging
between nodes
The SC approach, which can be described as a binary tree, as the first polar decoding algorithm
developed. Figure 1(a) depicts the binary tree of the (8,4, {0,1,2,4}) polar code, whereas Figure 1(b) depicts
the different variables exchanged between nodes. At each node of a stage 𝑑, the number of bits processed by
each node is 𝑁𝑑 = 2𝑁−𝑑−1
i.e., let’s use 𝛼 = [𝛼1, 𝛼2, … , 𝛼𝑁𝑑−1], by traversing the tree in the order indicated
in the Figure 1(b), 𝛼𝑙
and 𝛼𝑟
are obtained by the functions:
𝛼 ⥂𝑖
𝑙
= 𝑠𝑖𝑔𝑛(𝛼𝑖) ⋅ 𝑠𝑖𝑔𝑛(𝛼
𝑖+
𝑁𝑑
2
) ⋅ 𝑚𝑖𝑛( |𝛼𝑖|, |𝛼
𝑖+
𝑁𝑑
2
|) (1)
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𝛼 ⥂𝑖
𝑟
= (1 − 2𝛽 ⥂𝑖
𝑙
) ⋅ 𝛼𝑖 + 𝛼
𝑖+
𝑁𝑑
2
(2)
And at the leaf node, 𝛽𝑙
and 𝛽𝑟
are obtained by applying the binary qualification function ℎ (3):
𝛽𝑣
𝑙
= ℎ(𝛼𝑣
𝑙
) = {0 𝑖𝑓 𝛼𝑣
𝑙
≥ 0 𝑜𝑟 𝑖𝑠 𝑓𝑟𝑜𝑧𝑒𝑛
1 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
𝑎𝑛𝑑 𝛽𝑣
𝑟
= ℎ(𝛼𝑣
𝑟
) = {
0 𝑖𝑓 𝛼𝑣
𝑟
≥ 0 𝑜𝑟 𝑖𝑠 𝑓𝑟𝑜𝑧𝑒𝑛
1 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
(3)
The SC decoder can demonstrably reach a channel when 𝑁 → ∞. However, the error correction
performance is poor for small lengths when compared to existing codes like Turbo codes and LDPC codes.
The successive-cancellation list (SCL) decoder comes into the picture at this point [20]. So instead of making
a hard decision by (3), the key concept is to make a probabilistic estimate for each possibility, by considering
both 1 and 0, each one with a certain probability metric 𝑃𝑀𝑖
calculated by:
𝑃𝑀𝑖
= {
𝑃𝑀𝑖−1
𝑖𝑓 𝛽 = ℎ(𝛼𝑖)
𝑃𝑀𝑖−1
+ |𝛼𝑖| 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
(4)
At any leaf node, the number of possibilities is limited by list size 𝐿, by pruning the list each time to consider
the best 𝐿 possibilities.
2.3. Simplified-SCL decoding for polar codes
Despite their low complexity, the SC and SCL decoders are characterized by their serial nature.
In other words, a bit’s decoding is dependent on the decoding of the bits before it. Thus, at each instant, a bit
can be decoded. To remedy these problems, a simplification of this technique simplified-SCL has been
proposed in [21], to break the serial nature for some special nodes on the one hand, and to estimate all the
leaf bits of the special node at one time on the other hand. These special nodes are described in the Figure 2.
Figure 2. Labelled special nodes in binary tree for (8,4) polar code
a) Rate-0 node: it is the root node of a subtree whose leaf nodes are entirely frozen bit nodes as illustrated
in Figure 2. It is not necessary to go to the leaf node for such types of nodes, and the appropriate bits
can be set to 0.
b) Rate-1 node: it is the root node of a subtree whose leaf nodes are entirely information bit nodes as
illustrated in Figure 2. Because no frozen bit nodes are providing prior information, traversing subtree
yields no additional information. Hence it is sufficient to estimate the leaf bits at the current node.
c) Repetition (REP) node: it is the root node of a subtree, with all leaf nodes, are frozen except the last
node which is an information bit node as illustrated in Figure 2.
d) Single parity check (SPC) node: the root node of a subtree whose leaf nodes are all information bit
nodes except the first, which is a frozen bit node corresponds to the SPC node as illustrated in Figure 2.
When encountering one of these types of special nodes, an estimation of all leaf nodes is performed,
without having to traverse the subtree in the special node which is root. The formulas for estimating the
different variables mentioned in Figure 1 at each special node are presented in [21], as well as the formula for
updating the the path metrics (PM) metrics. The simplified-SCL decoder significantly reduces latency and
complexity while achieving the error correcting performance of a SCL.
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2.4. Multi-kernel polar code
Gabry et al. [22] develops a method for constructing polar codes with arbitrary lengths 𝑁 ≠ 2𝑛
.
Instead of using the Arikan kernel to generate the generator matrix, the authors recommended polar codes based
on a multi-kernel construction. I.e.,: 𝐺𝑝 = 𝑇𝑛1
⊗ 𝑇𝑛2
⊗ … ⊗ 𝑇𝑛𝑑
is the generator matrix of multi-kernel polar
code and its length is 𝑁 = 𝑛1 × 𝑛2 × … × 𝑛𝑑.
(a)
(b)
Figure 3. Decoding tree of (12,6) multi-kernel polar code: (a) decoding tree and (b) binary variable
exchanging between nodes of the ternary kernel
As a regular polar code, the SC decoding technique, adapted to multi-kernel polar code (12,6) is
illustrated in the Figure 3(a) its generator matrix is 𝐺𝑝 = 𝑇2 ⊗ 𝑇3 ⊗ 𝑇2, based on the Arikan kernel 𝑇2 and
the ternary kernel 𝑇3 (5).
𝑇2 = [
1 0
1 1
] ; 𝑇3 = [
1 1 0
1 0 1
1 1 1
] (5)
The decoding of the bits corresponding to the Arikan kernel 𝑇2 is carried out, in the same way, described
previously. Then for the ternary kernel 𝑇3, the decoding is carried out in the order mentioned in Figure 3(b).
𝛼 ⥂𝑖
𝑙
= 𝑠𝑖𝑔𝑛(𝛼𝑖) ⋅ 𝑠𝑖𝑔𝑛(𝛼
𝑖+
𝑁𝑑
3
) ⋅ 𝑠𝑖𝑔𝑛(𝛼
𝑖+
2𝑁𝑑
3
) ⋅ 𝑚𝑖𝑛( |𝛼𝑖|, |𝛼
𝑖+
𝑁𝑑
3
| , |𝛼
𝑖+
2𝑁𝑑
3
|) (6)
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𝛼 ⥂𝑖
𝑐
= (1 − 2𝛽 ⥂𝑖
𝑙
) ⋅ 𝛼𝑖 + 𝑠𝑖𝑔𝑛(𝛼
𝑖+
𝑁𝑑
3
) ⋅ 𝑠𝑖𝑔𝑛(𝛼
𝑖+
2𝑁𝑑
3
) ⋅ 𝑚𝑖𝑛( |𝛼
𝑖+
𝑁𝑑
3
| , |𝛼
𝑖+
2𝑁𝑑
3
|) (7)
𝛼 ⥂𝑖
𝑟
= (1 − 2𝛽 ⥂𝑖
𝑙
) ⋅ 𝛼
𝑖+
𝑁𝑑
3
+ (1 − 2𝛽 ⥂𝑖
𝑙
⊕ 𝛽𝑖
𝑐
) ⋅ 𝛼
𝑖+
2𝑁𝑑
3
(8)
For 𝛽𝑙
, 𝛽𝑐
and 𝛽𝑟
, the (3) is used to calculate their values, and the value of 𝛽 returned to the parent node is
obtained (9).
𝛽𝑖 = [𝛽𝑖
𝑙
⊕ 𝛽𝑖
𝑐
, 𝛽𝑖
𝑙
⊕ 𝛽𝑖
𝑟
, 𝛽𝑖
𝑙
⊕ 𝛽𝑖
𝑐
⊕ 𝛽𝑖
𝑟
] (9)
3. ADAPTED SIMPLIFIED-SCL DECODING FOR EXTENDED GOLAY CODE
Lin et al. [14] and Khebbou et al. [18], was the begining of the decoding of binary linear block
codes by polar code decoding techniques. The idea is to use a permutation matrix 𝜋 to ensure a mapping
between the codewords of a polar code and those of a binary linear block code. The polar codes obtained
after permutation are PCDF. These were the first to be introduced into the literature as a solution to the
problem of short minimum Hamming distance in short length regimes. As opposed to a regular polar code,
some positions of the frozen bits are not fixed at 0 for PCDF, their values are obtained by linear functions of
the information bits which precede them. In [16], an example is described using an extended BCH code.
3.1. Golay transformation to polar code
The transformation proposed in [14] applied on the extended Golay code is used in this work,
it consists in identifying the permutation matrix 𝜋 that optimizes the Bhattacharyya parameter [23], [24],
which allows to classify the sets information bits and of frozen bits. The following notations are used:
a) 𝑇2 and 𝑇3: the kernels mentioned in (5).
b) 𝐺𝑝: generator matrix of polar code based on multi-kernel with 𝑁 = 24 obtained by 𝐺𝑝 = 𝑇3 ⊗ 𝑇2 ⊗ 𝑇2 ⊗ 𝑇2.
c) 𝐺𝐺𝑜𝑙𝑎𝑦: generator matrix of extended [24,12,8] Golay code.
d) 𝐻𝐺𝑜𝑙𝑎𝑦: parity check matrix of extended [24,12,8] Golay code.
e) 𝐸: elimination matrix which ensures the transformation into a reduced row echelon form.
f) 𝐸′
: invertible elimination matrix which ensures the transformation into a backward reduced row echelon
form.
The deduction of the polar code with frozen dynamic bits, equivalent to the Golay code can be done in two
ways. The first one, by using 𝐺𝐺𝑜𝑙𝑎𝑦 of the extended Golay code using (10).
𝑅 = 𝐸 ⋅ 𝐺𝐺𝑜𝑙𝑎𝑦 ⋅ 𝜋−1
⋅ 𝐺𝑝
−1
(10)
The set of the statically frozen bits are represented by indexes of the columns of 𝑅 with values of 0 (their values
are set to 0), the set of the information bits are represented by the columns of 𝑅 with a single value of 1, and the
remaining columns of 𝑅 are for dynamic frozen bits (their values are linear functions of the information bits).
The second one, by using 𝐻𝐺𝑜𝑙𝑎𝑦 of the extended Golay code using (11).
𝑅′ = 𝐺𝑝 ⋅ 𝜋 ⋅ 𝐻𝐺𝑜𝑙𝑎𝑦 ⋅ 𝐸′ (11)
The position of dynamic frozen bits in 𝑅’ is determined by the row index of the last non-zero
components of multiple 1 columns, while the zero frozen bits correspond to the column index of non-zero
components of single 1 columns of 𝑅′
, and the remainders are information bits. In this work, we will
transform the extended Golay code using the second way. To do this, let’s take the matrices.
The matrix 𝐻𝐺𝑜𝑙𝑎𝑦 is part of the (12), so 𝑢. 𝑅′ = 0 by definition of parity check matrix. So by
observing the result 𝑅′, we can notice that the indices of the columns {4, 5, 6, 7, 8, 9, 10, 11, 12} are static
frozen positions. The indices of the columns {1,2,3} have multiple 1 must also satisfy 𝑢. 𝑅′ = 0 and they
represent dynamic frozen positions, whose system below allows to define their values according to the
information bits. The remaining positions are information bits:
{
𝑢22 = 𝑢17 + 𝑢18
𝑢21 = 𝑢18
𝑢20 = 𝑢17 + 𝑢18 + 𝑢19
(12)
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And 𝑃𝑀 update for the information bits is performed (16):
𝑃𝑀𝑙 = 𝑃𝑀𝑙 + 𝑠𝑖𝑔𝑛(𝛼𝑖) ⋅ 𝛼𝑖 − (1 − 2𝛽𝑖) ⋅ 𝛼𝑖 (16)
For the parity check bit, it is updated (17):
𝑃𝑀𝑙 = {
𝑃𝑀𝑙 + |𝛼𝑖| 𝑖𝑓 𝛽𝑖 = ℎ(𝛼𝑖)
𝑃𝑀𝑙 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
(17)
Figure 4. Adapted simplified successive-cancellation list decoding tree for polar code equivalent to extended
Golay code [24,12,8] with dynamic frozen bits based on multi-kernel
4. RESULTS AND INTERPRETATIONS
To compare the technique proposed in this work with existing techniques in the literature, this
section illustrates the decoding of the Golay code by three decoding methods, i.e., ordered statistics decoding
(OSD), maximum likelihood decoding (MLD), and the simplified-SCL adapted to multi-kernel polar decoder
proposed in this paper. Although MLD of forwarding error correction codes is known to be the most
accurate, it is rarely employed in practice because it is too difficult to implement efficiently, and MLD of
arbitrary linear codes was established as an NP-hard problem [25]. The OSD is a decoder that was proposed
in 1995 as an approximation to the MLD for linear block codes in order to reduce decoding complexity to
𝑂(𝑛𝑘2
+ 2𝑟
𝑛𝑘), with 𝑟 is the order used for OSD [26]. Figure 5 is a simulation of frame-error rate (FER) for
the extended Golay code over the additive white gaussian noise (AWGN) channel, using three techniques.
Although both the adapted simplified-SCL with list size 𝐿 = 64 and the first-order OSD achieve the
performance of an MLD, but the OSD requires additional effort to control its decoding flow based on the
results of sorting symbol reliabilities, compared to the simplified-SCL complexity. Since the proposed
technique is a derivative of SC, its decoding complexity is 𝒪(𝐿𝑁𝑙𝑜𝑔(𝑁)), which is a logarithmic complexity as
opposed to the OSD having an exponential complexity 𝒪(𝑁𝐾2
+ 2𝑟
𝑁𝐾). Note that order 𝑟 = 1 represents the
order that allows achieving the saturation of an OSD. In other words, whatever the chosen order, the performances
will remain the same.
Lin et al. [14] the decoding of binary linear block codes is treated by the SCL method, which
consists in traversing the whole decoding tree. But it is characterized by its serial nature and the estimation of
each bit is done based on the bit that precedes it. This work is the continuation of [18] which is limited to the
adaptation of the simplified-SCL to codes of length is 𝑁 = 2𝑚
where 𝑚 positive integer, in order to
generalize the simplified-SCL for PCDF based on multi-kernel, to take advantage of a binary linear block
codes whose size 𝑁 ≠ 2𝑚
.
By definition, the construction of polar codes is done explicitly; i.e., the code of size 𝑁 is obtained
starting from a code of size 𝑁/2. Thus each sub-tree of such polar code is also a polar code. For the multi-kernel
polar code equivalent to the extended Golay code proposed in this work, we can notice from Figure 4 that the
technique of decoding technique proposed in this paper, makes it possible to reduce the time steps and
latency by those of 5 polar codes of size 𝑁 = 4. As illustrated in [27, Table 1], the time steps required for
decoding an SPC node is (𝑁𝑣 + 1) for the SCL. However for the same node, the proposed technique in this
work require only (𝑁𝑣 − 2 log(𝑁𝑣) − 2). As well as for the REP node, the time steps required for decoding is
(2𝑁𝑣 − 1) versus 2 times steps for the proposed simplified-SCL in this work.
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Figure 5. Frame-error rate for (24,12) extended Golay code
5. CONCLUSION
In this work, a less complex Golay code decoding technique has been shown compared to existing
methods. It implements the simplified successive-cancellation list decoder adapted to multi-kernel polar code
with frozen dynamic bits. With an appropriate selection of the permutation matrix, these algorithms can
provide a maximum likelihood decoding for [24,12,8] extended Golay code, with a minimization of
complexity and latency, by puncturing the tree traverse of the SCL principle. The MLD is considered as the
most powerful decoding method but it is considered as an NP-hard problem, we compared the method
described in this work with OSD, one of the universal decoder for linear codes known by performances close
to those of MLD, but it has an exponential complexity. The method that we proposed is characterized by a
logarithmic complexity that allows to reach the same performances of OSD. The constraint of the definition
of the most optimal permutation matrix 𝜋 for an eventual binary linear block code remains a direction of
future reflections, since currently the identification of this matrix is done by a random search between the 𝑁!
possibilities. For that, the use of evolutionary algorithms as genetic algorithms can be an alternative to the
direct search.
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BIOGRAPHIES OF AUTHORS
Driss Khebbou He got his engineer degree in Software and Computer Systems
at the Faculty of Science and Technology of Tangier, Abdelmalek Essaâdi University,
Morocco in 2014. He is an engineer in information systems since 2015. Currently, he is
working on his Ph.D at the ENSAM- Ecole Nationale des Arts et Métiers, Moulay Ismail
University of Meknès, Morocco, in the computer engineering department. He can be
contacted at email: khebbou.driss@gmail.com.
Idriss Chana Idriss Chana received the Ph.D. degree from Mohamed V
University of Rabat, Morocco in 2013. He is currently an Associate Professor at Moulay
Ismail University of Meknès, Morocco. His research interests include information and
communication technologies and Artificial Intelligence. A large part of his research projects
are related to Error correcting codes and Turbo codes. Idriss Chana has published more than
30 papers in major journals and conferences in Information Theory and Articial Intelligence.
He can be contacted at email: idrisschana@gmail.com.
Hussain Ben-Azza is a professor at ENSAM- Ecole Nationale des Arts et
Métiers, Meknes, Morocco, attached to Department of Industrial and Production Engineering,
Moulay Ismail University of Meknès. He obtained his Ph.D. degree in mathematics and
computer science in 1995 from Claude Bernard University Lyon 1, France. His research
interests include coding theory, cryptography, wireless communications, but also applications
of optimization techniques to industrial engineering. He can be contacted at email:
hbenazza@yahoo.com.