David Bernard is a French national with over 15 years of experience in ESD protection development and library design at Atmel. He has led projects developing IO libraries and defining ESD strategies. His expertise includes defining ESD test structures, analyzing TLP results, and implementing ESD protection at the device, cell, library, and chip levels. He also has experience developing standard cell and IO libraries, defining compaction and generation rules. Bernard holds a PhD in microelectronics and has published several papers in the field of ESD protection and interconnect modeling.

1. David BERNARD – Resume
Nationality: French
Date of Birth: November 10th, 1972
Marital Status: conjugal relationship, no children
Address: 30, route d’Eguilles – Villa L’Amadour
13090 Aix-En-Provence
Email: bernarddavid4699@neuf.fr
Management, Technical Expertise, Library Design
PROFILE
ESD protection development and full chip ESD strategy definition/implementation
Standard Cell and IOs Libraries development
Profile 2008 – On going
- Project Leader (IOs Library and ESD strategy) – ATMEL, Central Engineering Team –
Rousset (France)
2005 – 2008
- Senior Designer (IOs Library and ESD strategy) – ATMEL, Central Engineering Team –
Rousset (France)
2001 – 2005
- Designers (IOs and Standard Cells Library) – ATMEL, Library & Design Tools
Department - Rousset (France)
BACKGROUND
ESD Device Level
- Definition and implementation of ESD Test Structures
Field - Collaboration with T.D. for dedicated devices
Expertise -
-
TLP results analysis
Defined ESD design rules related to ESD devices for pad cell designers (T.D. and PDK
collaboration)
- Defined ESD Pcells for pad cell design (PDK collaboration)
Cell Level
- Designed various circuit driven ESD protection (schematic, layout implementation and
Electrical characterization) according to system level constraints
- Implemented ESD devices in IO Library
- Defined, managed automation and run Cell Level ESD characterization Flow
- Definition and implementation of ESD Test Bench
- Reviewed layout of all pad cells according to ESD aspect
- Defined, managed automation and run Cell level integration flow
Library Level
- Defined ESD Guidelines for customers regarding IOs and ESD Libraries
- Defined and implemented each ESD cell for automatic ESD safe design
Chip Level
- Defined and implemented relevant ESD strategy according to product constraints
- Defined, managed automation and run Chip Level ESD Verification Flow
- Run Chip Level ESD Verification and analysis on all products
System Level
- Defined compatibility of chip level ESD strategies with System level Test (e.g. ESD Gun)
- Defined compatibility of ESD strategies with applications constraints (security system,
Tolerant pins)

2. IOs Device Level
- Defined Bonding structure according to IOs pitch and assembly constraints
Field
Expertise Cell Level
- Definition and implementation of IOs topologies considering product aspect ratio
- Design of Standard IOs (GPIO, Open drain, Open Source, Tolerant, Compliant)
(schematic, layout implementation and Electrical characterization)
Library Level
- Definition and implementation of IOs Library content
Std Cells Cell Level
- Definition and implementation of standard cell topologies according to both process
Field constraints and PnR constraints
Experience -
-
Definition of Compaction rule for generation of standard cells from layout
Definition of Generation rules for generation of standard cells from schematic
Library Level
- Definition and implementation of cells with dedicated optimization (speed, power, density)
H. R. - Ph.D. Student Management
Management - Local and External Engineers
- Local and External Layout Technicians
EDUCATION
1997 - 2000
- Ph. Thesis – LIRMM / University Of Montpellier II
“Characterization and Modeling of Parasitic Interconnection Capacitances in Deep
Submicron Technologies”
1995 - 1996
- M.S. Degree from Microelectronic Department – LIRMM / University of Montpellier II
PUBLICATIONS
US Patents Issued
[1] US 8,009,396 “Method and Apparatus for ESD Protection”, D. Bernard, J .J. Kazazian, A. Riviere,
Filed in February 2008, Issued in August 2011
[2] US 7,760,476 “Threshold Voltage Method and Apparatus for ESD Protection”, A. Riviere, F. Demolli,
D. Bernard, Filed in June 2007, Issued in July 2010
[3] US 7,570,468 “Noise Immune RC Trigger for ESD Protection”, D. Bernard, A. Riviere, Filed in June
2007, Issued in August 2009
[4] US 7,180,331 “Voltage Tolerant Structure for IOs Cells”, D. Bernard, V. Gosmain, Filed in January
2005, Issued in February 2007

3. Journal Papers
[1] David Bernard, Christian Landrault, Pascal Nouet,
“Interconnect Capacitance Modelling in a VDSM CMOS Technology” . VLSI-SOC, 133-144, Kluwer
Academics Publisher 2001
Main Conference Papers
[1] Antoine Riviere, David Bernard, Florence Azais, Pascal Nouet,
"On the Use of LVTpnp in ESD Protection", International ESD Workshop, ESDa, Lake Taboe City CA,
USA, May 2007
[2] David Bernard, Christian Landrault, Pascal Nouet,
"Analytical Models for Inter- and Intra-Layer Capacitance Extraction in a 0,25 µm CMOS Technology",
SPI’2000, 4th IEEE Workshop on Signal Propagation On Interconnects, Magdeburg, Germany, May 17-
19, 2000.
[3] David Bernard, Christian Landrault, Pascal Nouet,
"Interconnect capacitance monitoring and modelling in a 0,25 µm CMOS technology",
DCIS’99, 14th Design of Circuits and Integrated Systems Conference, Palma de Mallorca, Spain,
November 16-19, 1999, pp. 701-705.
[4] David Bernard, Alain Toulouse, Christian Landrault, Pascal Nouet,
"Efficient 3D Modelling for Extraction of Interconnect Capacitance in Deep Submicron Dense Layouts",
DATE’99, Design, Automation and Test in Europe, Munich, Germany, March 9-12, 1999, pp. 576-580.
[5] David Bernard, Pascal Nouet, Christian Landrault, Alain Toulouse,
"Interconnects in deep sub-micron dense layouts : design and performance aspects",
SAME’98, Sophia-Antipolis Forum on MicroElectronics, Technical Conference Proceedings, October
29th, 1998, pp. 54-56.
SKILLS
Languages: French (mother tongue), English (fluent), Spanish (knowledge)
Tools: Cadence Design Framework, Virtuoso Assura, Mentor Calibre, Spice, Eldo, Spectre, ADE, Cadence
VLM layout compactor, Synopsys Cadabra layout generator, Magma Silicon Smart, Word, Excel, PowerPoint
Programming languages: C-shell, Cadence Diva, Cadence Skill (knowledge), PERL (knowledge)
MISC
Hobby: Video Game, Enology
Music: Saxophone, Guitar Bass
Sports: Soccer (only in front of TV now)