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![REFERENCES
[1] A. L. Lacaita, ‘‘Physics and Performance of Phase Change Memories,’’ SISPAD, pages 267-270, Sept. 2005.
[2] Varesi, E., et al. "Advances in Phase Change Memory Technology."European Phase Change and Ovonics Symposium, 2004.
[3] G. De Sandre et al., “A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90nm Standard CMOS Technology,” IJSSC, vol.46, no. 1,
January, 2011.
[4] G. De Sandre et al., “Program Circuit for a Phase Change Memory Array with 2 MB/s Write Throughput for Embedded Applications,” IEEE,
2008.
[5] Ayman Fayed and Mohammed Ismail, Adaptive Techniques for Mixed Signal System on Chip, Springer, Sept. 2006.
[6] Yuhua Cheng, “The Influence and Modelling of Process Variations and Device Mismatch for Analog/RF Circuit Design,” 4th IEEE International Caracas
Conference on Devices, Circuits and Systems, 17-19 April, 2002.
[7] Massimiliano Frulio, Stefano Sivero, Simone Bartoli and Sabina Mognoni, “DAC-Based Voltage Regulator for Flash Memory Array,”
US2003/028479, March 25, 2004.
[8] Joao Ramos, Michiel Steyaert, “Three Stage Amplifier With Positive Feedback Compensation Scheme,” IEEE Conference on Custom
Integrated Circuits, 2002.](https://image.slidesharecdn.com/currentdacbasedregulatorfornvm-170208194359/85/Current-dac-based-regulator-for-nvm-14-320.jpg)
![REFERENCES
[9] Saeed Reza Afrancheh, Mohammad Reza Arazm, Ali Reza Sahab, Hamid Reza Afrancheh, “Design Procedure for Settling Time
Minimization in Three-Stage RNMC Amplifiers,” IEEE EUROCON, pages 1-4, April 2011.
[10] P. E. Allen and D. R. Holberg, “CMOS Operational Amplifiers,” in CMOS Analog Circuit Design, 2nd Ed., Oxford
UniversityPress, 2002.
[11] BehzadRazavi, “Operational Amplifiers,” in Design of Analog CMOS Integrated Circuits,McGraw-Hill, Inc., New York, USA, Ed. 2002.
[12] G. Cappuccino, F. A. Amoroso, A. Pugliese, “Class-AB Output Stage Design For High Speed Three-Stage Op-Amps,” IEEE ICECS,
pages 1-4, Dec. 2009.
[13] Anshu Gupta, U.B.S. Chandrawat, D. K. Mishra, R. Khatri and Preet Jain, “A Two Stage and Three Stage CMOS OPAMP
with Fast Settling, High DC Gain and Low Power Designed in 180nm Technology,” IEEE, 2010.
[14] Gaetano Palumbo and Salvatore Pennisi, “Design Methodology and Advances in Nested-Miller Compensation,” IEEE Transactions on
Circuits and Systems-I, vol. 49, no. 7, July 2002.
[15] Wachirapunya Punyawong, Worawat SA-Ngiamvibool, Apinan Aurasopon, Saweth Hongprasit, ‘‘An Improvement of CMOS
Voltage Reference,’’ PRZEGLAD ELEKTROTECHNICZNY, June 2013.](https://image.slidesharecdn.com/currentdacbasedregulatorfornvm-170208194359/85/Current-dac-based-regulator-for-nvm-15-320.jpg)
Current dac based regulator for nvm
- 1. CURRENT DAC BASEDREGULATOR FOR NVM PRESENTED BY -BHAWANA SINGH NIRWAN
- 2. CONTENTS • Introduction • Flashmemory concerns • Phase change memories • Voltage regulator topologies • Proposed regulator • Reference circuit • Conclusion • References
- 3. NVM MARKET NVM TechnologyApplications Industry and Transportation Mobile Phones Mass Storage Memory Embedded MCU for Smart Cards
- 4. FLASH MEMORY CONCERN •Scaling technology • Less charge on floating gate CG DS B CG DS B B S CG D - - - - - - - - - - - - - -
- 5. NVM ALTERNATIVES • MagneticRAM (MRAM) • FeRAM • PCM (Select Transistor) I t IRESET ISET TSETTRESET PCM
- 6.
- 7. VOLTAGE REGULATION SCHEME WriteDriver (WD) Regulator Column Decoding Regulator Row Decoding Regulator To supply WDs at 4.4 V Column Decoder supply, 3.5 V Row Decoder supply, 2.5 V
- 8. VOLTAGE REGULATORS Voltage Baseddesign Vout = Vbg(1 + R_var/R_fix) Current Based design Vout = Vbg + I_var * R_fix I_var = Vbg/R
- 9. BASIC CURRENT MODEREGULATOR (ABSTRACT VIEW) Error amplifier: three-stage op-amp Current DAC modularity: 1 µA Vbg: 1.2 V
- 10. DESIGN APPROACH FORERROR AMPLIFIER Differential Input amplifier, single ended output Level Shift, Voltage to current conversion stage Output Stage Va Vb Folded Cascode stage Common source stage Push-pull stage Vout
- 11. ERROR AMPLIFIER DESIGN Vrefn& Vrefp: Used from reference current mirror Vbiasn = VGS7 + (VGS9 – VTH9) = VGS8 + (VGS10 – VTH10) Mb
- 12. ERROR AMPLIFIER DESIGN Associationof poles with nodes
- 13.
- 14. REFERENCES [1] A. L.Lacaita, ‘‘Physics and Performance of Phase Change Memories,’’ SISPAD, pages 267-270, Sept. 2005. [2] Varesi, E., et al. "Advances in Phase Change Memory Technology."European Phase Change and Ovonics Symposium, 2004. [3] G. De Sandre et al., “A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90nm Standard CMOS Technology,” IJSSC, vol.46, no. 1, January, 2011. [4] G. De Sandre et al., “Program Circuit for a Phase Change Memory Array with 2 MB/s Write Throughput for Embedded Applications,” IEEE, 2008. [5] Ayman Fayed and Mohammed Ismail, Adaptive Techniques for Mixed Signal System on Chip, Springer, Sept. 2006. [6] Yuhua Cheng, “The Influence and Modelling of Process Variations and Device Mismatch for Analog/RF Circuit Design,” 4th IEEE International Caracas Conference on Devices, Circuits and Systems, 17-19 April, 2002. [7] Massimiliano Frulio, Stefano Sivero, Simone Bartoli and Sabina Mognoni, “DAC-Based Voltage Regulator for Flash Memory Array,” US2003/028479, March 25, 2004. [8] Joao Ramos, Michiel Steyaert, “Three Stage Amplifier With Positive Feedback Compensation Scheme,” IEEE Conference on Custom Integrated Circuits, 2002.
- 15. REFERENCES [9] Saeed RezaAfrancheh, Mohammad Reza Arazm, Ali Reza Sahab, Hamid Reza Afrancheh, “Design Procedure for Settling Time Minimization in Three-Stage RNMC Amplifiers,” IEEE EUROCON, pages 1-4, April 2011. [10] P. E. Allen and D. R. Holberg, “CMOS Operational Amplifiers,” in CMOS Analog Circuit Design, 2nd Ed., Oxford UniversityPress, 2002. [11] BehzadRazavi, “Operational Amplifiers,” in Design of Analog CMOS Integrated Circuits,McGraw-Hill, Inc., New York, USA, Ed. 2002. [12] G. Cappuccino, F. A. Amoroso, A. Pugliese, “Class-AB Output Stage Design For High Speed Three-Stage Op-Amps,” IEEE ICECS, pages 1-4, Dec. 2009. [13] Anshu Gupta, U.B.S. Chandrawat, D. K. Mishra, R. Khatri and Preet Jain, “A Two Stage and Three Stage CMOS OPAMP with Fast Settling, High DC Gain and Low Power Designed in 180nm Technology,” IEEE, 2010. [14] Gaetano Palumbo and Salvatore Pennisi, “Design Methodology and Advances in Nested-Miller Compensation,” IEEE Transactions on Circuits and Systems-I, vol. 49, no. 7, July 2002. [15] Wachirapunya Punyawong, Worawat SA-Ngiamvibool, Apinan Aurasopon, Saweth Hongprasit, ‘‘An Improvement of CMOS Voltage Reference,’’ PRZEGLAD ELEKTROTECHNICZNY, June 2013.
- 16.