More Related Content
What's hot
What's hot (20)
Recently uploaded
Recently uploaded (20)
Cs 8351 dpsd-unit-2
- 1. CS 8351- DIGITAL PRINCIPLES AND SYSTEM DESIGN II YEAR CSE & IT UNIT-2 COMBINATIONAL CIRCUITS K.BALAJI, AP/ECE, SSMCE
- 2. Unit-2- Combinational circuits • The Logic circuits whose Output depends on the inputs at that time is known as combinational circuit K.BALAJI, AP/ECE, SSMCE
- 3. Analysis of Combinational circuit • K.BALAJI, AP/ECE, SSMCE
- 9. ANALYSIS PROCEDURE • Label all the Gate outputs with symbols • Determine Boolean functions • Repeat the step 2 until the Output • Substitute the functions to obtain the output in terms of input • Draw the Truth Table K.BALAJI, AP/ECE, SSMCE
- 10. HALF ADDER: • A Half Adder is a Combinational Circuit that performs the addition of two bits and produce the Outputs SUM & CARRY circuit K.BALAJI, AP/ECE, SSMCE
- 11. A B CARRY SUM 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 HALF ADDER TRUTH TABLE: K.BALAJI, AP/ECE, SSMCE
- 15. • HALF SUBTRACTOR: • A Half Subtractor is a Combinational Circuit that performs the Subtraction of two bits and produce the Outputs DIFFERENCE & BORROW K.BALAJI, AP/ECE, SSMCE
- 16. A B BORROW DIFFEREN CE 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 0 HALF SUBTRACTOR TRUTH TABLE: K.BALAJI, AP/ECE, SSMCE
- 17. K-Map for DIFFERENCE: K-Map for BORROW: DIFFERENCE = A’B + AB’ BORROW = A’B HALF SUBTRACTOR- LOGIC DIAGRAM K.BALAJI, AP/ECE, SSMCE
- 18. • FULL ADDER: • A Full Adder is a Combinational circuit that performs the binary addition of 3 input bits and produces the output SUM & CARRY. K.BALAJI, AP/ECE, SSMCE
- 19. A B C CARRY SUM 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 FULL ADDER- TRUTH TABLE: K.BALAJI, AP/ECE, SSMCE
- 23. FULL SUBTRACTOR • FULL SUBTRACTOR: • A Full Subtractor is a Combinational circuit that performs the Subtraction of 3 input bits and produces the output DIFFERENCE & BORROW. K.BALAJI, AP/ECE, SSMCE
- 30. FULLADDER USING TWO HALF ADDERS- LOGIC DIAGRAM K.BALAJI, AP/ECE, SSMCE
- 31. 4 BIT PARALLEL ADDER (RIPPLE CARRY ADDER) • 4 bit Parallel Adder can be designed by using 4 Full adders K.BALAJI, AP/ECE, SSMCE
- 33. PARALLEL SUBTRACTOR • Parallel Subtraction is based on 2’s Complement • A-B can be done by taking the 2’s complement of B and Adding with A K.BALAJI, AP/ECE, SSMCE
- 35. PARALLEL SUBTRACTOR K.BALAJI, AP/ECE, SSMCE
- 36. PARALLEL ADDER / SUBTRACTOR • Addition and Subtraction can be performed in one Common circuit – Adder / Subtractor • This is done by XOR Gate K.BALAJI, AP/ECE, SSMCE
- 37. PARALLEL ADDER / SUBTRACTOR K.BALAJI, AP/ECE, SSMCE
- 42. CARRY PROPAGATION ADDER • In Parallel Adder , The Carry outputs of each full adder is connected to the carry inputs of next full adder. • This causes delay. • To avoid the delay , we use carry propagation adder K.BALAJI, AP/ECE, SSMCE
- 43. CARRY PROPAGATION ADDER K.BALAJI, AP/ECE, SSMCE
- 59. CODE CONVERTERS • A Coder Converter circuit must be inserted between two systems , if each system uses different codes for the same information K.BALAJI, AP/ECE, SSMCE
- 60. BINARY TO BCD CODE CONVERTER K.BALAJI, AP/ECE, SSMCE
- 65. K MAP FOR B0 K.BALAJI, AP/ECE, SSMCE
- 66. K MAP FOR B0 K.BALAJI, AP/ECE, SSMCE
- 67. K MAP FOR B1 K.BALAJI, AP/ECE, SSMCE
- 69. K MAP FOR B2 K.BALAJI, AP/ECE, SSMCE
- 70. K MAP FOR B3 K.BALAJI, AP/ECE, SSMCE
- 71. K MAP FOR B4 K.BALAJI, AP/ECE, SSMCE
- 75. BCD TO EXCESS 3 CODE CONVERTER 0+3 =3 5+3 =8 K.BALAJI, AP/ECE, SSMCE
- 84. PARITY GENERATOR / CHECKER • A Parity Bit is an extra bit included with the Binary message at the Transmitting section to make the number of 1’s either odd or even. • It is used for detecting the errors in the received information K.BALAJI, AP/ECE, SSMCE
- 85. PARITY GENERATOR K.BALAJI, AP/ECE, SSMCE
- 86. PARITY GENERATOR K.BALAJI, AP/ECE, SSMCE
- 92. MAGNITUDE COMPARATOR • A Magnitude comparator is a combinational circuit used to compare the relative magnitude of two binary numbers A & B K.BALAJI, AP/ECE, SSMCE
- 103. DECODER • A Decoder is a combinational circuit that converts ‘n’ number of input lines to a 2^n output lines. • ex : 2 X 4 3 X 8 4 X 16 • Applications: Counter systems, BCD to seven segment decoder K.BALAJI, AP/ECE, SSMCE
- 104. 2 to 4 line Decoder K.BALAJI, AP/ECE, SSMCE
- 108. PRIORITY ENCODER K.BALAJI, AP/ECE, SSMCE
- 116. REFERENCES: 1. M. Morris R. Mano, Michael D. Ciletti, ―Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog‖, 6th Edition, Pearson Education, 2017. 2.Digital Principles and System Design, D.Edwin Das, Trisea Publisher K.BALAJI, AP/ECE, SSMCE