This document discusses conditional processing, Boolean, and comparison instructions in CPUs. It covers the following topics: - The CPU flags register which contains status flags like carry, overflow, zero, and sign flags. - The AND instruction which performs a bitwise AND operation and can be used to convert characters between lowercase and uppercase. It clears the overflow and carry flags. - The OR instruction which performs a bitwise OR operation and can be used to set bits. It clears the carry and overflow flags. - How bitmaps can represent sets and how AND, OR, and NOT instructions can perform set operations like intersection, union, and complement on bitmaps.

1. Conditional
Processing
Booleanand
Comparison
Instructions
• Presented To: Mam Asma Fardoos
• Presented By:

2. Conditional
Processing
Booleanand
Comparison
Instructions
• Group Members are:
• 20011519-033 Usama Aslam
• 20011519-006 Muhammad Rafy
• 20011519-056 Kinza Abbas
• 20011519-034 Sawera Nawaz

3. Conditional Processing
Booleanand
Comparison
Instructions
• Index:
• The CPU flags
• AND Instructions
• OR Instructions
• Bit-Mapped Set

4. TheCPUflags
Presented By:
(20011519-033)
Usama Aslam

5. CPU FLAGS
The FLAGS register is the status register that contains
the current state of a CPU.
The size and meanings of the flag bits are architecture
dependent.

6. Flags Register:
A special register with
individual bit position that indicate the status of
the microprocessor.
Two types of flags:
Status flags
Control flags

8. CPU flags:
Carry Flag (CF):
Set, if the result of an un-signed operation is too big
to fit into destination.
1 = Carry Flag
0 = No Carry

9. CPU Flags:
Overflow flag:
set, if the result of a signed operation in too wide to
fit into destination.
1 = Overflow flag
0 = No Overflow

10. CPU Flags:
Zero flag:
Set when the result of an Arithmetic
operation is zero.
1 = Zero
0 = No Zero

11. CPU Flags:
Sign Flag:
Set, When result of an operation is negative.
1 = Negative
0 = Positive

12. CPU Flags:
Parity Flag:
If lower byte of the result contains even no. of 1’s, the
parity Flag is set and for odd no. of 1’s , the parity Flag in reset.
Note: Parity Flag operates on lower 8-bits, it doesn’t operate on 16-bits.
1 = Negative
0 = positive

13. ANDInstruction
Presented By: Muhammad Rafy
(20011519-006)

14. AND
Instruction
• Definition
• The AND instruction performs a Boolean
(bitwise) AND operation between each pair
of matching bits in two operands and places
the result in the destination operand.
• Syntax
• AND destination,source
• Both operand must be same in size

15. ANDInstruction
• The following operand combinations are
permitted:
• AND reg,reg
AND reg,mem
AND reg,imm
AND mem,reg
AND
mem,imm
• The operands can be 8, 16, or 32 bits
• Truth Table for AND operation
x y x ∧ y
0 0 0
0 1 0
1 0 0
1 1 1

16. ANDInstruction
Example
Same operand types
0011 1011
AND 0000 1111
0000 1011
Example
suppose AL is initially set to 10101110 binary. After ANDing
it with 11110110, AL equals 10100110:
mov al,1010 1110b
and al,1111 0110b ; result in AL =10100110
Changed Unchanged

17. ANDInstruction
• The AND instruction always clears the
Overflow and
• Carry flags.
• It modifies the Sign, Zero, and Parity
flags in a way that is consistent with
the value assigned to the destination
operand.
• For example, suppose the following
instruction results in a value of Zero
in the EAX register. In that case, the
Zero flag will be set.
• and eax,1Fh

18. ANDInstruction
• Converting Characters to Upper Case
• The AND instruction provides an easy way to
translate a letter from lowercase to uppercase. If
we compare the ASCII codes of capital A and
lowercase a, it becomes clear that only bit 5 is
different:
• 0 1 1 0 0 0 0 1 = 61h ('a’)
• 0 1 0 0 0 0 0 1 = 41h ('A’)
• The rest of the alphabetic characters have the
same relationship. If we AND any character with
11011111 binary, all bits are unchanged except
for bit 5, which is cleared.

19. ORInstruction
Presented By:
(20011519-056)
Kinza Abbas

20. ORInstruction
• Definition
• The OR instruction performs a boolean OR
operation between each pair of matching bits in
two operands and places the result in the
destination operand. The OR instruction is
particularly useful when you need to set 1 or
more bits in an operand without affecting any
other.
• Syntax
• OR destination,source

21. ORInstruction
A B A V B
0 0 0
0 1 1
1 0 1
1 1 1
Combination of OR instruction
OR
reg,reg
OR
reg,mem
OR
reg,imm
OR
mem,reg
OR mem,imm
• The operands can be 8, 16, or 32 bits, and they must
be the samesize.
• Truth Table for OR instruction

22. ORInstruction
Example
If AL is initially equal to 11100011 binary and then we OR it with 00000100, the
result equals 11100111:
mov al,11100011b
or al,00000100b
Example
mov al,10
mov bl,11
; result in AL =11100111
or al,bl :result in AL =0001011

23. ORInstruction
Flags effected by OR instruction
• The OR instruction always clears the Carry and Overflow
flags. It modifies the Sign, Zero, and Parity flags in a way
that is consistent with the value assigned to the
destination operand.
Zero flag effected by OR instruction
• It is set when the result of an arithmetic operation is zero, if
OR instruction gives a result zero ZF is set
• Example
• if AH is initially equal to 00000000 binary and then we OR
• with 00000000 binary
• mov ah,00000000
• or ah,00000000 ; result in AH is 00000000
• Zero flag is set as our result is 00000000

24. ORInstruction Zero
flag
Sign
flag
Value in AL
…
Clear Clear Greater then
zero
Set Clear Equal to zero
Clear Set Less than
zero

25. ORInstruction
• Parity flag affected by OR instruction
• If the lower byte of the result contain even
number, then even parity set
• If OR instruction give result (number of 1’s
even in lower byte)
• then PF is set. For odd number of 1’s it is
reset
• Example
• mov ax,0000000001010110
• or ax,0000000000010010 ;Result in AX
= 0000000 01010110
• Parity flag is set because lower byte
contain even number of
• 1’s.

26. Bit-MappedSet
Presented By:
(20011519-034 )
Sawera Nawaz

27. Bit-MappedSet
• Some applications manipulate sets of items
selected from
• a limited-sized universal set.
• Examples might be employees within a company, or
environmental readings from a weather monitoring
station.
• Rather than holding pointers or references to
objects in a container such as a Java HashSet, an
application can use a bit vector (or bit map) to map
the bits in a binary number to an array of objects.

28. Bit-MappedSet
For example, the following
binary number uses bit
positions numbered from 0 on
the right to 31 on the left to
indicate that array elements 0,
1, 2, and 31 are members of
the set named SetX:
SetX = 10000000
00000000
00000000
00000111
We can easily check for set
membership by ANDing a
particular member’s bit
position
mov eax,SetX
and eax,10000b ;
is element[16] a
member of SetX?
If the AND instruction in this example clears the
Zero flag, we know that element [16] is a
member of SetX

29. Bit-MappedSet
Set Complement
• The complement of a set can be
generated using the NOT instruction,
which reverses all bits.
• The complement of the SetX that we
introduced is
• generated in EAX using the following
instructions:
• mov eax,SetX
• not eax ; complement of SetX

30. Bit-MappedSet
• Set Intersection
• The AND instruction produces a bit vector that represents
the intersection of two sets.
• The following code generates and stores the intersection of
SetX and SetY in EAX:
• mov eax,SetX
• and eax,SetY
• This is how the intersection of SetX and SetY is produced:
• 1000000 00000000 00000000 00000111(SetX)
• (AND) 1000001 01010000 00000111 01100011
(SetY)
• 1000000 00000000 00000000 00000011
(intersection)
• It is hard to imagine any faster way to generate a set
intersection.
• A larger domain would require more bits than could be held
in a single register, making it necessary to use a loop to
AND all of the bits together.

31. Bit-MappedSet
The OR instruction produces a bit map that
represents the union of two sets.
• mov eax,SetX
• or eax,SetY
The following code generates the union of
SetX and SetY in EAX:
This is how the union of SetX and SetY is
generated by the OR instruction:
1000000 00000000 00000000 00000111
(SetX)
(OR) 1000001 01010000 00000111
01100011 (SetY)
1000001 01010000 00000111 01100111
(union)
Set Union

32. Thank you