The document contains questions and answers related to timing analysis concepts in digital circuit design such as hold time checks, setup time, clock skew, rise and fall times of standard cells, and setup and hold checks for multicycle paths. It discusses how positive clock skew reduces setup violations, that rise times are generally greater than fall times for standard cells, and that maximum and minimum delays are considered for setup and hold checks respectively.

1. • Which equation is valid for hold check
a) Tck->q of launch flop + T_comb - T_uncertianity >= Hold time of
the capture flop
b) Tck->q of launch flop + T_comb <= Hold time of the capture flop -
T_uncertianity
c) Tck->q of launch flop + T_comb - T_uncertianity + Tclk_period >=
Hold time of the capture flop
d) Tck->q of launch flop + T_comb + Tclk_period >= Hold time of the
capture flop - T_uncertianity
Answer : a

2. • What is the impact of positive clock skew on setup time
a. Setup violations increases
b. Setup violations reduces
c. No change
d. It depends on capture flop library setup time
Answer : b

3. • Considering equivalent in-out conditions for a standard cell, as per
basic internal properties, which statement stands true
a) Rise time > fall time
b) Fall time > rise time
c) Rise time = fall time
d) Cannot be concluded
Answer : a

4. Q. As per below figure, what is the tsetup of the capture flop ?
a. 7ns
b. 4ns
c. 3ns
d. 1ns

5. • For setup timing checks, ____ delays are considered in launch path
and ____ delays are considered in capture path
a. Maximum, Minimum
b. Minimum, Maximum
c. Equal
d. Depends on environmental conditions
Answer : a

6. • For hold timing checks, ____ delays are considered in launch path and
____ delays are considered in capture path
a. Maximum, Minimum
b. Minimum, Maximum
c. Equal
d. Depends on environmental conditions
Answer : b

7. • For a multicycle path, if setup is checked at 5th clock edge, then for
valid timing checks, hold should be checked at which clock edge
a. 5th
b. 4th
c. 1st
d. None of the above