This document outlines a computer engineering project that uses an SMPCache simulator to evaluate cache performance under different design alternatives. It describes using the simulator to test workloads from SPEC benchmarks with varying cache size, levels, and mapping. Metrics like miss rate are recorded and analyzed to understand the impact of design choices and identify opportunities for higher cache performance through factors like increased size and associativity. Future work involves further experimentation and studying interactions between factors.

1. Jordan University
Computer Engineering Department
Computer Performance Evaluation Project
Supervisor: Dr. Ghieth Abandah
Student: Aieshah F. Almaslam
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2. Outline
 Introduction
 Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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3. 3
Why cache?
High cache performance leads to high total system performance

4. Cache performance parameters
 Cache size
 Cache block size
 Cache levels
 Cache mapping
 Replacement policy
 Unified cache or splitted
Very big range of combinations, so we need to
parameter performance evaluation.
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5. Outline
 Introduction
 Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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6. 6
SMPCache simulator
Trace driven simulator
Windows compatible
User friendly interface
Wide range of configuration
Uniprocessor build in memory traces
Multiprocessor downloaded memory traces
Creating your own memory traces
Text and graph results
Simulator

7. SMPCache User-friendly interface
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8. 8
Organization of memory SMP or DSM
Number of processors 1,2,4,8,16,32,64or 128
Snoopy Protocol MSI, MESI or DRAGON
Bus arbitration random, LFU or LRU
Directory protocol SGI or off
Word Width (bits( 8,16,32or 64
Words in a block 1,2,4,8,16,32,64,128,up to 1024
Memory Blocks 1,2,4,8,16,32,64,up to 4194304.
Cache Levels 1,2,3or 4
Unified or splitted unified or data and instructions
Cache Blocks 1,2,4,8,16,32,64,128,256,512,1024or 2048
Mapping Direct, set-associative or fully associative
Cache sets in case of set-associative mapping
Replacement policy Random, LRU, LFU or FIFO
Writing strategy Writeback
Architectural characteristics
supported by SMPCache

9. Outline
 Introduction
 SMPCache Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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10. 10
Memory traces from SPEC’92 Benchmarks
Uni-processor traces
Real applications
Build in simulator software
Different types of applications
Integer and floating point
Examples: Hydro, Nasa7, Cexp, Mdljd, Ear,
Comp,Wave, Swm and UComp
Workload

11. Outline
 Introduction
 SMPCache Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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12. 12
Miss rate
Less miss rate less main memory access
 indication on execution delay
 less ink in the final graph
Metric performance

13. Outline
 Introduction
 SMPCache Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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14. 14
Design alternatives
for Cache size factor
Main memory size 64Gbytes
Block size 16Kbytes
Cache mapping fully associative
cache replacement Policy LRU
Cache levels 1
Cache levels size 16/32/64/128/256/1000Kbytes
Memory traces Comp/Nasa7/hydro

15. 15
Design alternatives
for Cache multi-level factor
Main memory size 64Gbytes
Block size 16Kbytes
cache mapping fully associative
cache replacement Policy LRU
Cache levels 1/2/3/4
Cache levels size 16/32/64/128Kbytes in order
Memory traces Comp/Nasa7/hydro
16 / 32 / 64 / 128 Kbytes

16. 16
Design alternatives
for Cache maping factor
Main memory size 64Gbytes
Block size 16Kbytes
cache mapping direct , 2,4,8,16,32 set associatiev
and fully associative
cache replacement Policy LRU
Cache levels 1
Cache levels size 16Kbytes
Memory traces Comp/Nasa7/hydro

17. Outline
 Introduction
 SMPCache Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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18. Implementation
In each simulation experiment
 Determine Main memory cache configuration
 Select the desired option from list menu
 Run the simulation
 Record the result
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19. Outline
 Introduction
 SMPCache Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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20. An Example
of one experiment result
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21. Cache Performance when
cache size is changed
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22. Cache Performance when
cache levels is changed
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23. Cache Performance when
cache mapping is changed
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24. Outline
 Introduction
 SMPCache Simulator
 Workload
 Metrics
 Design alternatives
 Implementation
 Results Analysis
 Conclusion & Future work
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25. 25
Higher cache performance
 Higher cache size
 Higher cache levels
 Higher associativity
- But there is a ”Tradeoff”
Conclusion

26. 26
Evaluate cache performance by studying
More factors
Factor interaction
Future Work

27. Any Question?
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Eng. Aiesha F. Al-maslam