CA UNIT I.pptx

By
Ms.K.LALITHA, AP/CSE
KNCET
Wednesday, August 2, 2023 1

 Computer architecture is a set of rules and
methods that describe the functionality,
organization, and implementation of
computer systems

Functional Units – Basic Operational Concepts
– Performance- Instructions: Language of the
Computer – Operations, Operands –
Instruction Representation - Logical
operations –Decision Making – MIPS
Addressing.

 Moore’s law
 Abstraction to simplify design
 Common case fast
 Performance via parallelism
 Performance via pipelining
 Performance via prediction
 Hierarchy memory
 Dependability via redundancy

 States that integrated circuit resources
double’s every 2 yr’s or months.
 Important key note is that start and end of
completion may varies because of many
changes in between of period.
 So designer’s must anticipate the end design
at the beginning stage.

 Both computer architects and programmers
had to invent techniques to make themselves
more productive, for otherwise design time
would lengthen as dramatically as resources
grew by Moore's Law.
 For time consuming design’s of each and
every stage must be abstracted.
 By doing this each and every designer’s may
come to know that what type of information
was given at the initial stage.

 Making the common case fast will tend to
enhance performance better than optimizing
the rare case.
 More number of trail and error will be present
while designing the processor in case if any
particular design is not supported for that
configuration
 It’s better to change the design or to change
the entire architect for the processor.
 Because of that gives the faster performance.

 Throughput will be increased when using
parallel architecture for execution of multiple
task.

 Pipeline is used to fetch the instruction for
execution in parallel
 Operation of pipeline: first instruction output
may be taken as an input of next instruction
for processing.
 Example: output of first instruction is 10,
 Input of 2nd instruction is 10,20

 In some cases it is quit to use the predicted
processing instead of accurate.
 Because more are less both will be giving the
similar output.
 When the end design comes to know at the
initial stage.

 Programmers want memory to be fast, large,
and cheap, as memory speed often shapes
performance, capacity limits the size of
problems that can be solved, and the cost of
memory today is often the majority of
computer cost.
 Architects have found that they can address
these conflicting demands with a hierarchy of
memories, with the fastest, smallest, and
most expensive memory per bit at the top of
the hierarchy and the slowest, largest, and
cheapest per bit at the bottom.

 Computers only need to be fast
 They need to be dependable. Since any
physical device can fail, we make systems
dependable by including redundant
components that can take over when a failure
occurs and to help detect failures.

 Hardware
Input unit
Memory unit
Arithmetic logic unit
Control unit
Output unit

 System software
 Application software

 Operating system - Acts as a Intermediate between user
and computer hardware
 Editor- Create/modify source program/code
 Assembler - Convert the code into machine language
 Linker - Join several object file into one larger object
file
 Locator - Assign address to object code to load into
memory
 Interpreter - Processes higher level language programs
 Compiler - It processes whole source program
 Debugger - Load the source program into system
memory, execute it and debug it

 Word processing
 Spread sheets
 Image editors
 DBMS

 Processor and memory are now available at
better price than the olden day’s
 Processors and memory have improved at an
incredible rate computers are designed better
every time.
S.NO TECHNOLOGY RELATIVE PERFORMANCE
1951 VACUUM TUBES 1
1965 TRANSISTORS 35
1975 INTEGRATED CIRCIUTS 900
1995 VERY LARGE SCALE IC 2,400,000
2013 ULTRA LARGE SCALE IC 6,200,000,000

 John von neumann designed a computer
EDVAC (electronic discrete variable
computer)
 Used to perform more computation 5000
additions and subtraction per sec
 Made up of 18000 vacuum tubes
 Data are stored in single read-write memory
 Execution occurs in sequential fashion from 1
inst to next
 Wt: 30 tons, power consumption -140 kw

 It is a smaller than the other device and
consume less power, high speed, more
memory storage and size is small.
 It helps to handle both floating point and
fixed point operation.
 Separate i/o processor
 Support higher level programming languages.

 Low cost, fast processor, development of
memory chips.
 Allows to increase memory size and number of
i/o ports.
 Magnetic core memories are replaced
ICM(memory)
 Multipogramming, parallel processing, sharing
resources.
 Multiprogramming simplifies the CPU design and
increase the flexibility.
 Parallel processing was introduced to increase
effective speed at which program could be
executed.

 1964: IBM system/360 planned family of
computer
 Identical instruction set and operating
system, increase speed, i/o ports, memory
size, cost-from lower family to higher,
 Different models run the same software with
different price/performance.
 Mini computer: OEM(original equipment
manufacturer, bus structure.

 Uses LSI and VLSI for computer design
 It is possible to manufacture entire CPU, main
memory into single IC
 That can be implemented in PC and high
performance parallel processor.
 Concept supported are concurrency, pipeline,
cache, and virtual memories
 This evolved to produce the high
performance computing.

 Ultra large scale integration: embedding
millions of transistors on a single silicon
semiconductor microchip.
 ULSI has large computation and memory
powers from the microchip

 Performance is an important attribute of a computer.
 If a PC is working with high speed normally we will
compare that with other PC by speed wise as well as
cost, operation wise etc..
 User expects to reduce the start and execution time
of process.
 Execution time is also referred as response time.
Reduction in response time increases the throughput.
 Performance of computer is based on throughput so
it is reciprocal to execution time.
Performance A= 1/execution time A
 If 2 system named as A and B
performance A> performance B

 It can be written as
1/execution time a> 1/execution time b
Execution time b > execution time a
Performance a / Performance b = n
 If A is in n times faster than B then the
execution time on B is n times longer than it
is on A.
Performance A Execution time B
-------------- = --------------- = n
Performance B Execution time A

 EX: 1
If computer A runs a program in 10 seconds
and computer B runs the same program in 25
seconds, how much faster is A than B?
ANS: ?

 CPU execution time is measured in terms of
clock cycles. It is measured as clock cycles
per second.
CPU clock cycles for program
CPU execution time=
clock rate

 CPU execution time is measured in terms of
clock cycles. It is measured as clock cycles
per second.
CPU execution = CPU clock cycles for program X Clock
time for a program cycle time
Clock cycle time = 1/Clock rate
CPU execution time= CPU clock cycles for
program/ clock rate.

 EX : 2
Computer A runs a program in 12 seconds
with a 3GHz clock. We have to design a
computer B such that it can run the same
program in 9 sec. Determine the clock rate
for computer B. Assume that due to increase
in clock rate, CPU design of Computer B is
affected and it requires 1.2 times as many
clock cycles as computer A for execution of
this program.

1.CPU clock cycles A
2.Clock rate B

1.CPU clock cycles A = 36 X 109 cycles
2.Clock rate B =4.8 cycles /sec

T = N X CPI = N X CPI X Clock cycle time
R
N = Number of Instructions
CPI = CPU Clock cycles
Instruction count
R=Clock rate in clocks/second

 Running a processor in high clock speed
allows to perform the better performance, but
when compared with power supply it
generates more heat
 To solve this, if clock rate must be increased.
 P= CV2 f
 C= capacitive loading
 V= voltage applied
 F= running frequency

 If a new processor has 85% of the capacitive
load of old processor, Its supply voltage is
reduced by 20% and new processor results in
a 25% shrink in frequency. What is the impact
on power consumption?

 By lowering the power supply voltage as
possible to reduce power consumption
 By using large cooling devices.
 Turning off parts of chip that are not in
use(clock cycles).

 To decrease the response time from single
program execution by using single processor
they moved on to the concept of
multiprocessor which helps to execute
multiprogram simultaneously.

 Generally multiprocessor are represented as
multicore microprocessor (dual core, quad core)
etc..
Following problems are faced by the programmer
 Complex in making the program for multitasking
 No load balancing will over there
 Needs scheduling of sub task.
 Needs to maintain coordination between
subtasks.

 Improves cost and performance ratio of
system
 Several processor may be combined to fit the
needs of an application while avoiding the
expense of the unneeded capabilities of
centralized system.
 Easy to find out malfunctioning. So processor
can be replaced easily.
 Improves the reliability because of using
multi processor

 The basic function of computer to execute
program, sequence of instructions.
 Instructions are stored in the computer
memory.
 Instructions are executed to process data
which is loaded into the computer memory
through input unit.
 After processing the data, the result is either
stored back to into the computer memory for
the further reference or it is sent to the
outside world through the output port.

 Program Counter (PC)
 Instruction Register(IR)
 Memory Address Register(MAR)
 Memory Data Register(MDA) also called as
Memory Buffer Register(MBR)
 General Purpose Registers
 ISR- Interrupt Service Routine

 Number of operation and instruction are
executed based on the CPU which means that
can be represented as machine instruction.
 Machine instructions are in the form of binary
codes.
 If particular task has been completed with the
help of binary code then it is known as
machine language program.
 It also holds elements of instruction.

 Operation code: specifies the operation to be
performed, operations are represented in the
form of binary codes.
 Source and destination operand: specifies the
operand field of Source and Destination.
 Source operand address: operation specified by
the instruction may require one or more source
operands.
 Destination operand: operation executed by the
CPU may produce the result, since results are
stored in destination operand.
 Next instruction address: Next executable
instruction after completion of current
instruction

 Processor registers, main memory, I/O device
 Immediate value: The value of source
operand may be in the instruction itself.
 Representation of instruction:
 Opcode: 4 bits
 Operand address1 and 2 : 6 bits
OPCODE OPERAND
ADDRESS1
OPERAND
ADDRESS 2

1. According to operation: based on the instruction
operation instruction set can be differentiated.
 Data processing: arithmetic and logical
instruction, performs both arithmetic and logical
operation.
 Data storage: memory instruction, performs the
operation using register.
 Instruction must be transferred from CPU register
to memory register.
 Data movement: data transfer instruction, holds
the transfer of data from CPU register and I/O
devices

 Control: Test and Branch Instructions,
 Test instructions are used to test the value of
data word or the status of a computation.
 Branch instructions are used to branch to a
different set of instructions depending n the
decision made.
2. According to number of addresses:
◦ Three address instruction- ADD C,A,B
◦ Two address instruction – ADD A,B
◦ One address instruction – ADD D (AC<-AC+D)
◦ Zero address instruction – AC<-AC

EX :
Write a program to evaluate the arithmetic
statement Y=(A+B)*(C+D) using three-
address, two address, one address
instructions.
Soln:
Three address:
ADD R1, A, B
ADD R2 ,C, D
MUL Y,R1,R2

Two address:
MOV R1, A
ADD R1, B
MOV R2, C
ADD R2, D
MUL R1, R2
MOV Y, R1

One address:
LOAD A
ADD B (A <- A+B)
STORE X
LOAD C
ADD D
MUL X (ac=ac*x. Ex: c=c*x)
STORE Y

 Each instruction in a program specifies
operation to be performed and data to be
processed. For this reason instruction are
divided into 2 types: opcode and operand
Addresses:
 It holds the information as data, in many
cases calculation must be performed on the
operand reference in an instruction determine
physical address.
 In this context address can be considered as
unsigned integer operands.

 All computer supports numeric data types,
common data types
 Integer or fixed point
 Floating point
 Decimal

 A text and character string helps to make a
document
 ASCII code supports to represent the
character
 Unique 7-bit pattern helps to represent 123
different character
 ASCII encoded characters are stored and
transmitted using 8 bits per character.
 8th bit may be set to 0 or used as an parity bit
for error detection

 Most of the processor interpret data as a bit,
byte, word or double word they are
represented as units of data
 If data item is viewed as n of 1 bit item, each
item holds a logic value of 0 or 1

 Data transfer operation: move, store, load,
exchange, clear, set, push, pop
 Move: transfer word from source to destination
 store: from processor to memory
 Load: from memory to processor
 Exchange: swaps the data of source and
destination.
 Clear: from 0s to destination
 Set: from 1s to destination
 Push: from source to top of stack
 Pop: from top of stack to destination.

 Add, sub, multiply, divide, absolute, negate,
increment, decrement
 Add: addition of 2 operands,
 absolute: replace operand by its absolute
value
 Negate: changes sign of operand
 Increment: adds 1 to operand
 Decrement: sub 1 from operand

 AND: performs logical AND, OR, NOT, Exclusive Or
 Test: test specified condition and set flags
accordingly.
 Compare: performs logical or arithmetic comparison
 Set control variables: set controls for protection
purposes
 Logical shift: 2 shift operation may be happened
logical left shift and right shift.
 Arithmetic shift: arithmetic shift right operation
repeats the sign bit as the fill in for the vacant
position
 Rotate: the bits shifted out of the operand are lost,
except for last bit shifted out which is retained in the
carry flag C

 Translate: translates values in section of memory
based on a table of correspondences
 Converts: the content of word from one to
another
 Input: transfer data from specified i/o ports or
device to destination
 o/p: data from specified source to i/o ports
 Start i/o: transfer instructions to i/o processor to
initiate i/o operation
 Test i/o: transfer status information from i/o
system to specified destination.

 Jump: unconditional transfer, loads pc with
specified address.
 Jump conditional: test specified condition. If
condition is true, loads pc with specified
address; otherwise, do nothing.
 Call to subroutine: places current programs
return address on stack and jump to specified
address
 Return: load return address from stack into
pc

 Instruction format defines the lay out of bits
of an instruction
 It includes an opcode and implicitly, zero or
more operands, each explicit operand is
referenced using one of the addressing
modes
 Instruction length:
 More opcode and operands
 If operands and opcode are reduced program
complexity also gets reduced.

 Memory size: more bits are required in the
address field to access large memory range.
 Memory organization: the addressing
mechanism changes with the change in
memory organization and hence the required
number of addressing bits.
 Bus structure: the instruction length should
be equal to or multiple of the memory
transfer length

 Processor speed: memory becomes
bottleneck when more number of
instructions are given to CPU for processing

 Number of addressing modes: more
addressing modes more bits.
 Number of operands: more operands- more
number of bits.
 Register vs memory: when register are used
for address references few bits are required
than the memory
 Number of register sets: register are split up
into different categories data, segment, index
and pointer register.

 Address range: range of memory address that
can be referenced related to number of bits.
 Address granularity: address can references a
word or byte. A byte addressing is convenient
for character manipulation.

 Different instruction uses different memory
references, hence it is in situation that
instruction needs different addressing
modes.
 Even if instruction takes longer time for
decoding, executing that instruction is
incomplete instruction.

 Provides flexibility addressing modes
 Reduces the count of instruction fetch cycle.
 Reduces amount of space taken by a program

 Requires more CPU design
 Decoding of instruction is difficult.

 R-Format
 I-Format
 J-Format

 It helps the processor for accessing the data
from memory or i/o device.
 Different method used for accessing the data
are represented as addressing modes.
 To complete the operation of addressing
mode we use pc(program counter) which is
used to fetch the address of next instruction.
 Effective address are made by using three
elements: base, index, displacement

 Register
 Direct or absolute
 Immediate
 Indirect
 Register indirect
 Displacement
Relative
Base register addressing mode
Index addressing mode
 Auto increment and decrement.
 Stack Addressing mode

 Operand is the content of processor register
name of instruction is specified in the
instruction.
 Example: MOV R1, R2(content of register R2
is moved to R1)

 Address location of operand is given
explicitly.
 Example: MOV A 2000 it copies the content
of 2000 into the location A register.
 Address of operand is given explicitly.

 operand is given in explicit mode
 Example: MOV A, #20 copies the operand 20
in register A
 # is used to indicate this operand is referred
as immediate.

 Instruction holds the address of memory
which refers the address operand
 Register indirect addressing mode: effective
address of the operand is the content of a
register
 Example: MOV A,(R0) copies the content of
memory addressed by the content of register
R0 into register A

 The effective address of the operand is the
contents of a register or the main memory
location whose address is given explicitly in
the instruction.
 Example: MOV (R0), A

 Displacement addressing requires that the
instruction have two address fields,
at least one of which is explicit.
 The value contained in one address field (value =
A) is used directly.
 implicit reference is based on opcode,
refers to a register whose contents are added to
A to produce the effective address.
 Effective address= value + address of a register
 EA = A + (R)
 Relative addressing, Base-register addressing,
Indexing

 Referenced register is program counter hence
it can also be represented as PC-relative
addressing
 Adding the content of PC to the address field
EA=PC+ address part of instruction.
 This addressing mode commonly used to
specify target address branch instruction.
 JNZ BACK: this instruction causes program
execution to go to the branch target location
identified by the name back

 Referenced register consists of both main
memory address and displacement address,
displacement is usually unsigned integer
number EA=(R)+Displacement
 Example: MOV A, [R+8]

 In this addressing mode, the address field
refers main memory and referenced register
 EA= memory address +(R)
 Allows a user to find out where the
instruction is stored in memory.
 Example: MOV R, [R1 + RI]
 Main memory address are referred as R1
 RI can act as an reference register.

 EA of the operand is the register specified in
the instruction
 As per the autoincrement register it increase
the address register by 1 after accessing the
operand of main memory
 MOV R2, +(R0)
 MOV R2, (R0)+
 Auto decrement: MOV R1, -(R0)

 A stack is a linear array of reserved memory
locations.
 It is associated with a pointer called Stack
Pointer(SP)
 Example: PUSH R
 LIFO

CA UNIT I.pptx

Recommended

Recommended

More Related Content

Similar to CA UNIT I.pptx

Similar to CA UNIT I.pptx (20)

More from ssuser9dbd7e

More from ssuser9dbd7e (6)

Recently uploaded

Recently uploaded (20)

CA UNIT I.pptx