Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
MODIFIED MARCH C- WITH CONCURRENCY IN TESTING FOR EMBEDDED MEMORY APPLICATIONSVLSICS Design
March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST. As March algorithms are well known algorithms for testing embedded RAMS, out of which March Cis known for finding all SAF, SOF, CF. This March C- is used frequently in the industry also. The proposed march algorithm is modified march c- algorithm which uses concurrent technique. Using this modified march c- algorithm the complexity is reduced to 8n as well as the test time is reduced greatly. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. This technique is applied for a memory of size 256x8 and can be extended to any memory size.
Implementation of FSM-MBIST and Design of Hybrid MBIST for Memory cluster in ...Editor IJCATR
In current scenario, power efficient MPSoC’s are of great demand. The power efficient asynchronous MPSoC’s with
multiple memories are thought-off to replace clocked synchronous SoC, in which clock consumes more than 40% of the total power. It
is right time to develop the test compliant asynchronous MpSoC. In this paper, Traditional MBIST and FSM based MBIST schemes
are designed and applied to single port RAM. The results are discussed based on the synthesis reports obtained from RTL Complier
from Cadence. FSM based MBIST is power and area efficient method for single memory testing. It consumes 40% less power when
compared with traditional MBIST. But, in case of multiple memory scenarios, separate MBIST controllers are required to test each
individual memories. Thus this scheme consumes huge area and becomes inefficient. A novel technique for testing different memories
which are working at different frequencies is in need. Therefore, an area efficient Hybrid MBIST is proposed with single MBIST
controller to test multiple memories in an Asynchronous SoC. It also includes multiple test algorithms to detect various faults. An
Asynchronous SoC with DWT processor and multiple memories is discussed in this paper, which will used as Design under Test
[DUT] and Hybrid MBIST is built around it to test the heterogeneous memories. The design is coded in Verilog and Validated in
Spartan-3e FPGA kit.
AN EFFICIENT ALGORITHM FOR WRAPPER AND TAM CO-OPTIMIZATION TO REDUCE TEST APP...IAEME Publication
System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today’s integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That’s why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge about their internal structural details. Such modular testing triggers the need of a special test access mechanism (TAM) to build communication between core I/Os and TAM and promises to minimize overall test time. In this paper, various issues are analyzed to optimize the Wrapper and TAM, which comprises the optimal partitioning of TAM width, assignment of cores to partitioned TAM width etc.
Virtual private networks (VPN) provide remotely secure connection for clients to exchange information with company networks. This paper deals with Site-to-site IPsec-VPN that connects the company intranets. IPsec-VPN network is implemented with security protocols for key management and exchange, authentication and integrity using GNS3 Network simulator. The testing and verification analyzing of data packets is done using both PING tool and Wireshark to ensure the encryption of data packets during data exchange between different sites belong to the same company.
The performance of an algorithm can be improved using a parallel computing programming approach. In this study, the performance of bubble sort algorithm on various computer specifications has been applied. Experimental results have shown that parallel computing programming can save significant time performance by 61%-65% compared to serial computing programming.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
MODIFIED MARCH C- WITH CONCURRENCY IN TESTING FOR EMBEDDED MEMORY APPLICATIONSVLSICS Design
March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST. As March algorithms are well known algorithms for testing embedded RAMS, out of which March Cis known for finding all SAF, SOF, CF. This March C- is used frequently in the industry also. The proposed march algorithm is modified march c- algorithm which uses concurrent technique. Using this modified march c- algorithm the complexity is reduced to 8n as well as the test time is reduced greatly. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. This technique is applied for a memory of size 256x8 and can be extended to any memory size.
Implementation of FSM-MBIST and Design of Hybrid MBIST for Memory cluster in ...Editor IJCATR
In current scenario, power efficient MPSoC’s are of great demand. The power efficient asynchronous MPSoC’s with
multiple memories are thought-off to replace clocked synchronous SoC, in which clock consumes more than 40% of the total power. It
is right time to develop the test compliant asynchronous MpSoC. In this paper, Traditional MBIST and FSM based MBIST schemes
are designed and applied to single port RAM. The results are discussed based on the synthesis reports obtained from RTL Complier
from Cadence. FSM based MBIST is power and area efficient method for single memory testing. It consumes 40% less power when
compared with traditional MBIST. But, in case of multiple memory scenarios, separate MBIST controllers are required to test each
individual memories. Thus this scheme consumes huge area and becomes inefficient. A novel technique for testing different memories
which are working at different frequencies is in need. Therefore, an area efficient Hybrid MBIST is proposed with single MBIST
controller to test multiple memories in an Asynchronous SoC. It also includes multiple test algorithms to detect various faults. An
Asynchronous SoC with DWT processor and multiple memories is discussed in this paper, which will used as Design under Test
[DUT] and Hybrid MBIST is built around it to test the heterogeneous memories. The design is coded in Verilog and Validated in
Spartan-3e FPGA kit.
AN EFFICIENT ALGORITHM FOR WRAPPER AND TAM CO-OPTIMIZATION TO REDUCE TEST APP...IAEME Publication
System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today’s integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That’s why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge about their internal structural details. Such modular testing triggers the need of a special test access mechanism (TAM) to build communication between core I/Os and TAM and promises to minimize overall test time. In this paper, various issues are analyzed to optimize the Wrapper and TAM, which comprises the optimal partitioning of TAM width, assignment of cores to partitioned TAM width etc.
Virtual private networks (VPN) provide remotely secure connection for clients to exchange information with company networks. This paper deals with Site-to-site IPsec-VPN that connects the company intranets. IPsec-VPN network is implemented with security protocols for key management and exchange, authentication and integrity using GNS3 Network simulator. The testing and verification analyzing of data packets is done using both PING tool and Wireshark to ensure the encryption of data packets during data exchange between different sites belong to the same company.
The performance of an algorithm can be improved using a parallel computing programming approach. In this study, the performance of bubble sort algorithm on various computer specifications has been applied. Experimental results have shown that parallel computing programming can save significant time performance by 61%-65% compared to serial computing programming.
A review paper on memory fault models and test algorithmsjournalBEEI
Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.
IMPLEMENTATION AND VALIDATION OF MEMORY BUILT IN SELF TEST (MBIST) - SURVEYIAEME Publication
This paper provides a survey of Implementation and Validation involved in Memory Built in Self-Test (MBIST). This paper comprises of the various strategies involved in the implementation and Validation of the Memory Built in Self-Test (MBIST). MBIST (Memory built-in self-test) provides an effective solution for testing of such large memories. Verification of functioning MBIST is an essential part in any SoC design cycle, as it enables the designer to detect beforehand any issues related to MBIST [11] . The advantages of MBIST are simplicity of test program, Possibility to run different algorithm, Reduction in test cost, Possibility to run user defined algorithm on memories.
Complex Test Pattern Generation for high speed fault diagnosis in FPGA based ...IJMERJOURNAL
ABSTRACT: The memory blocks testing is a separate testing procedure followed in VLSI testing. The memory block testing involves writing a specific bit sequences in the memory locations and reading them again. This type of test is called March test. A particular March test consists of a sequence of writes followed by reads with increasing or decreasing address. For example the March C- test has the following test pattern. There are several test circuits available for testing the memory chips. However no test setup is developed so far for testing the memory blocks inside the FPGA. The BRAM blocks of FPGA are designed to work at much higher frequency than the FPGA core logic. Hence testing the BRAMs at higher speed is essential. The conventional memory test circuits cannot be used for this purpose. Hence the proposed work develops a memory testing tool based on March tests for FPGA based BRAM (block RAM testing). The code modules for March test generator shall be developed in VHDL and shall be synthesized for Xilinx Spartan 3 Family device. A PC based GUI tool shall send command to FPGA using serial port for selecting the type of test. The FPGA core gets the command through UART and performs the appropriate and sends the test report back to PC. The results shall be verified in simulation with Xilinx ISE simulator and also in hardware by using Chip scope. Xilinx Spartan 3 family FPGA board shall be used for hardware verification of the developed March test generator
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
OPTIMIZATION OF HEURISTIC ALGORITHMS FOR IMPROVING BER OF ADAPTIVE TURBO CODESIAEME Publication
The third component introduced in the turbo codes improved the code
performance by providing very low error rates for a very wide range of block lengths
and coding rates. But this increased the complexity and the parameters such as
permeability and permittivity rates were constant and they could not perform well
under noisy environments. This drawback was addressed in [1] by proposing A3DTC.
The bit error rate was minimized by generating parameters based on noise and
signal strengths. A performance comparison is done between the two heuristic
algorithms i.e., Genetic Algorithm and Particle Swarm Optimization Algorithm [2]
where a knowledge source using the two algorithms is generated. Under various noisy
environments the experimental results compare the performance of the two
algorithms. In this paper their performance is analyzed and optimization is done. The
results show that genetic algorithm is able to give better performance when compared
to particle swarm optimization algorithm.
OPTIMIZATION OF HEURISTIC ALGORITHMS FOR IMPROVING BER OF ADAPTIVE TURBO CODESIAEME Publication
The third component introduced in the turbo codes improved the code
performance by providing very low error rates for a very wide range of block lengths
and coding rates. But this increased the complexity and the parameters such as
permeability and permittivity rates were constant and they could not perform well
under noisy environments. This drawback was addressed in [1] by proposing A3DTC.
The bit error rate was minimized by generating parameters based on noise and
signal strengths. A performance comparison is done between the two heuristic
algorithms i.e., Genetic Algorithm and Particle Swarm Optimization Algorithm [2]
where a knowledge source using the two algorithms is generated. Under various noisy
environments the experimental results compare the performance of the two
algorithms. In this paper their performance is analyzed and optimization is done. The
results show that genetic algorithm is able to give better performance when compared
to particle swarm optimization algorithm
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
implementation of area efficient high speed eddr architectureKumar Goud
Abstract-This project presents an EDDR design, based on the residue-and-quotient (RQ) code, to embed into motion estimation (ME) for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the EDDR design. The proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. The functional verification and synthesis can be done by Xilinx ISE. That is when compare to the existing design the implemented design area and timing will be reduced.
Index Terms—Area overhead, data recovery, error detection, reliability, residue-and-quotient (RQ) code, Xilinx ISE
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
Specification-Based Test Program Generation for ARM VMSAv8-64 MMUsAlexander Kamkin
In this work, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.
Test Scheduling of Core Based SOC Using Greedy AlgorithmIJERA Editor
Escalating increase in the level of integration has led the design engineers to embed the pre-design and pre-verified logic blocks on chip to make a complete system on chip (SoC) technology. This advancing technology trend has led to new challenges for the design and test engineers. To ensure the testability of the entire system, the test planning needs to be done during design phase. To save the test cost, the test application time needs to be reduced which requires the test to be done concurrently. However the parallel running of test of multiple cores increases the power dissipation. This thereby leads to make test optimization to take care of time and power. This paper presents an approach for the scheduling the cores with the test time, power, test access mechanism and bandwidth constraint based on greedy algorithm. The TAM allotment to the various cores is done dynamically to save the test time and utilize the full bandwidth. Scheduling is done on ITC’02 benchmark circuits. Experiments on these ITC’02 benchmark circuits show that this algorithm offers lower test application time compared to the multiple constraint driven system-on-chip.
Because of the rapid growth in technology breakthroughs, including
multimedia and cell phones, Telugu character recognition (TCR) has recently
become a popular study area. It is still necessary to construct automated and
intelligent online TCR models, even if many studies have focused on offline
TCR models. The Telugu character dataset construction and validation using
an Inception and ResNet-based model are presented. The collection of 645
letters in the dataset includes 18 Achus, 38 Hallus, 35 Othulu, 34×16
Guninthamulu, and 10 Ankelu. The proposed technique aims to efficiently
recognize and identify distinctive Telugu characters online. This model's main
pre-processing steps to achieve its goals include normalization, smoothing,
and interpolation. Improved recognition performance can be attained by using
stochastic gradient descent (SGD) to optimize the model's hyperparameters.
Scientific workload execution on a distributed computing platform such as a
cloud environment is time-consuming and expensive. The scientific workload
has task dependencies with different service level agreement (SLA)
prerequisites at different levels. Existing workload scheduling (WS) designs
are not efficient in assuring SLA at the task level. Alongside, induces higher
costs as the majority of scheduling mechanisms reduce either time or energy.
In reducing, cost both energy and makespan must be optimized together for
allocating resources. No prior work has considered optimizing energy and
processing time together in meeting task level SLA requirements. This paper
presents task level energy and performance assurance-workload scheduling
(TLEPA-WS) algorithm for the distributed computing environment. The
TLEPA-WS guarantees energy minimization with the performance
requirement of the parallel application under a distributed computational
environment. Experiment results show a significant reduction in using energy
and makespan; thereby reducing the cost of workload execution in comparison
with various standard workload execution models.
More Related Content
Similar to Automatic generation of user-defined test algorithm description file for memory BIST implementation
A review paper on memory fault models and test algorithmsjournalBEEI
Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.
IMPLEMENTATION AND VALIDATION OF MEMORY BUILT IN SELF TEST (MBIST) - SURVEYIAEME Publication
This paper provides a survey of Implementation and Validation involved in Memory Built in Self-Test (MBIST). This paper comprises of the various strategies involved in the implementation and Validation of the Memory Built in Self-Test (MBIST). MBIST (Memory built-in self-test) provides an effective solution for testing of such large memories. Verification of functioning MBIST is an essential part in any SoC design cycle, as it enables the designer to detect beforehand any issues related to MBIST [11] . The advantages of MBIST are simplicity of test program, Possibility to run different algorithm, Reduction in test cost, Possibility to run user defined algorithm on memories.
Complex Test Pattern Generation for high speed fault diagnosis in FPGA based ...IJMERJOURNAL
ABSTRACT: The memory blocks testing is a separate testing procedure followed in VLSI testing. The memory block testing involves writing a specific bit sequences in the memory locations and reading them again. This type of test is called March test. A particular March test consists of a sequence of writes followed by reads with increasing or decreasing address. For example the March C- test has the following test pattern. There are several test circuits available for testing the memory chips. However no test setup is developed so far for testing the memory blocks inside the FPGA. The BRAM blocks of FPGA are designed to work at much higher frequency than the FPGA core logic. Hence testing the BRAMs at higher speed is essential. The conventional memory test circuits cannot be used for this purpose. Hence the proposed work develops a memory testing tool based on March tests for FPGA based BRAM (block RAM testing). The code modules for March test generator shall be developed in VHDL and shall be synthesized for Xilinx Spartan 3 Family device. A PC based GUI tool shall send command to FPGA using serial port for selecting the type of test. The FPGA core gets the command through UART and performs the appropriate and sends the test report back to PC. The results shall be verified in simulation with Xilinx ISE simulator and also in hardware by using Chip scope. Xilinx Spartan 3 family FPGA board shall be used for hardware verification of the developed March test generator
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
OPTIMIZATION OF HEURISTIC ALGORITHMS FOR IMPROVING BER OF ADAPTIVE TURBO CODESIAEME Publication
The third component introduced in the turbo codes improved the code
performance by providing very low error rates for a very wide range of block lengths
and coding rates. But this increased the complexity and the parameters such as
permeability and permittivity rates were constant and they could not perform well
under noisy environments. This drawback was addressed in [1] by proposing A3DTC.
The bit error rate was minimized by generating parameters based on noise and
signal strengths. A performance comparison is done between the two heuristic
algorithms i.e., Genetic Algorithm and Particle Swarm Optimization Algorithm [2]
where a knowledge source using the two algorithms is generated. Under various noisy
environments the experimental results compare the performance of the two
algorithms. In this paper their performance is analyzed and optimization is done. The
results show that genetic algorithm is able to give better performance when compared
to particle swarm optimization algorithm.
OPTIMIZATION OF HEURISTIC ALGORITHMS FOR IMPROVING BER OF ADAPTIVE TURBO CODESIAEME Publication
The third component introduced in the turbo codes improved the code
performance by providing very low error rates for a very wide range of block lengths
and coding rates. But this increased the complexity and the parameters such as
permeability and permittivity rates were constant and they could not perform well
under noisy environments. This drawback was addressed in [1] by proposing A3DTC.
The bit error rate was minimized by generating parameters based on noise and
signal strengths. A performance comparison is done between the two heuristic
algorithms i.e., Genetic Algorithm and Particle Swarm Optimization Algorithm [2]
where a knowledge source using the two algorithms is generated. Under various noisy
environments the experimental results compare the performance of the two
algorithms. In this paper their performance is analyzed and optimization is done. The
results show that genetic algorithm is able to give better performance when compared
to particle swarm optimization algorithm
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
implementation of area efficient high speed eddr architectureKumar Goud
Abstract-This project presents an EDDR design, based on the residue-and-quotient (RQ) code, to embed into motion estimation (ME) for video coding testing applications. An error in processing elements (PEs), i.e. key components of a ME, can be detected and recovered effectively by using the EDDR design. The proposed EDDR design for ME testing can detect errors and recover data with an acceptable area overhead and timing penalty. The functional verification and synthesis can be done by Xilinx ISE. That is when compare to the existing design the implemented design area and timing will be reduced.
Index Terms—Area overhead, data recovery, error detection, reliability, residue-and-quotient (RQ) code, Xilinx ISE
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
Specification-Based Test Program Generation for ARM VMSAv8-64 MMUsAlexander Kamkin
In this work, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.
Test Scheduling of Core Based SOC Using Greedy AlgorithmIJERA Editor
Escalating increase in the level of integration has led the design engineers to embed the pre-design and pre-verified logic blocks on chip to make a complete system on chip (SoC) technology. This advancing technology trend has led to new challenges for the design and test engineers. To ensure the testability of the entire system, the test planning needs to be done during design phase. To save the test cost, the test application time needs to be reduced which requires the test to be done concurrently. However the parallel running of test of multiple cores increases the power dissipation. This thereby leads to make test optimization to take care of time and power. This paper presents an approach for the scheduling the cores with the test time, power, test access mechanism and bandwidth constraint based on greedy algorithm. The TAM allotment to the various cores is done dynamically to save the test time and utilize the full bandwidth. Scheduling is done on ITC’02 benchmark circuits. Experiments on these ITC’02 benchmark circuits show that this algorithm offers lower test application time compared to the multiple constraint driven system-on-chip.
Similar to Automatic generation of user-defined test algorithm description file for memory BIST implementation (20)
Because of the rapid growth in technology breakthroughs, including
multimedia and cell phones, Telugu character recognition (TCR) has recently
become a popular study area. It is still necessary to construct automated and
intelligent online TCR models, even if many studies have focused on offline
TCR models. The Telugu character dataset construction and validation using
an Inception and ResNet-based model are presented. The collection of 645
letters in the dataset includes 18 Achus, 38 Hallus, 35 Othulu, 34×16
Guninthamulu, and 10 Ankelu. The proposed technique aims to efficiently
recognize and identify distinctive Telugu characters online. This model's main
pre-processing steps to achieve its goals include normalization, smoothing,
and interpolation. Improved recognition performance can be attained by using
stochastic gradient descent (SGD) to optimize the model's hyperparameters.
Scientific workload execution on a distributed computing platform such as a
cloud environment is time-consuming and expensive. The scientific workload
has task dependencies with different service level agreement (SLA)
prerequisites at different levels. Existing workload scheduling (WS) designs
are not efficient in assuring SLA at the task level. Alongside, induces higher
costs as the majority of scheduling mechanisms reduce either time or energy.
In reducing, cost both energy and makespan must be optimized together for
allocating resources. No prior work has considered optimizing energy and
processing time together in meeting task level SLA requirements. This paper
presents task level energy and performance assurance-workload scheduling
(TLEPA-WS) algorithm for the distributed computing environment. The
TLEPA-WS guarantees energy minimization with the performance
requirement of the parallel application under a distributed computational
environment. Experiment results show a significant reduction in using energy
and makespan; thereby reducing the cost of workload execution in comparison
with various standard workload execution models.
Investigating human subjects is the goal of predicting human emotions in the
real world scenario. A significant number of psychological effects require
(feelings) to be produced, directly releasing human emotions. The
development of effect theory leads one to believe that one must be aware of
one's sentiments and emotions to forecast one's behavior. The proposed line
of inquiry focuses on developing a reliable model incorporating
neurophysiological data into actual feelings. Any change in emotional affect
will directly elicit a response in the body's physiological systems. This
approach is named after the notion of Gaussian mixture models (GMM). The
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labels, and coincidental responses with training samples all directly impact the
outcomes that are accomplished. In terms of statistical parameters such as
population mean and standard deviation, the suggested method is evaluated
compared to a technique considered to be state-of-the-art. The proposed
system determines an individual's emotional state after a minimum of 6
iterative learning using the Gaussian expectation-maximization (GEM)
statistical model, in which the iterations tend to continue to zero error. Perhaps
each of these improves predictions while simultaneously increasing the
amount of value extracted.
Early diagnosis of cancers is a major requirement for patients and a
complicated job for the oncologist. If it is diagnosed early, it could have made
the patient more likely to live. For a few decades, fuzzy logic emerged as an
emphatic technique in the identification of diseases like different types of
cancers. The recognition of cancer diseases mostly operated with inexactness,
inaccuracy, and vagueness. This paper aims to design the fuzzy expert system
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free PSA (%FPSA) are used to determine prostate cancer risk (PCR), while
PCR serves as an output parameter. Mamdani fuzzy inference method is used
to calculate a range of PCR. The system provides a scale of risk of prostate
cancer and clears the path for the oncologist to determine whether their
patients need a biopsy. This system is fast as it requires minimum calculation
and hence comparatively less time which reduces mortality and morbidity and
is more reliable than other economic systems and can be frequently used by
doctors.
The biomedical profession has gained importance due to the rapid and accurate diagnosis of clinical patients using computer-aided diagnosis (CAD) tools.
The diagnosis and treatment of Alzheimer’s disease (AD) using complementary multimodalities can improve the quality of life and mental state of patients.
In this study, we integrated a lightweight custom convolutional neural network
(CNN) model and nature-inspired optimization techniques to enhance the performance, robustness, and stability of progress detection in AD. A multi-modal
fusion database approach was implemented, including positron emission tomography (PET) and magnetic resonance imaging (MRI) datasets, to create a fused
database. We compared the performance of custom and pre-trained deep learning models with and without optimization and found that employing natureinspired algorithms like the particle swarm optimization algorithm (PSO) algorithm significantly improved system performance. The proposed methodology,
which includes a fused multimodality database and optimization strategy, improved performance metrics such as training, validation, test accuracy, precision, and recall. Furthermore, PSO was found to improve the performance of
pre-trained models by 3-5% and custom models by up to 22%. Combining different medical imaging modalities improved the overall model performance by
2-5%. In conclusion, a customized lightweight CNN model and nature-inspired
optimization techniques can significantly enhance progress detection, leading to
better biomedical research and patient care.
Class imbalance is a pervasive issue in the field of disease classification from
medical images. It is necessary to balance out the class distribution while training a model. However, in the case of rare medical diseases, images from affected
patients are much harder to come by compared to images from non-affected
patients, resulting in unwanted class imbalance. Various processes of tackling
class imbalance issues have been explored so far, each having its fair share of
drawbacks. In this research, we propose an outlier detection based image classification technique which can handle even the most extreme case of class imbalance. We have utilized a dataset of malaria parasitized and uninfected cells. An
autoencoder model titled AnoMalNet is trained with only the uninfected cell images at the beginning and then used to classify both the affected and non-affected
cell images by thresholding a loss value. We have achieved an accuracy, precision, recall, and F1 score of 98.49%, 97.07%, 100%, and 98.52% respectively,
performing better than large deep learning models and other published works.
As our proposed approach can provide competitive results without needing the
disease-positive samples during training, it should prove to be useful in binary
disease classification on imbalanced datasets.
Recently, plant identification has become an active trend due to encouraging
results achieved in plant species detection and plant classification fields
among numerous available plants using deep learning methods. Therefore,
plant classification analysis is performed in this work to address the problem
of accurate plant species detection in the presence of multiple leaves together,
flowers, and noise. Thus, a convolutional neural network based deep feature
learning and classification (CNN-DFLC) model is designed to analyze
patterns of plant leaves and perform classification using generated finegrained feature weights. The proposed CNN-DFLC model precisely estimates
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blocks are utilized to design the proposed CNN-DFLC model. Fine-grained
feature weights are obtained using convolutional and pooling layers. The
obtained feature maps in training are utilized to predict labels and model
performance is tested on the Vietnam plant image (VPN-200) dataset. This
dataset consists of a total number of 20,000 images and testing results are
achieved in terms of classification accuracy, precision, recall, and other
performance metrics. The mean classification accuracy obtained using the
proposed CNN-DFLC model is 96.42% considering all 200 classes from the
VPN-200 dataset.
Big data as a service (BDaaS) platform is widely used by various
organizations for handling and processing the high volume of data generated
from different internet of things (IoT) devices. Data generated from these IoT
devices are kept in the form of big data with the help of cloud computing
technology. Researchers are putting efforts into providing a more secure and
protected access environment for the data available on the cloud. In order to
create a safe, distributed, and decentralised environment in the cloud,
blockchain technology has emerged as a useful tool. In this research paper, we
have proposed a system that uses blockchain technology as a tool to regulate
data access that is provided by BDaaS platforms. We are securing the access
policy of data by using a modified form of ciphertext policy-attribute based
encryption (CP-ABE) technique with the help of blockchain technology. For
secure data access in BDaaS, algorithms have been created using a mix of CPABE with blockchain technology. Proposed smart contract algorithms are
implemented using Eclipse 7.0 IDE and the cloud environment has been
simulated on CloudSim tool. Results of key generation time, encryption time,
and decryption time has been calculated and compared with access control
mechanism without blockchain technology.
Internet of things (IoT) has become one of the eminent phenomena in human
life along with its collaboration with wireless sensor networks (WSNs), due
to enormous growth in the domain; there has been a demand to address the
various issues regarding it such as energy consumption, redundancy, and
overhead. Data aggregation (DA) is considered as the basic mechanism to
minimize the energy efficiency and communication overhead; however,
security plays an important role where node security is essential due to the
volatile nature of WSN. Thus, we design and develop proximate node aware
secure data aggregation (PNA-SDA). In the PNA-SDA mechanism, additional
data is used to secure the original data, and further information is shared with
the proximate node; moreover, further security is achieved by updating the
state each time. Moreover, the node that does not have updated information is
considered as the compromised node and discarded. PNA-SDA is evaluated
considering the different parameters like average energy consumption, and
average deceased node; also, comparative analysis is carried out with the
existing model in terms of throughput and correct packet identification.
Drones provide an alternative progression in protection submissions since
they are capable of conducting autonomous seismic investigations. Recent
advancement in unmanned aerial vehicle (UAV) communication is an internet
of a drone combined with 5G networks. Because of the quick utilization of
rapidly progressed registering frameworks besides 5G officialdoms, the
information from the user is consistently refreshed and pooled. Thus, safety
or confidentiality is vital among clients, and a proficient substantiation
methodology utilizing a vigorous sanctuary key. Conventional procedures
ensure a few restrictions however taking care of the assault arrangements in
information transmission over the internet of drones (IOD) environmental
frameworks. A unique hyperelliptical curve (HEC) cryptographically based
validation system is proposed to provide protected data facilities among
drones. The proposed method has been compared with the existing methods
in terms of packet loss rate, computational cost, and delay and thereby
provides better insight into efficient and secure communication. Finally, the
simulation results show that our strategy is efficient in both computation and
communication.
Monitoring behavior, numerous actions, or any such information is considered
as surveillance and is done for information gathering, influencing, managing,
or directing purposes. Citizens employ surveillance to safeguard their
communities. Governments do this for the purposes of intelligence collection,
including espionage, crime prevention, the defense of a method, a person, a
group, or an item; or the investigation of criminal activity. Using an internet
of things (IoT) rover, the area will be secured with better secrecy and
efficiency instead of humans, will provide an additional safety step. In this
paper, there is a discussion about an IoT rover for remote surveillance based
around a Raspberry Pi microprocessor which will be able to monitor a
closed/open space. This rover will allow safer survey operations and would
help to reduce the risks involved with it.
In a world where climate change looms large the spotlight often shines on
greenhouse gases, but the shadow of man-made aerosols should not be
underestimated. These tiny particles play a pivotal role in disrupting Earth's
radiative equilibrium, yet many mysteries surround their influence on various
physical aspects of our planet. The root of these mysteries lies in the limited
data we have on aerosol sources, formation processes, conversion dynamics,
and collection methods. Aerosols, composed of particulate matter (PM),
sulfates, and nitrates, hold significant sway across the hemisphere. Accurate
measurement demands the refinement of in-situ, satellite, and ground-based
techniques. As aerosols interact intricately with the environment, their full
impact remains an enigma. Enter a groundbreaking study in Morocco that
dared to compare an internet of thing (IoT) system with satellite-based
atmospheric models, with a focus on fine particles below 10 and 2.5
micrometers in diameter. The initial results, particularly in regions abundant
with extraction pits, shed light on the IoT system's potential to decode
aerosols' role in the grand narrative of climate change. These findings inspire
hope as we confront the formidable global challenge of climate change.
The use of technology has a significant impact to reduce the consequences of
accidents. Sensors, small components that detect interactions experienced by
various components, play a crucial role in this regard. This study focuses on
how the MPU6050 sensor module can be used to detect the movement of
people who are falling, defined as the inability of the lower body, including
the hips and feet, to support the body effectively. An airbag system is
proposed to reduce the impact of a fall. The data processing method in this
study involves the use of a threshold value to identify falling motion. The
results of the study have identified a threshold value for falling motion,
including an acceleration relative (AR) value of less than or equal to 0.38 g,
an angle slope of more than or equal to 40 degrees, and an angular velocity
of more than or equal to 30 °/s. The airbag system is designed to inflate
faster than the time of impact, with a gas flow rate of 0.04876 m3
/s and an
inflating time of 0.05 s. The overall system has a specificity value of 100%,
a sensitivity of 85%, and an accuracy of 94%.
The fundamental principle of the paper is that the soil moisture sensor obtains
the moisture content level of the soil sample. The water pump is automatically
activated if the moisture content is insufficient, which causes water to flow
into the soil. The water pump is immediately turned off when the moisture
content is high enough. Smart home, smart city, smart transportation, and
smart farming are just a few of the new intelligent ideas that internet of things
(IoT) includes. The goal of this method is to increase productivity and
decrease manual labour among farmers. In this paper, we present a system for
monitoring and regulating water flow that employs a soil moisture sensor to
keep track of soil moisture content as well as the land’s water level to keep
track of and regulate the amount of water supplied to the plant. The device
also includes an automated led lighting system.
In order to provide sensing services to low-powered IoT devices, wireless sensor networks (WSNs) organize specialized transducers into networks. Energy usage is one of the most important design concerns in WSN because it is very hard to replace or recharge the batteries in sensor nodes. For an energy-constrained network, the clustering technique is crucial in preserving battery life. By strategically selecting a cluster head (CH), a network's load can be balanced, resulting in decreased energy usage and extended system life. Although clustering has been predominantly used in the literature, the concept of chain-based clustering has not yet been explored. As a result, in this paper, we employ a chain-based clustering architecture for data dissemination in the network. Furthermore, for CH selection, we employ the coati optimisation algorithm, which was recently proposed and has demonstrated significant improvement over other optimization algorithms. In this method, the parameters considered for selecting the CH are energy, node density, distance, and the network’s average energy. The simulation results show tremendous improvement over the competitive cluster-based routing algorithms in the context of network lifetime, stability period (first node dead), transmission rate, and the network's power reserves.
The construction industry is an industry that is always surrounded by
uncertainties and risks. The industry is always associated with a threatindustry which has a complex, tedious layout and techniques characterized by
unpredictable circumstances. It comprises a variety of human talents and the
coordination of different areas and activities associated with it. In this
competitive era of the construction industry, delays and cost overruns of the
project are often common in every project and the causes of that are also
common. One of the problems which we are trying to cater to is the improper
handling of materials at the construction site. In this paper, we propose
developing a system that is capable of tracking construction material on site
that would benefit the contractor and client for better control over inventory
on-site and to minimize loss of material that occurs due to theft and misplacing
of materials.
Today, health monitoring relies heavily on technological advancements. This
study proposes a low-power wide-area network (LPWAN) based, multinodal
health monitoring system to monitor vital physiological data. The suggested
system consists of two nodes, an indoor node, and an outdoor node, and the
nodes communicate via long range (LoRa) transceivers. Outdoor nodes use an
MPU6050 module, heart rate, oxygen pulse, temperature, and skin resistance
sensors and transmit sensed values to the indoor node. We transferred the data
received by the master node to the cloud using the Adafruit cloud service. The
system can operate with a coverage of 4.5 km, where the optimal distance
between outdoor sensor nodes and the indoor master node is 4 km. To further
predict fall detection, various machine learning classification techniques have
been applied. Upon comparing various classifier techniques, the decision tree
method achieved an accuracy of 0.99864 with a training and testing ratio of
70:30. By developing accurate prediction models, we can identify high-risk
individuals and implement preventative measures to reduce the likelihood of
a fall occurring. Remote monitoring of the health and physical status of elderly
people has proven to be the most beneficial application of this technology.
The effectiveness of adaptive filters are mainly dependent on the design
techniques and the algorithm of adaptation. The most common adaptation
technique used is least mean square (LMS) due its computational simplicity.
The application depends on the adaptive filter configuration used and are well
known for system identification and real time applications. In this work, a
modified delayed μ-law proportionate normalized least mean square
(DMPNLMS) algorithm has been proposed. It is the improvised version of the
µ-law proportionate normalized least mean square (MPNLMS) algorithm.
The algorithm is realized using Ladner-Fischer type of parallel prefix
logarithmic adder to reduce the silicon area. The simulation and
implementation of very large-scale integration (VLSI) architecture are done
using MATLAB, Vivado suite and complementary metal–oxide–
semiconductor (CMOS) 90 nm technology node using Cadence RTL and
Genus Compiler respectively. The DMPNLMS method exhibits a reduction
in mean square error, a higher rate of convergence, and more stability. The
synthesis results demonstrate that it is area and delay effective, making it
practical for applications where a faster operating speed is required.
The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.
The global agriculture system faces significant challenges in meeting the
growing demand for food production, particularly given projections that the
world's population will reach 70% by 2050. Hydroponic farming is an
increasingly popular technique in this field, offering a promising solution to
these challenges. This paper will present the improvement of the current
traditional hydroponic method by providing a system that can be used to
monitor and control the important element in order to help the plant grow up
smoothly. This proposed system is quite efficient and user-friendly that can
be used by anyone. This is a combination of a traditional hydroponic system,
an automatic control system and a smartphone. The primary objective is to
develop a smart system capable of monitoring and controlling potential
hydrogen (pH) levels, a key factor that affects hydroponic plant growth.
Ultimately, this paper offers an alternative approach to address the challenges
of the existing agricultural system and promote the production of clean,
disease-free, and healthy food for a better future.
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Automatic generation of user-defined test algorithm description file for memory BIST implementation
1. International Journal of Reconfigurable and Embedded Systems (IJRES)
Vol. 11, No. 2, July 2022, pp. 103~114
ISSN: 2089-4864, DOI: 10.11591/ijres.v11.i2.pp103-114 103
Journal homepage: http://ijres.iaescore.com
Automatic generation of user-defined test algorithm description
file for memory BIST implementation
Aiman Zakwan Jidin1,2
, Razaidi Hussin1
, Lee Weng Fook3
, Mohd Syafiq Mispan2
, Loh Wan Ying1
1
Faculty of Electronics Engineering Technology, Universiti Malaysia Perlis, Perlis, Malaysia
2
Faculty of Electrical and Electronics Engineering Technology, Universiti Teknikal Malaysia Melaka, Melaka, Malaysia
3
Emerald System Design Center, Penang, Malaysia
Article Info ABSTRACT
Article history:
Received Jan 13, 2022
Revised Feb 15, 2022
Accepted Mar 11, 2022
Memory built-in self-test (BIST) is a widely used technique to allow the
self-test and self-checking of the embedded memories on chips after the
fabrication process. It can be used by implementing a standard testing
algorithm available in the EDA tool library or a user-defined algorithm
(UDA). This paper presents the development of software that automatically
generates a description file of a UDA to be deployed for memory BIST
circuit implementation using Tessent memory BIST software. It comprises
the test setup and also the microprogram coding for each instruction to be
executed when performing tests on embedded memories. The proposed
automation software was tested by using March SR as the input algorithm
and the results obtained from the simulations show that the output test
patterns generated by the implemented memory BIST match the expected
patterns and passed all the tests, which validated the correct functionality of
the UDA description file generation. The proposed automation software also
fast generation the UDA description file, which was completed in less than
500 ms.
Keywords:
Automation software
March algorithm
Memory BIST
Memory fault models
User-defined algorithm
This is an open access article under the CC BY-SA license.
Corresponding Author:
Razaidi Hussin
Faculty of Electronics Engineering Technology, Universiti Malaysia Perlis
06100 Arau, Perlis, Malaysia
Email: shidee@unimap.edu.my
1. INTRODUCTION
The process to test the embedded memories on a chip is becoming more challenging nowadays,
since they are becoming more compact and more defects which may randomly happen since the introduction
of the very deep submicron (VDSM) technologies [1]–[6]. Furthermore, it becomes more important than ever
since the chips are now memory-dominant, where some studies show that up to 90% of the chip area is
occupied by the memories [7]–[10]. Memory built-in self-test (BIST) is a technique that is very widely used
for embedded memory testing. It offers several advantages such as the ability to perform self-test and self-
check of the output responses without the use of an expensive external tester, and the ability to perform tests
on multiple memories in parallel, which allow the reduction in overall test cost and test duration, respectively
[8], [11]–[15]. Its efficiency in terms of the fault coverage and also the test duration depends on the test
algorithm being used for its implementation [16].
A memory BIST can be implemented by using an electronic design automation (EDA) tool like
Mentor Graphics Tessent software. It can be implemented by using either a standard test algorithm available
in the EDA library or by using a user-defined algorithm (UDA) [17]. A UDA is an algorithm which is
customized for a specific target, either to have a low test length or to have an optimized detection on a
2. ISSN: 2089-4864
Int J Reconfigurable & Embedded Syst, Vol. 11, No. 2, July 2022: 103-114
104
specific set of faults. To use a UDA when implementing a memory BIST circuit, a description file is
necessary to define a custom algorithm and to describe its behavior such as the test setup and the
microprogram coding of each instruction to be executed during memory testing. In addition, a UDA can be
either hard-coded or soft-coded in the memory BIST implementation. While the former offers
design simplicity, the latter offers more flexibility where test algorithms can be changed during program
execution [18].
This paper presents the development of automation software which generates a description file of an
input UDA to be hard-coded for memory BIST implementation in Tessent memory BIST software, to reduce
human effort in obtaining a correct description file of a UDA in a very brief delay. This was achieved by
automatically extracting test operation sequences of the UDA and mapping the test sequences of each test
element of the UDA to the corresponding operation name and the values of the related parameters to be
written into the UDA description file.
Section 2 describes the test algorithm’s test operation sequences. Then, Section 3 describes the
contents of the UDA description file which is utilizable in the Tessent memory BIST software. Section 4
discusses the process flow of the proposed automation software. Finally, Section 5 observed and analyzed the
outputs of the simulation performed on the implemented memory BIST circuit using the generated UDA
description file. This paper is focusing only on the March-series test algorithm, with a test complexity lesser
than 22N, where N is the size of the memory. March SR algorithm, with 14N test complexity, is used for
elaboration and demonstration purposes since it consists of different test elements with different test
sequences, test lengths, and test address directions, which is useful for testing the proposed automation
software.
2. MARCH ALGORITHM AS UDA FOR MEMORY BIST IMPLEMENTATION
2.1. March algorithm description
Table 1 describes the symbol used in the test algorithm test operation sequence notation [3], [19]–
[23]. In general, a March algorithm consists of m test elements, each of them separated by a semicolon.
A test element consists of a set of test operations to be carried out on each cell, starting from the minimum
address until the maximum address (in the case of ascending address order) or vice-versa (in the case of
descending address direction), before proceeding to the next test element. The test operation can be either a
read (r) or a write (w) operation, using only two possible test values (logic 0 or logic 1) called the data
backgrounds [24], [25].
Table 1. The description of the symbols used in the memory testing algorithm notation
Symbol Description
↑ or ⇑ address sequence changes in ascending order
↓ or ⇓ address sequence changes in descending order
↕ or ⇕ address sequence can change either way
R0 or r0 read operation (reading a 0 from a cell)
R1 or r1 read operation (reading a 1 from a cell)
W0 or w0 write operation (writing a 0 to a cell)
W1 or w1 write operation (writing a 1 to a cell)
; test element separator
A March algorithm consists of multiple test elements, each of which is separated by a semicolon.
Each test element will be executed sequentially, starting from the first test element until the final test
element. In the example of March SR algorithm with the test operation sequences ⇑(w0); ⇑(r0, w1, r1, w0);
⇑(r0, r0); ⇑(w1); ⇓(r1, w0, r0, w1); ⇓(r1, r1) [26]. It consists of 6 test elements, notated as M(i) where i = {0,
1, 2, 3, 4, 5}. As can be seen, M(0) to M(3) have the ascending address order, where the test operations will
be executed starting from the memory cell with the minimum address. While M(4) and M(5) have the
descending address order, where the test operations will be executed starting from the memory cell with the
maximum address. Since it has in total of 14 test operations, the test complexity of the March SR algorithm is
14N.
In the March SR algorithm, all cells will be initialized to 0 first in ascending address order during
M(0). Then, in M(1), each cell will be read (expecting 0), written to 1, read (expecting 1), and rewritten to 0
starting from the cell with the minimum address. Next, each cell, starting from the cell with the minimum
address, will be read twice (both expecting 0) in M(2). In M(3), all cells will be written to 1 in the ascending
address order. After that, each cell, starting from the cell with the maximum address, will be read (expecting
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1), written to 0, read (expecting 0), and rewritten to 1 in M(4). Finally, in M(5), each cell, starting from the
cell with the minimum address, will be read twice (both expecting 1).
2.2. UDA Tessent Core Description (TCD) file
The TCD file is the configuration data syntax that is used to describe the modules in the Mentor
Graphics Tessent software such as the memories, boundary scan segments, and fusebox. For memory BIST
implementation purposes, a TCD file is necessary to specify the behavior of the memory e.g. the module
name, the number of words, and the memory type (ROM, SRAM, or DRAM). Furthermore, in the case of the
memory BIST implementation with UDA, an additional TCD file is needed to describe the memory test
algorithm which will be hard-coded into the BIST controller. The TCD files for memory BIST are
recognized with the .tcd_mem_lib extension [17].
For UDA description, the TCD file contains the test setup and the microprogram coding of each
instruction to be executed during memory testing. The test setup consists of information such as the name of
the UDA, the minimum and the maximum row and column addresses, and the selection of the test operation
set. While the microprogram coding describes the test operation sequences of each test element separately, in
terms of the address order (increment or decrement), the write data value, the expected read data value, and
the operation name which are predefined in the operation set library specified in the test setup. The
microprogram coding for each test element is written in the template:
Instruction (M<i>_<test operation sequences>){
OperationSelect: <Operation name>;
X1AddressCmd: <Address Order>;
Y1AddressCmd: <Address Order>;
ExpectDataCmd: <Expect data>;
WriteDataCmd: <Write data>;
NextConditions {
//insert conditions
}
}
For example, the coding for M(2) of March SR algorithm (⇑(r0, r0)) is written as:
Instruction (M2_r0r0){
OperationSelect: ReadRead
X1AddressCmd: Increment;
Y1AddressCmd: Increment;
ExpectDataCmd: DataReg;
NextConditions {
X1_EndCount : on;
Y1_EndCount : on;
}
}
In the case where a test element consists of more than 3 test operations, a special
BranchToInstruction command will be added to the coding, so that it can be coded in two linked
instructions. For example, M(1) of March SR algorithm (⇑(r0, w1, r1, w0)) is written as two linked
instructions M1_r0w1 and M1_r1w0, as:
Instruction (M1_r0w1){
OperationSelect: ReadModifyWrite;
ExpectDataCmd: DataReg;
WriteDataCmd: InverseDataReg;
NextConditions {
}
}
Instruction (M1_r1w0){
OperationSelect: ReadModifyWrite;
X1AddressCmd : Increment;
Y1AddressCmd : Increment;
ExpectDataCmd: InverseDataReg;
WriteDataCmd: DataReg;
BranchToInstruction : M1_r0w1;
NextConditions {
X1_EndCount : on;
Y1_EndCount : on;
}
}
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In addition, a specific instruction InhibitLastAddressCount needs to be added and set its
value to on in the case where a transition between two test elements involves a change in the address
direction, like in the case of the transition between M(3) (increase address order) and M(4) (decrease address
order). This is necessary to prevent the address counter from wrapping around to the minimum address when
the maximum address is reached at the end of M(3). Therefore, at the start of M(4), it will start to count down
from the maximum address. Thus, the microprogram coding of M(3) is written as:
Instruction (M3_w1){
OperationSelect : WriteWriteFastRow;
X1AddressCmd : Increment;
Y1AddressCmd : Increment;
WriteDataCmd : InverseDataReg;
InhibitLastAddressCount : on;
NextConditions {
X1_EndCount : on;
Y1_EndCount : on;
}
}
The description file is unique for each UDA since different algorithms are composed of different
test operation sequences. It is then read by the memory BIST insertion tools, which will extract its test
operation sequences based on the operations, the address directions, the values to be written into the memory
cells, and the expected values to be read from the memory. During the memory BIST implementation
process, this microprogram coding is converted into a memory BIST controller hardware, which is coded in
Verilog HDL.
3. RESEARCH METHODOLOGY
Figure 1 shows the overall process flow of the proposed automation software, which is developed
using the C++ programming language. Upon executing the software, the UDA is read from an input file and
essential information is extracted from it, e.g. the test operation sequences and the number of test elements m.
The input file reading process is done by using the functions available in the file streaming fstream library in
C++. From here, m data structures are created, each of which is dedicated to store the information of each test
element: the address order ao, the test operations rw which stores r or w for read or write operation,
respectively, and the data background db associated to each test operation. In the case of the March SR
algorithm, 6 data structures are created to store the ao, the rw, and the db of each of its test elements, as
described in Table 2.
Table 2. The breakdowns of March SR algorithm test sequences into separated test elements
Test element Address order ao Test operations rw Data backgrounds db
M(0) ⇑ w 0
M(1) ⇑ r, w, r, w 0, 1, 1, 0
M(2) ⇑ r, r 0, 0
M(3) ⇑ w 1
M(4) ⇓ r, w, r, w 1, 0, 0, 1
M(5) ⇓ r, r 1, 1
Next, it opens or creates a new UDA TCD file as the output, which is saved with the .tcd_mem_lib
extension recognized by the Tessent memory BIST tools. Immediately after that, the name of the UDA and
the test setup such as the starting address and the maximum memory address will be defined in the output
file. Then, the automation software determines the operation name and the values of write data, and the
expected read data of the test element to be written in the TCD file, by using the mapping provided in Table
3. The write data and the expected read data only have two possible values: DataReg (logic 0) and
InverseDataReg (logic 1). While the test operations are mapped to the operation names that are available
under the TessentSyncRamOps operation set library [17].
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Figure 1. The process flowchart of the UDA description file generation
Table 3. The mapping of the extracted UDA to the parameters in the TCD file
Extracted data from input UDA Data to be written into TCD file
Test operations rw Data backgrounds db Operation name Write data Expected data
w
0
WriteWriteFastRow
DataReg -
1 InverseDataReg -
r
0
ReadReadFastRow
- DataReg
1 - InverseDataReg
rw
00
ReadModifyWrite
DataReg DataReg
01 InverseDataReg DataReg
10 DataReg InverseDataReg
11 InverseDataReg InverseDataReg
rr
00
ReadRead
- DataReg
11 - InverseDataReg
wr
00
WriteRead
DataReg DataReg
11 InverseDataReg InverseDataReg
rwr
000
ReadWriteRead
DataReg DataReg
111 InverseDataReg InverseDataReg
011
ReadWriteReadInvert
InverseDataReg DataReg
100 DataReg InverseDataReg
After determining these parameters, the microprogram coding of the test element is written to the
output TCD file, by following the template previously discussed in Section 3. These processes are repeated
for all test elements of the UDA. The process flow of determining the operation name, the value of the write
data, and the expected read data for each test element is detailed in Figure 2. The provided flowchart also
shows that if the address order of the current test element ao(i) is different from the one of the next test
element ao(i+1), the value of InhibitLastAddressCount is set to on.
Once all the test elements have been coded and written to the TCD file, the output file is closed and
the software execution ends. The generated TCD file is then copied into the Tessent memory BIST working
directory. It will be read by the tools to be used as the algorithm for memory BIST implementation.
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Figure 2. The process flowchart of determining the operation name and the values of write data and expected
data of each test element
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4. RESULTS AND DISCUSSION
To validate the functionality of the proposed automation software, firstly the test operation
sequences of the March SR algorithm were stored in an input text file named march_SR.txt, to be used as the
input UDA. The proposed automation software was executed by reading the input file, extracting the
information, and producing the microprogram coding of the UDA in the output description file
march_SR.tcd_mem_lib, as shown in Figure 3. It shows that both M(1) and M(4), which consist of 4 test
operations each, require the branching command BranchToInstruction to link up two instructions
together. In addition, the InhibitLastAddressCount command is also added and set to on inside the
instruction M3_w1. By using the gettimeofday()function in the C++ programming language, the
automation execution completion time to generate the UDA TCD file was measured in multiple attempts,
which took less than 500 ms on a PC with a 2.40 GHz microprocessor and 8GB of RAM. However, no
comparison of the completion time is to be made since no previous similar works were published.
Figure 3. The generated description file march_SR.tcd_mem_lib
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The generated TCD file was then read by the Tessent memory BIST tools, and the March SR
algorithm was applied as the UDA for the memory BIST implementation. For this purpose, a simple
arithmetic logic unit (ALU) which contains a 70-word SRAM as the memory instance is used. Figure 4
shows the schematic view of the generated memory BIST circuit. 5 additional modules are added and
connected to the memory instances:
− tessent_mbist_controller, which generates the test addresses and the test inputs according to the UDA
test sequences which are hard-coded inside this module
− tessent_memory_interface, which acts as the interface between the memory BIST controller and the
memory instance
− tessent_mbist_bap, which is the BIST access port to configure the memory BIST controller and to
monitor test pass/fail status
− two tessent_sib instances, the segment insertion bit blocks which act as the switches to include or to
exclude the memory BIST from the IJTAG network on the chip
Figure 4. The generated memory BIST circuit
Once implemented, the memory BIST circuit is simulated in the QuestaSim simulator, by using the
test patterns which are generated during its implementation process. Figure 5 shows the overall waveform of
the simulation performed on the implemented memory BIST. It can be observed that the ERROR flag stays
low throughout the simulation, which indicates that there is no mismatch occurring between the observed
read outputs (dout) and the expected outputs. While the CMP_EN signal is toggling and is high whenever a
comparison between the output read value and the expected value is necessary.
Besides, the simulation also shows that the overall test took 19.6 us to be completed, where the
clock period used for this simulation is 20 ns. From here, the test complexity of the UDA can be derived
using (1).
𝑇𝑒𝑠𝑡 𝐶𝑜𝑚𝑝𝑙𝑒𝑥𝑖𝑡𝑦 =
𝑇𝑒𝑠𝑡 𝐷𝑢𝑟𝑎𝑡𝑖𝑜𝑛
𝑇𝑐𝑙𝑜𝑐𝑘∗𝑁
(1)
In this case, N = 70 which is the size of the memory model used for the test. Hence, the test
complexity of the UDA used for this implementation is equal to 14, which is equal to the expected
complexity of the March SR algorithm (14N) [26].
Figure 5. The overall waveform of the simulation performed on the implemented memory BIST
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Figure 6 to Figure 11 shows the waveform of the simulation, representing the test patterns of each
test element. The waveform in Figure 6 corresponds to the test operation of M(0): ⇑(w0), where all memory
cells are written to 0, starting from address 0 to address 69 (or 45h in hexadecimal). No comparison is needed
at this stage since it is a write-only operation (indicated by CMP_EN = 0). In Figure 7, the waveform
demonstrates that each cell is read first (expecting 0 at the output), written to logic 1, reread (expecting 1 at
the output), and finally written back to logic 0. These processes are executed in ascending address order. This
translates the test operation sequences of M(1): (⇑(r0, w1, r1, w0). The patterns shown in Figure 8
correspond to the M(2): ⇑(r0, r0), where each cell is read twice in the ascending address order and both read
operations are expecting logic 0 at the output.
Figure 6. The simulation waveform represents the patterns of M(0)
Figure 7. The simulation waveform represents the patterns of M(1)
Figure 8. The simulation waveform represents the patterns of M(2)
While Figure 9 shows the patterns executed by M(3): ⇑(w1), where it has almost the same pattern as
test element 0, but logic 1 is written to the cells instead of logic 0. Next, the waveform in Figure 10
corresponds to the patterns of M(4): ⇓(r1, w0, r0, w1), where each cell is read (expecting 1 at the output),
written to logic 0, reread (expecting 0 at the output), and finally written back to logic 1, in the descending
address direction. Finally, the patterns of M(5): ⇓(r1, r1) are translated by the waveform in Figure 11, where
each cell is read twice (expecting logic 1 at the output) in the descending address order.
Figure 9. The simulation waveform represents the patterns of M(3)
Figure 10. The simulation waveform represents the patterns of M(4)
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Figure 11. The simulation waveform represents the patterns of M(5)
Thus, the observed simulation waveforms met the expectations, where the observed test patterns
correspond to the test sequences of the March SR algorithm and no mismatch occurred between the output
values read from the memory and the expected output value, and they proved that the memory BIST circuit
has been successfully implemented by using the UDA description file generated by the proposed automation
software.
For future planning, the mapping provided in Table 3 will be improved by adding more possible
combinations of test operations such as wwr or rww which may exist in test algorithms with higher test
complexity than 22N, to ensure that it can work on as many algorithms as possible. Besides, the UDA
description generation algorithm will be improved to allow the optimization of the UDA microprogram
coding e.g. to reduce the line number or instructions by using the repetition technique. Furthermore, it will
also be tested using various March algorithms with different test sequences and complexities to guarantee its
accuracy and reliability.
5. CONCLUSION
This research paper has presented the development of automation software to automatically generate
a UDA description file to be used for the memory BIST implementation in Tessent memory BIST software.
The proposed automation software was developed by using the C++ programming language and consists of
the reading and extracting information from the input UDA, segregation of test operation sequences into
separated test elements, determination of operation names, write data values, and expected read values to be
written into the output TCD file. The generated file is then read by Tessent memory BIST tools during the
implementation process, and the simulation was performed on the implemented memory BIST circuit, which
produced correct test patterns as per expectation and correspond to the intended test operation sequences. The
proposed automation software allows the generation of the required UDA description file automatically with
a completion time lesser than 500 ms, thus, reducing human effort and time in obtaining a working
description file.
ACKNOWLEDGEMENTS
The authors would like to acknowledge the Faculty of Electronic Engineering Technology,
Universiti Malaysia Perlis (UniMAP), Universiti Teknikal Malaysia Melaka (UTeM), and the Ministry of
Higher Education Malaysia, for their contribution, support to this research, and financial assistance under the
SLAB scheme.
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BIOGRAPHIES OF AUTHORS
Aiman Zakwan Jidin is currently a Ph.D. candidate at Universiti Malaysia Perlis,
Malaysia. His research topic is focusing on optimizing memory testing algorithm efficiency for
improving fault coverage. Previously, he obtained his MEng in Electronic and Microelectronic
System from ESIEE Engineering Paris, France in 2011, before working as FPGA IP Core
Design Engineer at Altera Corporation Malaysia (now part of Intel). He is a full-time lecturer
and researcher at Universiti Teknikal Malaysia Melaka (UTeM), in Electronic and Computer
Engineering. His research interests include DFT, VLSI, and FPGA system design. He can be
contacted at email: aimanzakwan@utem.edu.my.
Razaidi Hussin received a Ph.D. degree in Electronic and Electrical Engineering
from the University of Glasgow, the UK in 2017 with a focus on oxide-reliability issues in
complementary metal-oxide-semiconductor nanoscale devices. He joined Universiti Malaysia
Perlis (previously known as KUKUM) in 2002. He is currently a full-time Senior Lecturer at
the Faculty of Electronic Engineering Technology, Universiti Malaysia Perlis. He can be
contacted at email: shidee@unimap.edu.my.
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Lee Weng Fook is a Technical Director at Emerald Systems Design Center with
26 years of IC Design experience. Lee has vast experience in designing with Verilog and
VHDL, RTL coding, and logic synthesis for ASIC/FPGA/SOC. Lee’s specialization is in
synthesizing and tweaking synthesis for performance and low power, leading to enhanced
methodology to address advanced DFT techniques for VDSM technology, development, and
deployment of low power standard cell libraries. Lee has led the development of new
architectures and micro-architectures for efficient PMSM motion control ASIC and has
developed architectures for AI classification algorithms implementation in ASIC. Lee has
published 4 IC Design books, “Learning from VLSI Design Experience” ISBN: 978-
3030032371 with Springer Press, “VHDL Coding and Logic Synthesis with Synopsys” ISBN:
0-12-440651-3 with Academic Press Publication, “Verilog Coding for Logic Synthesis” ISBN:
0-471-42976-7 with John Wiley Publication and “VLIW Microprocessor Hardware Design for
ASICs and FPGA” ISBN: 978-0071497022 with McGraw Hill Publication. Lee is also the
inventor and co-inventor of 14 design patents granted by the US Patent and Trademark Office
(US Patent # 7,057,949 7,010,736 6,891,752 6,771,093 6,665,214 6,654,349 6,622,274
6,587,982 6,549,477 6,546,410 6,532,175. He can be contacted at email:
seanlee@emersysdesign.com.
Mohd Syafiq Mispan received B.Eng Electrical (Electronics) and M.Eng
Electrical (Computer and Microelectronic System) from Universiti Teknologi Malaysia,
Malaysia in 2007 and 2010 respectively. He had experience working in the semiconductor
industry from 2007 until 2014 before pursuing his Ph.D. degree. He obtained his Ph.D. degree
in Electronics and Electrical Engineering from the University of Southampton, the United
Kingdom in 2018. He is currently a senior lecturer in the Faculty of Electrical and Electronics
Engineering Technology, Universiti Teknikal Malaysia Melaka. His current research interests
include hardware security, CMOS reliability, VLSI design, and Electronic Systems Design. He
can be contacted at email: syafiq.mispan@utem.edu.my.
Loh Wan Ying received her B.Eng Electronic with Honours from University
Tunku Abdul Rahman. Loh is currently a Ph.D. candidate at Universiti Malaysia Perlis,
Malaysia. Her research interest is focusing on improving the efficiency of fault detection by
optimizing memory testing algorithms. Loh has a few years of experience in designing with
Verilog and VHDL, RTL ASIC/IP coding, and FPGA synthesis. Loh also has experience
working with RISC V, AXI bus, and FPGA SoC. Loh has experience in Artificial Intelligence
(AI) frontend design and full-chip verification. She can be contacted at email:
wyloh@studentmail.unimap.edu.my.