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Institute for System Programming of the Russian Academy of Sciences (ISP RAS)
25 Alexander Solzhenitsyn st., Moscow, 10900...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
Specification-Based TPG for ARM VMSA MMUs
Alexander Kamkin et al.
Workshop on Microprocessor Test and Verification
Decembe...
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Specification-Based Test Program Generation for ARM VMSAv8-64 MMUs

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In this work, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.

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Specification-Based Test Program Generation for ARM VMSAv8-64 MMUs

  1. 1. Institute for System Programming of the Russian Academy of Sciences (ISP RAS) 25 Alexander Solzhenitsyn st., Moscow, 109004, Russia | http://www.ispras.ru Specification-Based Test Program Generation for ARM VMSAv8-64 MMUs Alexander Kamkin Mikhail Chupilko, Andrei Tatarnikov Artem Kotsynyak, Alexander Protsenko, Sergey Smolov
  2. 2. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX Test Program Generator MicroTESK ARMv8 2 Specifications Test Programs etc . Specification Analysis Symbolic Execution Constraint Solving MicroTESK Specifications ISA (nML) MMU (SL) other units Test Programs (Assembly) Test Templates (Ruby) ARMv8 Specifications Test Engineers
  3. 3. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX nML Lang. Types, Registers, and Modes 3 // Data Types type BYTE = card(8) // Unsigned type SHORT = int(16) // Signed type DWORD = card(64) // Unsigned ... // Memory Operations let MemOp_LOAD = 0 // Int Constant let MemOp_STORE = 1 // Memory Access Types let AccType_NORMAL = 0 let AccType_ORDERED = 5 let AccType_PTW = 8 ... // Registers and Aliases reg X[32, DWORD] // 32 DWORD Registers reg SP[DWORD] alias = X[31] ... // Register Access Modes mode REG(i: card(5)) = X[i] syntax = format("x%d", i) // E.g. x13 image = format("%5s", i) // E.g. 01101 number = i // User-Defined Attribute ... // Physical Memory Array mem MEM[(2 ** 48) / 8, DWORD]1 2 3
  4. 4. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX nML Lang. Operations and Their Groups 4 // Load-Acquire Register Instruction op LDAR(rt: REG, rn: REG) syntax = // Assembly Format format("ldar %s, [%s, #0]", rt.syntax, if rn.number == 31 then "sp" else rn.syntax endif) image = // Binary Encoding format("1100100011011111111111%5s%5s", rn.image, rt.image) action = { // Instruction Semantics F(MemOp_LOAD, rt, rn, 64, AccType_ORDERED).action; } op F(opc: BYTE, rt: REG, rn: REG, ...) action = { va = rn; // Register Read if opc == MemOp_LOAD then if va<...> != 0 then exception("AlignmentFault"); endif; // Virtual -> Address Translation temp = MEM[va >> 3]; rt = temp<...>; // Register Write ... endif; } // Group of Operations op LOAD = LDR | LDUR | LDAR | ...1 2 3
  5. 5. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX MMU Lang. Address Types and Segments 5 address VA( vaddress : 64, // Virtual Address acctype : 4, // Memory Access Type iswrite : 1, // Store/Load wasaligned : 1, // Aligned/Unaligned size : 6 // Data Portion Size ) address IPA( ipaddress : 48, // Intermediate Address level : 2, // Page Table Level ... secondstage : 1, // Second/First Stage ) address PA( paddress : 48, // Physical Address ... ) // Mapping of VA to PA segment SEG(va: VA) = (pa: PA) range = (0, 0x0000ffffFFFFffff) read = { // Flat Address Translation pa.paddress = va.vaddress<47..0>; ... // Or Table-Based Translation if TLB(va).hit then record = TLB(va); ... pa.paddress = f(record, va) endif; } buffer TLB(va: VA) entry = (...) // TLB Record Format ... // Other Parameters 1 2 3
  6. 6. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX MMU Lang. Set-Associative Buffers 6 // Register-Mapped Buffer register buffer TLB(va: VA) ways = N // Associativity sets = M // Number of Sets tag = f(va) // Tag Function index = g(va) // Index Function policy = none // Eviction Policy entry = ( // Entry Format perms : Permissions, nG : 1, contiguous : 1, blocksize : 32, addrdesc : AddrDesc ) // Memory-Mapped Buffer memory buffer TranslationTable(va: VA) entry = ( IGNORED : 9, // <63..55> XN : 1, // <54> PXN : 1, // <53> Contiguous : 1, // <52> RES0 : 4, // <51..48> pa : 36, // <47..12> nG : 1, // <11> AF : 1, // <10> SH : 2, // <9..8> AP : 2, // <7..6> NS : 1, // <5> AttrIndx : 3, // <4..2> page : 1, // <1> valid : 1 // <0> ) ... 1 2
  7. 7. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX MMU Lang. Memory Management Logic 7 mmu MMU(va: VA) = (data: 64) read = { // Load Operation if va.acctype != AccType_PTW then pa = AArch64TranslateAddress(va); else pa = SEG(va); // Flat Translation endif; if L1(pa).hit then ... else ... if va.acctype != AccType_PTW then temp = AArch64MemSingleRead(va); else temp = MEM(pa); endif; ... endif; data = temp<...>; } write = { ... } // Store Operation } // Translation Table Walk function AArch64TableWalk (...): TLBRecord { if ... then AArch64TranslationFault(); endif; if ... then AArch64AddressSizeFault(); endif; // Level 0 c = AArch64TranslationTableWalkRepeat(c); if c.return_ALL != 1 then // Level 1..3 c = AArch64TranslationTableWalkRepeat(c); endif; ... } // Stage 1 Address Translation function AArch64S1Translate (...): AddrDesc { if S1_ENABLED then S1 = AArch64TranslationTableWalk(...); ... endif; return S1.addrdesc; }1 2 Recursive Call // TranslationTable(va) -> MMU(va) record = TranslationTable(va) 3
  8. 8. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX Start TLB Error Perm TT0 TT1 TT2 TT3 L1 L2Data1 MEMData2Stop StopStop Stop Error Error Perm L1 L2Data1 MEMData2Stop StopStop ErrorPerm L1 L2Data1 MEMData2Stop StopStop Error Perm L1 L2Data1 MEMData2Stop StopStop Error Perm L1 L2Data1 MEMData2Stop StopStop Error Stop Stop Stop Stop Stop Stop Aligned Miss Miss Miss Miss Hit Miss Ok MissHit MissHit Unaligned Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated MicroTESK MMU Execution Paths 8 Control Flow Execution Paths in MMU  4  105 paths 24 path classes
  9. 9. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX MicroTESK Inter-Path Dependencies 9 Start TLB Error Perm TT0 TT1 TT2 TT3 L1 L2Data1 MEMData2Stop StopStop Stop Error Error Perm L1 L2Data1 MEMData2Stop StopStop ErrorPerm L1 L2Data1 MEMData2Stop StopStop Error Perm L1 L2Data1 MEMData2Stop StopStop Error Perm L1 L2Data1 MEMData2Stop StopStop Error Stop Stop Stop Stop Stop Stop Aligned Miss Miss Miss Miss Hit Miss Ok MissHit MissHit Unaligned Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Buffer Usage Conflicts Conflict Types • Index Equal / Not Equal • Tag Equal / Not Equal • Tag Evicted / Not Evicted Cache L1 Way 1 ... Way N Set 1 Tag: Data … Tag: Data … Tag 2: … … Tag 1: … Set M Tag: Data … Tag: Data Address 1 Tag 1 Index 1=2 Offset 1 Address 2 Tag 2 Index 1=2 Offset 2   = =
  10. 10. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX Start TLB Error Perm TT0 TT1 TT2 TT3 L1 L2Data1 MEMData2Stop StopStop Stop Error Error Perm L1 L2Data1 MEMData2Stop StopStop ErrorPerm L1 L2Data1 MEMData2Stop StopStop Error Perm L1 L2Data1 MEMData2Stop StopStop Error Perm L1 L2Data1 MEMData2Stop StopStop Error Stop Stop Stop Stop Stop Stop Aligned Miss Miss Miss Miss Hit Miss Ok MissHit MissHit Unaligned Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Hit Ok MissHit MissHit Violated Ruby Lang. Test Program Templates 10 class MmuTemplate < ArmV8BaseTemplate def run block(:engine => "memory", ...) { ldar reg(_), reg(_) do situation("access", miss ("TLB"), # Constraints hit ("TranslationTable", 0) end stlr reg(_), reg(_) do situation("access", hit ("TLB"), # Constraints miss ("L1"), end } end end 1 Symbolic Execution Constraint Solving
  11. 11. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX Ruby Lang. Register and Buffer Preparators 11 # Default Preparator for # X Registers (REG Mode) preparator(:target => "REG") { movk target, value(0, 15), 0 movk target, value(16, 31), 1 movk target, value(32, 47), 2 movk target, value(48, 63), 3 } # Optimized Preparator preparator(:target => "REG" :mask => "0000XXXXXXXXXXXX") { movz target, value(0, 15), 0 movk target, value(16, 31), 1 movk target, value(32, 47), 2 } # Preparator for Translation Table (Level 0) buffer_preparator( :target => "TranslationTable"){ mrs x0, ttbr0_el1 # Table Base movz x1, address, 0 # Entry Index add_sh_reg x0, x0, x1, LSL, 3 # Entry Address movk x2, entry(0, 15), 0 # Entry<0..15> ... stlr x2, x0 # Write } 1 3 # Preparator for L1 Cache buffer_preparator( :target => "L1") { movz x0, address(0, 15), 0 # Data Address ... ldar x1, x0 # Load Data } 2
  12. 12. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX VMSAv8-64 Case Study Specification Size Description ARMv8 Reference Manual  600 pages Chapters B2, C6, D3, D4, D7, and J8 Formal Specifications (ISA)  3000 lines 85 LD/ST Instructions, and Registers Formal Specifications (MMU)  2000 lines TLB, TranslationTable0-4, and L1-2 12 Characteristic Minimum Maximum Average Number of Transitions in a Path 3 463 422 Number of Variables in a Path Formula 6 1493 1218 Number of Execution Paths per Access  400 000
  13. 13. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX VMSAv8-64 Lessons Learned +Domain-Specific Languages (Specifications in nML/MMUSL) • ease specification analysis and test coverage extraction • simplify learning of the tool +Dynamic Programming Languages (Test Templates in Ruby) • can be extended with test generation constructs • are popular among hardware designers (especially, Python) - Low Performance (Constraint Solving) • Z3, CVC4, etc. require file-based interaction • in-house solver is under development 13
  14. 14. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX MicroTESK Plans for the Future • Technical Tasks • code stabilization, optimization, etc. • user documentation, trainings, etc. • demo versions for widely-spread architectures • Scientific Tasks • test engine composition (memory, branches, etc.) • multicore microprocessors (cache coherence, etc.) • online test program generation (post-silicon verification) 14
  15. 15. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX MicroTESK Contacts 15 http://forge.ispras.ru/projects/microtesk microtesk-support@ispras.ru
  16. 16. Specification-Based TPG for ARM VMSA MMUs Alexander Kamkin et al. Workshop on Microprocessor Test and Verification December 3-4, 2015 | Austin, TX Thank You! Questions? 16

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