The document is an announcement for Synopsys' 2010 Summer Young Tiger Internship Campaign (SYTIC) in Taiwan. It provides details on: 1. The internship program that will offer scholarships for Masters and PhD students from Taiwanese universities to intern at Synopsys' Taiwan R&D center for 2 months over summer 2010. 2. Synopsys' position as a global leader in electronic design automation (EDA) software, and background on its Taiwan R&D center located in Taipei and Hsinchu. 3. Nine internship positions are available focused on EDA software development across various teams, with requirements and contact information provided.

1.
台灣新思科技有限公司
暨 教育部顧問室 VLSI 教改計畫 DAT 聯盟產學合作計劃
2010 Summer Young Tiger Internship Campaign (SYTIC)
主 旨： 本計劃為美商新思科技(Synopsys)為落實培育半導體設計人才，積極參與推動與國內
產、學、研界合作，新思台灣前瞻製程 EDA 研發中心(Advance Process EDA R&D Center)
特邀請 EDA 相關之學術研究機構，推薦研究生至台灣研發中心實習。
公司簡介： 新思科技(Synopsys)【Synopsys Inc. Nasdaq: SNPS】為全球領先之半導體電子設計自動化
(EDA)解決方案提供廠商。總部位於美國加州山景市(Mountain View)，在北美、歐洲、
亞洲與日本等有超過六十個據點，新思科技擁有業界最先進及完整的產品線遍及整個晶
片設計流程，全球半導體及電子產業可用以設計出複雜的積體電路(ICs)、FPGAs 及系統
單 晶 片 (SoCs) 。 如 需 更 詳 盡 資 料 ， 請 參 觀 新 思 科 技 公 司 網 站 :
http://www.synopsys.com 。
研發中心簡介：新思科技台灣研發中心成立於 2004 年，以台灣完整半導體產業雄厚基礎，發展半導
體 EDA 電子設計自動化軟體技術，促使台灣成為新思科技全球佈局策略中的亞洲研發
龍頭。此研發中心現階段的研究發展規劃，為結合台灣晶圓代工製造、封測、IC 設計
優勢，更進一步開發先進奈米製程所需的 EDA 軟體設計技術。目前台灣研發中心總人
數約 140 人，辦公室位於台北市以及竹北市．
實習獎學金： 本公司將提供錄取實習碩博士研究生暑期實習獎學金
(博士生實習獎學金兩個月共計新台幣十萬元 / 碩士生實習獎學金兩個月共計新台幣七
萬元 )
對 象： 經由學術機構推薦之國內各大學相關科系之碩博士研究生
實習期間： 自民國九十九年七月 至 九月十五日間，為期二個月
實習地點： 台灣新思科技台北辦公室 或 新竹辦公室（台北市信義區 或 竹北台元科技園區）
名 額： 九名
推薦方式： 請將英文履歷資料 e‐mail: intern_tw@synopsys.com (Email 主旨請註明: 2010SYTIC，並在
email 內容中列舉想參與的專案編號以及指導教授名稱，專案編號請參閱附件，若提供
教授推薦函更佳)。 報名截止日期為民國 99 年 6 月 15 日止
諮詢窗口： 陳小姐 (Tel: 02‐23453020 ext 52922, Email: denisec@synopsys.com)
實習內容： 請參閱附件說明

2. 專案
專案內容說明 實習對象需求說明
編號
A Hiring Manager: Cindy Shen Requirements:
Intern Job Description: The requirements of the candidate will
1. Learn Synopsys tool ICC Flip‐Chip router; be EE/CS majored and in the senior of
2. Study two different 45‐degree Flip‐Chip undergraduate or
router algorithms; graduate school. VLSI subject
3. Investigate and compare the 45‐degree specialization will be a preference and
routing experiment results for different can quickly learn how to run the
tools. EDA/CAD tool with interested in IC
4. Provide advantage/disadvantage analysis for layout.
two different tools;
Propose suggestions for two different
tools/algorithms.
B Hiring Manager: Cindy Shen Requirements:
Intern Job Description: The requirements of the candidate will
ICC/Flip‐Chip Routing Team: be EE/CS majored and in the senior of
 Learn how to use tool ICC, practically the undergraduate or
routing, chip‐finishing and flip‐chip routing graduate school. VLSI subject
flow. specialization will be a preference and
1. Investigate test data and help on the can quickly learn how to run the
visualization debugging tool. EDA/CAD tool with interested in IC
2. Study two different 45‐degree Flip‐Chip router layout.
algorithms and flows.
3. Help on testing the tool flow and propose
enhanced functionalities.
4. Generate testing data under Synopsys test
data library.
C Hiring Manager: Pamela Liu Requirements:
Intern Job Description: Candidate for this position must have a
Responsible for developing and debugging large BS in CS/EE with at least 1+ year or a
scale EDA software programs in C/C++. MS in CS/EE with 0+ years solid work
experiences programming in C/C++ in a
Linux/Unix environments. He or she
must have experiences developing
complex software projects and be able
to demonstrate good problem solving
and analysis skills. Relevant experiences
developing or using EDA tools is highly
desirable.
D Hiring Manager: Peter Wei Requirements:
Intern Job Description: The candidate is required to have EE or
The goal of this project is to develop a current CS background. Preferred second year
waveform synthesis methodology for Master student or PhD student
microprocessor (ARM) which can be an essential specialized in microarchitecture design.

3. part of PrimeRail macro modeling.
Tasks include:
a. Survey the microprocessor power
simulation technology, and evaluate
possible solutions for PrimeRail.
b. Develop and design a current waveform
synthesis method for PrimeRail dynamic
hard macro model.
The intern can learn and practice the macro
model generation methodology of IR‐drop
analysis through this project.
E Hiring Manager: Peter Wei Requirements: The candidate is
Intern Job Description: required to have EE or CS background.
Intern will investigate distributed processing of Preferred second year Master student
matrix solver program from PrimeRail. or PhD student. Understanding the
basic SPD matrix solving and basic
Distributed processing system provides the rich parallel programming.
opportunity to enhance the performance and
capacity of SPD (symmetric positive definitive)
matrix solver.
Through this work, intern can learn the general
distributed processing algorithm, implementation
techniques and how these techniques are applied
to matrix solving.
F Hiring Manager: Subarna Sinha Requirements:
Intern Job Description: M.S or PhD candidate in CS/EE/CE or
Develop an accurate and scalable solution for full‐ related field
chip geometry manipulation in a distributed
processing environment. The project will involve
both algorithm development and
implementation. The goal is to have the software
working on large chips, provide accurate results
(non‐distributed versus distributed) while
showing good scalability with an increase in the
number of processors. In addition, the method
should work well in a pipeline environment.
G Hiring Manager: Subarna Sinha Requirements:
Intern Job Description: M.S or PhD candidate in CS/EE/CE or
Develop an accurate and scalable solution for full‐ related field
chip geometry manipulation in a distributed
processing environment. The project will involve
both algorithm development and
implementation. The goal is to have the software

4. working on large chips, provide accurate results
(non‐distributed versus distributed) while
showing good scalability with an increase in the
number of processors. In addition, the method
should work well in a pipeline environment.
H Hiring Manager: Pei‐Hsin Ho Requirements:
Intern Job Description: Ph.D. student who has demonstrated
Implementation and experimentation of physical ability in rapid coding and detailed
synthesis technologies that provide 10x speedup analysis of experimental results.
and neutral QoR
I Hiring Manager: Pei‐Hsin Ho Requirements:
Intern Job Description: Ph.D. student who has demonstrated
Implementation and experimentation of physical ability in rapid coding and detailed
synthesis technologies that provide 10x speedup analysis of experimental results.
and neutral QoR