1. This document is the mid-semester examination for the Analog Electronics course taken in Fall 2018 at the Indian Institute of Information Technology Ranchi. It contains 6 questions assessing knowledge of operational amplifiers, bipolar junction transistors, diode characteristics, and transistor biasing circuits. 2. The questions cover key characteristics of ideal op-amps, deriving voltage gain expressions for inverting and non-inverting configurations, explaining base width modulation in BJTs, drawing and explaining diode I-V characteristics and breakdown mechanisms, identifying diode properties from descriptions, and designing a self-bias circuit and deriving the stability factor expression for a voltage divider bias circuit. 3. The exam is worth a total of 30 marks and

1. INDIAN INSTITUTE OF INFORMATION TECHNOLOGY RANCHI
(At NIT Jamshedpur - 831014), Jharkhand
Department of Electronics and Communication Engineering
MID - SEMESTER EXAMINATION-2018 (AUTUMN SESSION)
Course Code: EC 207 Course Title: Analog Electronics
Date: 27.11.2018 Day: Tuesday
Course Instructor: Dr. Santosh Kumar Mahto
Duration: 2 Hours Max. Marks: 30
Instructions:
1. Attempt all questions.
2. The figure in the right-hand margin indicates full marks.
3. Missing data, if any, may suitably be assumed.
4. Symbols have their usual meaning.
1. (a) Write downthe characteristicsof Ideal OP-AMP.
(b) Derive the expression of voltagegainforInvertingandnon-invertingOP-AMP.
[2+4]
2.
Explainbase widthmodulationinBipolarJunctionTransistor.
4
3.
Draw the I-V characteristicsof Diode andexplainthe knee voltage and down voltage.
What are the cause of breakdown explain.
[3+2]
4. a.
a.
The static charateristics of an adequately forward biased p-n junction is a
straight line. If the plot is of
i. logI Vs logV
ii. logI Vs V
iii. I Vs logV
iv. I Vs V
2
b. For a p-n junction match the type of breakdown with phenomenon
Column I
1. Avalanche Breakdown
2. Zener Breakdown
3. Punch through
Column II
A. Collision of carriers with crystal ions
B. Early effect
C. Rupture of Covalent bond due to strong electric field.
2
d. We can design NOT Gate using diode. ( True/False) 1
e. Ideal voltage Source has low input impedance and high out put impedance.
( True/False)
1
f. Ideal diode is piece wise linear device. ( True/False) 1
5.
Designa self biascircuitfora commonemitteramplifierusing as NPN transistor with
β=100, and the other details are VCC=12V, VCEQ=6V, ICQ=4mA, RC=1KΩ and RE=0.5KΩ.
4
6
Derive an expression for the stability factor ‘s’ of the voltage divider bias circuit.
4
XXX