ADC_1682318820251.pptx
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Direct ADCs directly compare the input analog voltage to an internally generated reference voltage and output a digital code. Integrated ADCs first convert the input voltage into a linear function of time or frequency before outputting a digital code. A flash ADC is a direct ADC that uses parallel comparators to simultaneously compare the input voltage to different reference levels and output a digital code in a single step. However, it requires an exponentially increasing number of comparators for higher resolution. A dual-slope ADC is an integrated ADC that uses an integrator to convert the input voltage into a linear ramp over time. It then integrates a reference voltage into a ramp of the opposite polarity until the two ramps cancel out, at which point
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ACEP Magazine edition 4th launched on 05.06.2024
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODEL
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
A SYSTEMATIC RISK ASSESSMENT APPROACH FOR SECURING THE SMART IRRIGATION SYSTEMS
The smart irrigation system represents an innovative approach to optimize water usage in agricultural and landscaping practices. The integration of cutting-edge technologies, including sensors, actuators, and data analysis, empowers this system to provide accurate monitoring and control of irrigation processes by leveraging real-time environmental conditions. The main objective of a smart irrigation system is to optimize water efficiency, minimize expenses, and foster the adoption of sustainable water management methods. This paper conducts a systematic risk assessment by exploring the key components/assets and their functionalities in the smart irrigation system. The crucial role of sensors in gathering data on soil moisture, weather patterns, and plant well-being is emphasized in this system. These sensors enable intelligent decision-making in irrigation scheduling and water distribution, leading to enhanced water efficiency and sustainable water management practices. Actuators enable automated control of irrigation devices, ensuring precise and targeted water delivery to plants. Additionally, the paper addresses the potential threat and vulnerabilities associated with smart irrigation systems. It discusses limitations of the system, such as power constraints and computational capabilities, and calculates the potential security risks. The paper suggests possible risk treatment methods for effective secure system operation. In conclusion, the paper emphasizes the significant benefits of implementing smart irrigation systems, including improved water conservation, increased crop yield, and reduced environmental impact. Additionally, based on the security analysis conducted, the paper recommends the implementation of countermeasures and security approaches to address vulnerabilities and ensure the integrity and reliability of the system. By incorporating these measures, smart irrigation technology can revolutionize water management practices in agriculture, promoting sustainability, resource efficiency, and safeguarding against potential security threats.
Recycled Concrete Aggregate in Construction Part III
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Low power architecture of logic gates using adiabatic techniques
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressions
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
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ADC_1682318820251.pptx
- 1. Direct vs Integrated ADC Differences Direct Type Integrated Type A/D Conversion is in a direct manner A/D Conversion is in a indirect manner. Input analog voltage is directly compared with the internally generated equivalent signal and converts the same into digital code. Input analog voltage is converted into a linear function of time or frequency and converts the same into digital code. Eg: Flash (comparator) type ADC, Counter type ADC, Tracking or Servo operated ADC and Successive approximation ADC. Eg: Charge balancing type ADC and dual slope ADC.
- 2. Flash ADC Simultaneous ADC Parallel Comparator ADC
- 3. Condition Comparator Output Vi > Vref V0 = 1 Vi < Vref V0 = 0
- 4. Flash ADC Truth Table
- 5. Pros and Cons • Advantages: • Flash ADC is the fastest because A/D conversion is performed simultaneously through a set of comparators. Typical conversion time is 100 ns or less. • The construction is simple and easier to design. • Disadvantages: • This is not suitable for A/D conversion with more than 3 or 4 digital output bits. It is because of the fact that (2n – 1) comparators are required for an n-bit ADC and the number of comparators required doubles for each added bit.
- 8. Description • Consists of a 1. high impedance buffer (voltage follower), A1 2. integrator, A2 3. voltage comparator (CMP) • If there is no START command, SW1 is connected to ‘gnd’ and SW2 is closed. Now CAZ is used to provide compensation for the offset voltage of all three op-amps. • If START command is issued, SW2 is connected to ‘gnd’ and SW1 is connected to Va .
- 9. Description • At time, t1: • SW1 is connects Va to A1. SW2 is grounded. • n-stage counter starts counting from ‘0’ and it resets after 2n clock cycles. • Va is integrated by the integrator until counter is resetted (i.e) for a fixed duration of 2n clock periods. • For an integrator, if the input is a positive step; then the output is a negative ramp. So, a negative ramp is obtained across output (V0).
- 10. Description • At time, t2: • n-stage counter is resetted. • SW1 connects VR to A1. SW2 is grounded. • Counter again starts counting from ‘0’. • VR is integrated by the integrator (a positive ramp is obtained as VR is positive) until the output voltage (V0) is zero.
- 11. Description • At time, t3: • V0 will become ‘0’. • Now the counter value at t3 , say ‘N’, is proportional to the analog input voltage, Va. • EOC is issued by the converter.
- 12. Output Waveform
- 13. Derivation of V0 • See Notes
- 14. Inferences: • N is directly proportional to Va. • Provides excellent noise rejection. • Needs long conversion time. • Used for accurate measurement of slow varying (less frequency) signals.
- 15. Problem: