2010 on bridge development for satellite test of equivalance principle

1. On Bridge development for
Satellite Test of Equivalence Principle
HEPL, Stanford University
By Siddartha S Verma
Team: Dr. Suwen Wang, Tom Holmes, David Hipkins
Supervised by: Prof. C.W.Francis Everitt
13th October, 2010
{Special thanks to Valerio Ferroni and Rashed Al Yousif for intellectual and moral support.}

2. Current state of the Lock In board -
•Board ready for testing.
Summary of what has been achieved:
•Assembled board.
• Software EAGLE file for the BOARD and the SCHEMATIC of the Lock In amplifier done.
• Capacitive bridge model in the Simulink (for 1st run) neglecting the non-linearity.
• Created Simulink model for the Lock-In amplifier, testing in progress.

3. Figure1
Fig 1: the actual board status, hitherto.

4. Figure2
Fig 2: The final board file for the Lock In designed using EAGLE software. To
show the connections and the circuitry in the PCB.

5. Figure 3
Fig 3: the final schematic designed using EAGLE software. To show the
circuitry in used for making the Lock-In board.

6. Figure 4
Fig 4: the zoomed in picture of the board file shows the naming convention of all the
components in the board.
NS: Proper care has to be taken in order to arrange the components such that the names
doesn’t overlap each other.

7. Figure 5
Fig 5: the zoomed in view of the schematic build which shows the names of all the
components transparently.

8. Lock In module
Controller
Injection
section
X - X +
Differential amplifier
X
Y
Figure 6
Software part
Hardware
part
Fig 6: the bridge implementation. To show the overall working mechanism for the
1st run.NB: The output from the Lock In can be seen on the Simulink as well as Dspace
interface.

9. Capacitive bridge model in the Main Simulink model.
Fig 7: to show how the Capacitive bridge model is integrated in the main
Simulink model.
NB: A corresponding block of capacitive bridge model also exists in the Dspace Interface

10. Fig 8: to show when we go inside the 3 axis Capacitive bridge model, which was
integrated to the Simulink model in the previous slide.

11. Figure 9
Fig 9: to show when we go inside the position to capacitance block. We will use
only the X-axis for our current work. The function which converts position to
capacitance is embedded inside blocks named as- X-axis_Tmin and so on.

12. Figure 10
Fig 10: The 1st Simulink model for the Lock In amplifier for 1st run.
Simulink model for the Lock In amplifier:

13. Figure 11
Fig 11: The output from the 1st Lock In amplifier simulated from it.

14. Figure 12
Fig 12: the 2nd Simulink model for the Lock In amplifier possible for future work.

15. Figure 13
Fig 13: the inside of the 2nd Simulink model for the Lock In amplifier shown in previous
slide.

16. Future work:
•Board testing
•Further modification of Lock-In Simulink model.
This effort for the future:
• Input and Output impedance modeling.
•Board support electronics.
•Phase of D-Space generated reference to the Lock In hardware.
•Modification of the Position to Capacitance function which would include non-linearities.
Issues:
•Some of the things which could consume much times are- debugging the electronic
circuit in the EAGLE software and having the board and schematic file free of all the
design-rule-check errors and the electrical-rule-check errors. Once could confront almost
300 of those errors after making the final circuit design in EAGLE.
•The shipment of the electronic components sometime delays your effort since the need
of some of the components could be anticipated after having the major part of the PCB
done.
•Incompatibility issues which could arise when the hardware is run along with the D-
Space software.