This document describes a design approach using UML 2.0 for specifying stream processor systems. Key aspects include:
1. UML 2.0 notations like composite classes, ports, and hierarchical statecharts are used to abstractly specify stream processors and applications.
2. Specifications are translated to SystemC models, including a TLM simulator and RTL code.
3. A case study demonstrates specifying a real-time stream processor in UML 2.0 and generating SystemC models for verification.
A DSEL for Addressing the Problems Posed by Parallel ArchitecturesJason Hearne-McGuiness
The document proposes a domain-specific embedded language (DSEL) to address issues with programming parallel architectures. The DSEL aims to add parallelism capabilities to an existing language with minimal changes. It defines types like thread pools and safe collections. The DSEL is designed to provide guarantees around correctness and efficiency of generated schedules while avoiding issues with other parallel programming approaches. An implementation in C++ exists to demonstrate the DSEL.
This is a lecture about Software Architecture Styles, part of the Advanced Software Engineering course, at the University of L'Aquila, Italy (www.di.univaq.it/muccini/SE+/2012)
A SYSTEMC/SIMULINK CO-SIMULATION ENVIRONMENT OF THE JPEG ALGORITHMVLSICS Design
In the past decades, many factors have been continuously increasing like the functionality of embedded systems as well as the time-to-market pressure has been continuously increasing. Simulation of an entire system including both hardware and software from early design stages is one of the effective approaches to improve the design productivity. A large number of research efforts on hardware/software (HW/SW) co-simulation have been made so far. Real-time operating systems have become one of the important components in the embedded systems. However, in order to validate function of the entire system, this system has to be simulated together with application software and hardware. Indeed, traditional methods of verification have proven to be insufficient for complex digital systems. Register transfer level test-benches have become too complex to manage and too slow to execute. New methods and verification techniques began to emerge over the past few years. Highlevel test-benches, assertion-based verification, formal methods, hardware verification languages are just a few examples of the intense research activities driving the verification domain.
This document provides an overview of transaction level modeling. It defines four transaction level models (TLMs) - specification model, component-assembly model, bus-arbitration model, and bus-functional model. These models are used at different stages of the design flow, from modeling system functionality without implementation details, to modeling with approximate timing, to cycle-accurate modeling. The models balance abstraction level and implementation details to aid system-level design while still allowing validation and refinement.
Architecture Analysis of Systems based on Publish-Subscribe SystemsDharmalingam Ganesan
This document discusses analyzing systems based on the publisher-subscriber architectural style. It describes analyzing a NASA system called GMSEC that uses this style. Static analysis is used to understand how components connect and communicate. Dynamic analysis involves monitoring a running system to understand behavior, such as which subscribers receive messages from which publishers. This analysis uncovered a high-priority bug and provided valuable insights into GMSEC.
This presentation is about a lecture I gave within the "Software systems and services" immigration course at the Gran Sasso Science Institute, L'Aquila (Italy): http://cs.gssi.infn.it/.
http://www.ivanomalavolta.com
Automated Performance Analysis of Business ProcessesDaniele Gianni
This document describes a model-driven method for the automated performance prediction of business processes. The method uses PyBPMN to specify functional and non-functional requirements, UML models to specify the design, EQN models to specify performance, and jEQN code to implement/execute the performance model. An example application is presented to validate the approach, showing how a business process for checking out orders is modeled and its performance predicted. The conclusions discuss how the method automates existing simulation approaches using model-driven standards and closes the gap between business process and performance modeling languages.
A framework for distributed control and building performance simulationDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
A DSEL for Addressing the Problems Posed by Parallel ArchitecturesJason Hearne-McGuiness
The document proposes a domain-specific embedded language (DSEL) to address issues with programming parallel architectures. The DSEL aims to add parallelism capabilities to an existing language with minimal changes. It defines types like thread pools and safe collections. The DSEL is designed to provide guarantees around correctness and efficiency of generated schedules while avoiding issues with other parallel programming approaches. An implementation in C++ exists to demonstrate the DSEL.
This is a lecture about Software Architecture Styles, part of the Advanced Software Engineering course, at the University of L'Aquila, Italy (www.di.univaq.it/muccini/SE+/2012)
A SYSTEMC/SIMULINK CO-SIMULATION ENVIRONMENT OF THE JPEG ALGORITHMVLSICS Design
In the past decades, many factors have been continuously increasing like the functionality of embedded systems as well as the time-to-market pressure has been continuously increasing. Simulation of an entire system including both hardware and software from early design stages is one of the effective approaches to improve the design productivity. A large number of research efforts on hardware/software (HW/SW) co-simulation have been made so far. Real-time operating systems have become one of the important components in the embedded systems. However, in order to validate function of the entire system, this system has to be simulated together with application software and hardware. Indeed, traditional methods of verification have proven to be insufficient for complex digital systems. Register transfer level test-benches have become too complex to manage and too slow to execute. New methods and verification techniques began to emerge over the past few years. Highlevel test-benches, assertion-based verification, formal methods, hardware verification languages are just a few examples of the intense research activities driving the verification domain.
This document provides an overview of transaction level modeling. It defines four transaction level models (TLMs) - specification model, component-assembly model, bus-arbitration model, and bus-functional model. These models are used at different stages of the design flow, from modeling system functionality without implementation details, to modeling with approximate timing, to cycle-accurate modeling. The models balance abstraction level and implementation details to aid system-level design while still allowing validation and refinement.
Architecture Analysis of Systems based on Publish-Subscribe SystemsDharmalingam Ganesan
This document discusses analyzing systems based on the publisher-subscriber architectural style. It describes analyzing a NASA system called GMSEC that uses this style. Static analysis is used to understand how components connect and communicate. Dynamic analysis involves monitoring a running system to understand behavior, such as which subscribers receive messages from which publishers. This analysis uncovered a high-priority bug and provided valuable insights into GMSEC.
This presentation is about a lecture I gave within the "Software systems and services" immigration course at the Gran Sasso Science Institute, L'Aquila (Italy): http://cs.gssi.infn.it/.
http://www.ivanomalavolta.com
Automated Performance Analysis of Business ProcessesDaniele Gianni
This document describes a model-driven method for the automated performance prediction of business processes. The method uses PyBPMN to specify functional and non-functional requirements, UML models to specify the design, EQN models to specify performance, and jEQN code to implement/execute the performance model. An example application is presented to validate the approach, showing how a business process for checking out orders is modeled and its performance predicted. The conclusions discuss how the method automates existing simulation approaches using model-driven standards and closes the gap between business process and performance modeling languages.
A framework for distributed control and building performance simulationDaniele Gianni
Presentation delivered at the 3rd IEEE Track on
Collaborative Modeling & Simulation - CoMetS'12.
Please see http://www.sel.uniroma2.it/comets12/ for further details.
Challenges in multi core programming by Nishigandha WankhadeNishigandha Wankhade
This document discusses the challenges of multi-core programming. It outlines sequential programming models and how concurrency differs by allowing tasks to execute concurrently rather than sequentially. The main challenges discussed are software development challenges like task decomposition, communication between concurrent tasks, and accessing shared resources, as well as testing and debugging concurrent programs. It also discusses libraries for C++ developers to implement multi-threading and challenges around utilizing different processor architectures.
CS266 Software Reverse Engineering (SRE)
Reengineering and Reuse of Legacy Software
Teodoro (Ted) Cipresso, teodoro.cipresso@sjsu.edu
Department of Computer Science
San José State University
Spring 2015
MODEL DRIVEN ARCHITECTURE, CONTROL SYSTEMS AND ECLIPSEAnže Vodovnik
This paper describes the use of model driven architecture and its application in control system development. It also presents a prototype solution based on the Eclipse framework implemented by the author.
Anže Vodovnik, Klemen Žagar, Cosylab, Ljubljana, Slovenija
The document discusses protecting applications from transient failures during cloud deployments. It presents the AURA tool, which uses a directed acyclic graph and message passing to deploy applications and recover from failures. The tool monitors deployment and retries failed nodes to overcome transient errors. The author proposes implementing error recovery and message passing in AURA using ASP.NET and SQL Server for improved failure handling and snapshots.
This paper presents an improved hardware acceleration scheme for Java method calls in the REALJava coprocessor. The strategy is implemented in an FPGA prototype and allows for measuring real performance increases. It validates the coprocessor concept for accelerating Java bytecode execution in embedded systems with limited CPU performance and memory availability. The coprocessor architecture is highly modular, separating communication from the execution core to improve reusability and allow for system scalability.
Automatically bridging UML profiles into MOF metamodelsIvano Malavolta
27th August 2015. My presentation at SEAA 2015 (http://paginas.fe.up.pt/~dsd-seaa-2015/) about our approach for autmatically bridging UML profiles into MOF metamodels. SEAA 2015 is the 41st Euromicro Conference on Software Engineering and Advanced Applications, and it has been held in 26 - 28 August 2015, Funchal, Madeira, Portugal.
Accompanying paper:
http://www.ivanomalavolta.com/files/papers/SEAA_2015.pdf
Abstract:
In Model-Driven Engineering, UML profiles and MOF-based Domain Specific Modeling Languages (DSMLs) are the most used approaches for describing domain specific applications. The choice of the right approach depends on several aspects, such as tool support, expressivity, complexity of models, company policies. In general, profiled UML models are very much used since they are intuitive for designers and model editors already exist, however they are intrinsically complex for model manipulation (e.g., transformation, analysis); conversely, domain specific models are more concise and easy to be manipulated, but they require an initial effort in terms of designers training and model editors development.
In this paper we propose an approach that allows getting the best of the two worlds: on one side designers can use UML profiles familiar to them, on the other side DSML models (automatically generated from profiled UML models) enable a better model manipulation. Our approach is based on an automatic bridge between UML profiles and MOF metamodels (which are the main artifacts of MOF-based DSMLs). The bridge is transparent to the user since it autonomously operates both on UML profiles and all the involved models. The bridge is realized through model transformation techniques in the Eclipse platform. In this paper we show its application on a case study based on SysML.
The document discusses frameworks and patterns for reusable software architectures in C++ network programming. It provides an overview of product line architectures and how frameworks can be used to support concurrent and networked applications. The document outlines some key frameworks in ACE (Adaptive Communication Environment) and how they embody commonality and variability. It also discusses design patterns used in a networked logging service example.
Model Driven Architecture and eXecutable UMLelliando dias
The document discusses Model Driven Architecture (MDA) and how executable UML models can support MDA. Key points include:
- MDA uses three primary model viewpoints: computation independent, platform independent, and platform specific models.
- Executable UML models can be used to validate platform independent models by executing acceptance tests on them.
- Model transformations allow automated mappings between models and generation of platform specific models.
PHP modernization approach generating KDM models from PHP legacy codejournalBEEI
With the rise of new web technologies such as web 2.0, Jquery, Bootstrap. Modernizing legacy web systems to benefit from the advantages of the new technologies is more and more relevant. The migration of a system from an environment to another is a time and effort consuming process, it involves a complete rewrite of the application adapted to the target platform. To realize this migration in an automated and standardized way, many approaches have tried to define standardized engineering processes. Architecture Driven Modernization (ADM) defines an approach to standardize and automate the reengineering process. We defined an ADM approach to represent PHP web applications in the highest level of abstraction models. To do this, we have used software artifacts as a entry point . This paper describes the extraction process, which permits discovering and understanding of the legacy system. And generate models to represent the system in an abstract way.
Advanced Software Engineering course, a.y. 2014-2015
http://lore.com/Advanced-Software-Engineering-Univaq/
This lecture is about Architecture Description Languages. What they are, how they evolved in time, current challenges and perspectives.
This document provides information about the PG Diploma in Computer Applications program, including its modules, specializations, and target audience. The course covers the modules required for the DOEACC 'O' level certification. Students can get dual qualifications of the PG Diploma and BCA degree without extra cost. The program is designed based on market trends and covers topics like basic computing, MS Office, IT tools, publishing, web design, and business systems. The target audience includes students from accredited institutes who have completed 10+2 or ITI certificate after class 10 followed by an accredited 'O' level course.
This document analyzes trends in ADC performance as CMOS technology scales down to smaller node sizes. It examines a large dataset of over 1100 scientific publications on experimental CMOS ADCs from 1976 to 2010. The following trends are observed:
1) Noise floor increases with scaling due to lower supply voltages and reduced signal swing. Empirical data shows the noise floor approaching limits that prevent further improvement of sampling rate as nodes shrink past 90nm.
2) Sampling rate increases for low-resolution ADCs but decreases for high-resolution ADCs with scaling. Limits are estimated where noise prevents maintaining or improving sampling rate in newer nodes.
3) Monolithic integration of wideband ADCs for wireless is limited to nodes older
The document discusses how Soft Machines validated a VISCTM microprocessor design using Synopsys ZeBu emulation. It describes the emulation setup developed, including transactors to probe the design and a cosim framework to compare results with simulation. Various debug methodologies leveraging ZeBu's tools helped identify bugs early in emulation runs of tests, operating system boots, and benchmarks.
This document summarizes the key steps and optimizations required to develop an efficient FPGA accelerator for non-binary LDPC decoding using high-level synthesis. It describes how a naive implementation based solely on a software description achieves limited performance, and how careful tuning of the high-level application description through optimizations like directive-based transformations can achieve performance close to hand-optimized RTL. The document aims to guide readers on designing efficient HLS-based hardware accelerators by considering limitations of the target device and characteristics of the application.
This document introduces and defines the syntax and semantics of "cinnamons", a new computation model intended to form the theoretical foundation for Control Network Programming (CNP). CNP is a visual, declarative programming approach that combines graphs and primitives. Cinnamons are the simplest possible version of CNP programs, defined rigorously with minimal features for formal study. The syntax defines cinnamons as a set of graphs called subnets, with arrows labeled as primitives or subnet calls. Semantics specify how cinnamons compute by traversing graphs and executing primitives. Cinnamons are shown to be Turing complete by equivalence to WHILE programs.
This document proposes an adaptive universal FEC scheme based on Reed-Solomon decoding for wireless sensor networks. It discusses the challenges of achieving reliability in WSNs due to diverse node features, applications, and changing channel conditions. It presents an adaptive universal FEC scheme that can dynamically select error correcting codes based on channel conditions and system constraints. A system design approach is discussed to explore tradeoffs between efficiency and flexibility. A dynamic partitioning module is also presented to optimize the system's performance by inferring the best error correcting scheme and partitioning scheme based on channel conditions and constraints. Implementation results on wireless sensor motes show the proposed system can achieve up to 56% power savings with less than 4% overhead.
This document summarizes the state-of-the-art in scalable video compression approaches based on wavelet transforms. It describes the basic principles of wavelet-based scalable video coding (WSVC), including enabling spatial, temporal, and quality scalability. Spatial scalability is enabled through multiresolution transforms like the discrete wavelet transform (DWT) and lifting schemes. Temporal scalability is achieved through motion-compensated temporal filtering. Quality scalability can be realized by progressive bitplane coding of wavelet subbands. The document reviews different WSVC architectures and compares their performance to the scalable video coding (SVC) standard.
Component-Based and Model-Driven Engineering: what is the difference? A CBSE ...Ivica Crnkovic
This document discusses the differences between component-based engineering (CBSE) and model-driven engineering (MDE). It notes that while CBSE focuses on source code and executable code reuse through composition, MDE takes a more top-down approach. The document argues that MDE and CBSE can be combined, with MDE helping to generate connectors/adapters, transform models, and evolve models in CBSE. CBSE can also benefit MDE by providing runtime feedback and reusing existing component technologies.
Challenges in multi core programming by Nishigandha WankhadeNishigandha Wankhade
This document discusses the challenges of multi-core programming. It outlines sequential programming models and how concurrency differs by allowing tasks to execute concurrently rather than sequentially. The main challenges discussed are software development challenges like task decomposition, communication between concurrent tasks, and accessing shared resources, as well as testing and debugging concurrent programs. It also discusses libraries for C++ developers to implement multi-threading and challenges around utilizing different processor architectures.
CS266 Software Reverse Engineering (SRE)
Reengineering and Reuse of Legacy Software
Teodoro (Ted) Cipresso, teodoro.cipresso@sjsu.edu
Department of Computer Science
San José State University
Spring 2015
MODEL DRIVEN ARCHITECTURE, CONTROL SYSTEMS AND ECLIPSEAnže Vodovnik
This paper describes the use of model driven architecture and its application in control system development. It also presents a prototype solution based on the Eclipse framework implemented by the author.
Anže Vodovnik, Klemen Žagar, Cosylab, Ljubljana, Slovenija
The document discusses protecting applications from transient failures during cloud deployments. It presents the AURA tool, which uses a directed acyclic graph and message passing to deploy applications and recover from failures. The tool monitors deployment and retries failed nodes to overcome transient errors. The author proposes implementing error recovery and message passing in AURA using ASP.NET and SQL Server for improved failure handling and snapshots.
This paper presents an improved hardware acceleration scheme for Java method calls in the REALJava coprocessor. The strategy is implemented in an FPGA prototype and allows for measuring real performance increases. It validates the coprocessor concept for accelerating Java bytecode execution in embedded systems with limited CPU performance and memory availability. The coprocessor architecture is highly modular, separating communication from the execution core to improve reusability and allow for system scalability.
Automatically bridging UML profiles into MOF metamodelsIvano Malavolta
27th August 2015. My presentation at SEAA 2015 (http://paginas.fe.up.pt/~dsd-seaa-2015/) about our approach for autmatically bridging UML profiles into MOF metamodels. SEAA 2015 is the 41st Euromicro Conference on Software Engineering and Advanced Applications, and it has been held in 26 - 28 August 2015, Funchal, Madeira, Portugal.
Accompanying paper:
http://www.ivanomalavolta.com/files/papers/SEAA_2015.pdf
Abstract:
In Model-Driven Engineering, UML profiles and MOF-based Domain Specific Modeling Languages (DSMLs) are the most used approaches for describing domain specific applications. The choice of the right approach depends on several aspects, such as tool support, expressivity, complexity of models, company policies. In general, profiled UML models are very much used since they are intuitive for designers and model editors already exist, however they are intrinsically complex for model manipulation (e.g., transformation, analysis); conversely, domain specific models are more concise and easy to be manipulated, but they require an initial effort in terms of designers training and model editors development.
In this paper we propose an approach that allows getting the best of the two worlds: on one side designers can use UML profiles familiar to them, on the other side DSML models (automatically generated from profiled UML models) enable a better model manipulation. Our approach is based on an automatic bridge between UML profiles and MOF metamodels (which are the main artifacts of MOF-based DSMLs). The bridge is transparent to the user since it autonomously operates both on UML profiles and all the involved models. The bridge is realized through model transformation techniques in the Eclipse platform. In this paper we show its application on a case study based on SysML.
The document discusses frameworks and patterns for reusable software architectures in C++ network programming. It provides an overview of product line architectures and how frameworks can be used to support concurrent and networked applications. The document outlines some key frameworks in ACE (Adaptive Communication Environment) and how they embody commonality and variability. It also discusses design patterns used in a networked logging service example.
Model Driven Architecture and eXecutable UMLelliando dias
The document discusses Model Driven Architecture (MDA) and how executable UML models can support MDA. Key points include:
- MDA uses three primary model viewpoints: computation independent, platform independent, and platform specific models.
- Executable UML models can be used to validate platform independent models by executing acceptance tests on them.
- Model transformations allow automated mappings between models and generation of platform specific models.
PHP modernization approach generating KDM models from PHP legacy codejournalBEEI
With the rise of new web technologies such as web 2.0, Jquery, Bootstrap. Modernizing legacy web systems to benefit from the advantages of the new technologies is more and more relevant. The migration of a system from an environment to another is a time and effort consuming process, it involves a complete rewrite of the application adapted to the target platform. To realize this migration in an automated and standardized way, many approaches have tried to define standardized engineering processes. Architecture Driven Modernization (ADM) defines an approach to standardize and automate the reengineering process. We defined an ADM approach to represent PHP web applications in the highest level of abstraction models. To do this, we have used software artifacts as a entry point . This paper describes the extraction process, which permits discovering and understanding of the legacy system. And generate models to represent the system in an abstract way.
Advanced Software Engineering course, a.y. 2014-2015
http://lore.com/Advanced-Software-Engineering-Univaq/
This lecture is about Architecture Description Languages. What they are, how they evolved in time, current challenges and perspectives.
This document provides information about the PG Diploma in Computer Applications program, including its modules, specializations, and target audience. The course covers the modules required for the DOEACC 'O' level certification. Students can get dual qualifications of the PG Diploma and BCA degree without extra cost. The program is designed based on market trends and covers topics like basic computing, MS Office, IT tools, publishing, web design, and business systems. The target audience includes students from accredited institutes who have completed 10+2 or ITI certificate after class 10 followed by an accredited 'O' level course.
This document analyzes trends in ADC performance as CMOS technology scales down to smaller node sizes. It examines a large dataset of over 1100 scientific publications on experimental CMOS ADCs from 1976 to 2010. The following trends are observed:
1) Noise floor increases with scaling due to lower supply voltages and reduced signal swing. Empirical data shows the noise floor approaching limits that prevent further improvement of sampling rate as nodes shrink past 90nm.
2) Sampling rate increases for low-resolution ADCs but decreases for high-resolution ADCs with scaling. Limits are estimated where noise prevents maintaining or improving sampling rate in newer nodes.
3) Monolithic integration of wideband ADCs for wireless is limited to nodes older
The document discusses how Soft Machines validated a VISCTM microprocessor design using Synopsys ZeBu emulation. It describes the emulation setup developed, including transactors to probe the design and a cosim framework to compare results with simulation. Various debug methodologies leveraging ZeBu's tools helped identify bugs early in emulation runs of tests, operating system boots, and benchmarks.
This document summarizes the key steps and optimizations required to develop an efficient FPGA accelerator for non-binary LDPC decoding using high-level synthesis. It describes how a naive implementation based solely on a software description achieves limited performance, and how careful tuning of the high-level application description through optimizations like directive-based transformations can achieve performance close to hand-optimized RTL. The document aims to guide readers on designing efficient HLS-based hardware accelerators by considering limitations of the target device and characteristics of the application.
This document introduces and defines the syntax and semantics of "cinnamons", a new computation model intended to form the theoretical foundation for Control Network Programming (CNP). CNP is a visual, declarative programming approach that combines graphs and primitives. Cinnamons are the simplest possible version of CNP programs, defined rigorously with minimal features for formal study. The syntax defines cinnamons as a set of graphs called subnets, with arrows labeled as primitives or subnet calls. Semantics specify how cinnamons compute by traversing graphs and executing primitives. Cinnamons are shown to be Turing complete by equivalence to WHILE programs.
This document proposes an adaptive universal FEC scheme based on Reed-Solomon decoding for wireless sensor networks. It discusses the challenges of achieving reliability in WSNs due to diverse node features, applications, and changing channel conditions. It presents an adaptive universal FEC scheme that can dynamically select error correcting codes based on channel conditions and system constraints. A system design approach is discussed to explore tradeoffs between efficiency and flexibility. A dynamic partitioning module is also presented to optimize the system's performance by inferring the best error correcting scheme and partitioning scheme based on channel conditions and constraints. Implementation results on wireless sensor motes show the proposed system can achieve up to 56% power savings with less than 4% overhead.
This document summarizes the state-of-the-art in scalable video compression approaches based on wavelet transforms. It describes the basic principles of wavelet-based scalable video coding (WSVC), including enabling spatial, temporal, and quality scalability. Spatial scalability is enabled through multiresolution transforms like the discrete wavelet transform (DWT) and lifting schemes. Temporal scalability is achieved through motion-compensated temporal filtering. Quality scalability can be realized by progressive bitplane coding of wavelet subbands. The document reviews different WSVC architectures and compares their performance to the scalable video coding (SVC) standard.
Component-Based and Model-Driven Engineering: what is the difference? A CBSE ...Ivica Crnkovic
This document discusses the differences between component-based engineering (CBSE) and model-driven engineering (MDE). It notes that while CBSE focuses on source code and executable code reuse through composition, MDE takes a more top-down approach. The document argues that MDE and CBSE can be combined, with MDE helping to generate connectors/adapters, transform models, and evolve models in CBSE. CBSE can also benefit MDE by providing runtime feedback and reusing existing component technologies.
Integration of real time software modules for reconfigurable sensPham Ngoc Long
The document describes a framework for integrating reusable real-time software modules in a reconfigurable multi-sensor control system. The framework uses a global database of state variables through which modules can exchange information. Modules are modeled as port automata with input and output ports. A state variable table mechanism implemented in the Chimera II real-time operating system allows modules running on different processors to efficiently communicate and synchronize.
The document discusses different types of friends represented by different colors. A green friend is positive and hopeful. A blue friend brings peace and serenity. A yellow friend makes people laugh and provides comfort when sad. A red friend encourages rule following but also change through warm words. An orange friend enhances spirit and energy. A grey friend teaches silence and self-reflection. A purple friend helps learn wisdom and true authority. A brown friend helps come down to reality. A white friend helps discover wisdom in experiences. Together, all friends form a rainbow of love.
A tlm based platform to specify and verify component-based real-time systemsijseajournal
This paper is about modeling and verification languages with their pros and cons. Modeling is dynamic
part of system development process before realization. The cost and risky situations obligate designer to
model system before production and modeling gives designer more flexible and dynamic image of realized
system. Formal languages and modeling methods are the ways to model and verify systems but they have
their own difficulties in specifying systems. Some of them are very precise but hard to specify complex
systems like TRIO, and others do not support object oriented design and hardware/software co-design in
real-time systems. In this paper we are going to introduce systemC and the more abstracted method called
TLM 2.0 that solved all mentioned problems.
System on Chip Design and Modelling Dr. David J GreavesSatya Harish
The document provides an overview of a course on system on chip design and modeling techniques. The course covers topics like register transfer language, SystemC components, basic SoC components, assertion-based design, network on chip structures, and architectural design exploration. It aims to cover the front end of the design automation process, including specification, modeling at different levels of abstraction, and logic synthesis. A running example evolves over the lectures to demonstrate a simple SoC.
The document discusses deployment diagrams in UML. Deployment diagrams model how system components are deployed on physical infrastructure, showing nodes where components are located, network capabilities, and other physical details. They show the runtime configuration and topology of processors, devices, and software components. The document provides examples of using deployment diagrams to model embedded systems, client-server systems, and fully distributed systems.
The real time publisher subscriber inter-process communication model for dist...yancha1973
1) The document proposes a real-time publisher/subscriber model for inter-process communication in distributed real-time systems.
2) In the model, processes publish and subscribe to messages using logical handles called distribution tags, without knowledge of senders/receivers.
3) An application programming interface is presented that allows processes to create/destroy tags, publish/receive messages, and query senders/receivers.
4) The model is fault-tolerant, supporting applications like clock synchronization across nodes and allowing processes to be upgraded online.
Towards a metamodel for the Rubus Component ModelAlessio Bucaioni
Presentation of the speech at ModComp, MODELS 2014, held in Valencia, Spain.
ICONS CREDITS
Magnifying Glass by Edward Boatman from The Noun Project
Time by Wayne Middleton from The Noun Project
Puzzle by Agarunov Oktay-Abraham from The Noun Project
Gears by Eugen Belyakoff from The Noun Project
"A Highly Decoupled Front-end Framework for High Trafficked Web Applications"...Prem Gurbani
This document summarizes a paper that proposes a new front-end framework architecture for high-traffic web applications. The framework aims to decouple layers to improve scalability, flexibility, and development efficiency. It proposes producing JSON data on the server and caching reusable components on the client to reduce bandwidth. This allows parallel development and minimizes dependencies between teams.
Automatic Synthesis and Formal Verification of Interfaces Between Incompatibl...IDES Editor
In this work, we are concerned with automatic
synthesis and formal verification of interfaces between
incompatible soft intellectual properties (IPs) for System On
Chip (SOC) design. IPs Structural and dynamic aspects are
modeled via UML2.x diagrams such as structural, timing and
Statecharts diagrams. From these diagrams, interfaces are
generated automatically between incompatible IPs following
an interface synthesis algorithm. Interfaces behaviors
verification is performed by the model checker that is
integrated in Maude language. A Maude specification
including interface specification and properties for verification
are generated automatically from UML diagrams.
Server Emulator and Virtualizer for Next-Generation Rack ServersIRJET Journal
This document discusses developing a server emulator using QEMU to virtualize hardware and enable faster software development. It describes booting OpenBMC on an emulated AST2600-EVB board in QEMU. Networking, SSH, and other services were enabled to allow remote access. A container image was created to automate the process. Results showed the emulated BMC booting successfully and functional tests passing, demonstrating the emulator reduces hardware dependence and speeds development. Future work could add more web interface features and virtual GPIO support.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
Automatically partitioning packet processing applications for pipelined archi...Ashley Carter
This document describes a technique for automatically partitioning sequential packet processing applications into coordinated parallel subtasks that can be efficiently mapped to pipelined network processor architectures. The technique balances work among pipeline stages and minimizes data transmission between stages. It was implemented in an auto-partitioning C compiler for Intel network processors. Experimental results showed over 4x speedups for IPv4 and IP forwarding benchmarks on a 9-stage pipeline compared to non-partitioned code.
Highlighted notes of article while studying Concurrent Data Structures, CSE:
The Concurrency Challenge
Wen-mei W. Hwu, Kurt Keutzer, Tim Mattson
IEEE Design and Test
The Concurrency Challenge
July-August 2008, pp. 312-320, vol. 25
DOI Bookmark: 10.1109/MDT.2008.110
Wen-mei Hwu is a professor and
the Sanders-AMD Endowed Chair of
Electrical and Computer Engineering
at the University of Illinois at Urbana-
Champaign. His research interests
include architecture and compilation for parallel-
computing systems. He has a BS in electrical
engineering from National Taiwan University, and
a PhD in computer science from the University of
California, Berkeley. He is a Fellow of both the IEEE
and the ACM.
Kurt Keutzer is a professor of
electrical engineering and computer
science at the University of California,
Berkeley and a principal investigator
in UC Berkeley’s Universal Parallel
Computing Research Center. His research focuses
on the design and programming of ICs. He has a BS
in mathematics from Maharishi International University, and an MS a PhD in computer science from
Indiana University, Bloomington. He is a Fellow of the
IEEE and a member of the ACM.
Timothy G. Mattson is a principal
engineer in the Applications Research
Laboratory at Intel. He research inter-
ests focus on performance modeling
for future multicore microprocessors
and how different programming models map onto
these systems. He has a BS in chemistry from the
University of California, Riverside; an MS in chemistry
from the university of California, Santa Cruz; and a PhD in theoretical chemistry from the University of
California, Santa Cruz. He is a member of the
American Association for the Advancement of Sci-
ence (AAAS).
https://ieeexplore.ieee.org/document/4584454
Executable UML (xUML) provides an executable version of UML with a precisely defined semantics for actions. xUML supports the separation of business logic from platform technology through platform independent models (PIMs) that can be automatically transformed into platform specific models (PSMs) through model mappings. Tools such as Kennedy Carter's iUML and Accelerated Technology's BridgePoint allow developers to simulate and test xUML models prior to translation into executable code.
10 - Architetture Software - More architectural stylesMajong DevJfu
The Microkernel pattern partitions an operating system into isolated, minimal components that communicate through a small, fixed message-passing interface, allowing components to be developed and upgraded independently while maintaining overall system stability and security.
The development of embedded applications (such as Wireless Sensor Network protocols) often
requires a shift to formal specifications. To insure the reliability and the performance of the
WSNs, such protocols must be designed following some methods reducing error rate. Formal
methods (as Automata, Petri nets, algebra, logics, etc.) were largely used in the specification of
these protocols, their analysis and their verification. After that, their implementation is an
important phase to deploy, test and use those protocols in real environments. The main
objective of the current paper is to formalize the transformation from high-level specification (in
Timed Automata) to low-level implementation (in NesC language and TinyOs system) and to
automate such transformation. The proposed transformation approach defines a set of rules that
allow the passage between these two levels. We implemented our solution and we illustrated the
proposed approach on a protocol case study for the "humidity" and "temperature" sensing in
WSNs applications.
Software performance simulation strategies for high-level embedded system designMr. Chanuwan
This document discusses software performance simulation strategies for high-level embedded system design. It introduces instruction set simulators (ISSs), which are accurate but slow. It also discusses binary-level simulation (BLS) and source-level simulation (SLS), which are faster approaches based on native execution. The document proposes a new approach called intermediate source code instrumentation based simulation (iSciSim) that aims to achieve high accuracy, speed, and low complexity for system-level design space exploration.
This paper analyzes the effects of different Network-on-Chip (NoC) modeling styles in SystemC on simulation speed compared to a reference VHDL model. Two approximately timed (AT) and loosely timed (LT) transaction level (TL) models achieved 13-40x and 20-30x speedups respectively over the VHDL model with less than 10% error. The AT model offered a notable speedup with modest error and is recommended over the LT model which did not provide significant additional speedup despite larger estimation errors, especially under higher loads. Increasing transfer size and raising the abstraction level to transaction-level modeling were found to be effective methods to significantly improve simulation performance for evaluating NoC designs.
Concurrent Matrix Multiplication on Multi-core ProcessorsCSCJournals
With the advent of multi-cores every processor has built-in parallel computational power and that can only be fully utilized only if the program in execution is written accordingly. This study is a part of an on-going research for designing of a new parallel programming model for multi-core architectures. In this paper we have presented a simple, highly efficient and scalable implementation of a common matrix multiplication algorithm using a newly developed parallel programming model SPC3 PM for general purpose multi-core processors. From our study it is found that matrix multiplication done concurrently on multi-cores using SPC3 PM requires much less execution time than that required using the present standard parallel programming environments like OpenMP. Our approach also shows scalability, better and uniform speedup and better utilization of available cores than that the algorithm written using standard OpenMP or similar parallel programming tools. We have tested our approach for up to 24 cores with different matrices size varying from 100 x 100 to 10000 x 10000 elements. And for all these tests our proposed approach has shown much improved performance and scalability
Network Analyzer and Report Generation Tool for NS-2 using TCL ScriptIRJET Journal
This document describes a tool called the ARGT (Analyzer and Report Generation Tool) for NS-2 that allows users to generate TCL script files to model network scenarios in a flexible way. The tool provides a graphical user interface where users can create wired or wireless network topologies by adding nodes and links. It allows configuration of network protocols and applications. The tool then generates a TCL script that can be run directly in NS-2 to simulate the network and produce output files. The document evaluates the tool's ability to analyze simulation results for metrics like throughput, delay, and jitter. It finds that the ARGT is an improvement over previous tools as it integrates TCL script generation, simulation, and performance analysis into a single
This presentation is a short introduction to issues in Hardware-Software Codesign. It discusses definition of codesign, its significance, design issues in Hardware-software codesign, Abstraction levels, Duality of harware and software
This document describes an automation tool that was developed to generate a Register Abstraction Layer (RAL) from an IP core's register description provided in the IP-XACT schema format. The tool parses the IP-XACT XML file without any prior knowledge of SystemVerilog or UVM. It then generates a RAL file in SystemVerilog that can be integrated into a UVM verification environment to verify various devices under test. The tool aims to save time and reduce errors compared to manually writing large RAL files.
1. Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream
Processing£
Yongxin ZHU Zhenxin SUN
School of Computing School of Computing
National University of Singapore National University of Singapore
zhuyx@comp.nus.edu.sg sunzhenx@comp.nus.edu.sg
Alexander MAXIAGUINE Weng-Fai WONG
Computer Engineering and Networks Laboratory School of Computing
ETH Zurich National University of Singapore
maxiagui@tik.ee.ethz.ch wongwf@comp.nus.edu.sg
Abstract Because of specific application domains, existing
stream programming languages such as StreamIT [14],
While enabling fast implementation and reconfiguration StreamC [12], and NVIDIA Cg [11] with many differences
of stream applications, programmable stream processors which result in an incompatibility issue to specifications and
design reuse. More importantly, they are programming lan-
expose issues of incompatibility and lack of adoption in ex-
guages and do not meet the requirements for high level ab-
isting stream modelling languages. To address them, we straction, description and modelling.
describe a design approach in which specifications are cap- The Unified Modelling Language (UML) is gaining pop-
tured in UML 2.0, and automatically translated into Sys- ularity from real time system designers. UML has been
temC models consisting of simulators and synthesizable widely accepted in both software design and system ar-
code under proper style constraints. As an application case, chitecture community since its invention. UML has also
we explain real time stream processor specifications using been evolving to meet the needs of real time embedded sys-
new UML 2.0 notations. Then we expound how our trans- tems [7]. UML 2.0 incorporates more modelling abstraction
lator generates SystemC models and includes additional notations in the real time software domain and designers can
hardware details. Verifications are made during UML ex- expect to use these notations in their initial specifications,
consisting of class diagrams, state diagrams and structure
ecution as well as assertions in SystemC. The case study
diagrams, which are available in products such as Rational
demonstrates the feasibility of fast specifications, modifica- Rose Real Time and I-Loigx’s Rhapsody [5].
tions and generation of real time stream processor designs. However, real time UML may not suffice for stream pro-
cessor designs because of their special needs. On stream
processors, a large amount of on-chip resources are allo-
cated to deliver long instruction and large data packets.
1 Introduction Stream processor architectures also have to adapt to dif-
ferent stream applications. Although programmable stream
Over the last few years, there is a remarkable increase processors [6] provide the hardware for quick implementa-
in the complexity of media-intensive products such as digi- tion, it is still not clear for designers if UML 2.0 can be used
tal video recorder, DVD players, MPEG players and video to specify streaming features clearly and easily. This is one
conference devices. The complexity stems from the heavy of the aims of this paper.
computational workload and large data volume in the media Since there is a huge gap between UML-based descrip-
stream. Due to the complexity, designing streaming proces- tions and their implementations, it is clear that such descrip-
sors has become a complicated task. An approach to tam- tions need to be refined to a number of more detailed ones
ing the complexity is to raise the level of abstraction to that in order to get the final implementation level specifications.
of system-level designs. This approach incurs the needs to SystemC is a design language that allows designs to be ex-
specify abstract models of systems. pressed and verified at sufficiently high levels of abstraction
while at the same time enabling the linkage to hardware
£ Acknowledgement: This research was partially funded under implementation and verification. Furthermore, SystemC,
A*STAR Project 022/106/0043. when viewed from a programming perspective, is a collec-
1
2. tion of class libraries built on top of C++ and so is natu- We further consider real time constraints in stream pro-
rally compatible with object oriented design methodologies. cessing. In classic real time systems, real time constraints
Therefore, creating a flexible and fully automated transla- are usually applied to system response time. Other than
tion mechanism from the UML-based design language at classic logic constraints, constraints on stream processing
the top layer to SystemC appears to be a promising strategy. are often in the form of quality of service, which ensures a
processing rate of the stream. For example, an MPEG-2/4
video clip requires a minimum playback rate at 25 frames
2 Our Scope of Work and Related Work per second (fps). The number of pixels per frame depends
on the resolution settings during sampling. Similarly, for
In the domain of UML for real time systems, a large body MP3 audio clips, the choices of playback rates usually range
of work has been reported. Some UML extensions from from 64 Kilo bits per second (Kbps) to 256 Kbps depending
UML 1.x are proposed in [7]. Two instances of UML ex- on the requirements of playback quality.
tension and translation are [2, 15]. Some studies exploited The implication of the guarantee of the playback rate is
the possibility to describe a synchronous dataflow model [4] there are enough data stored in the buffer in front of the
and a model for incremental designs [3] in UML. A previ- playback device which is a real time client. Let ¼ denote
ous effort [13] focused on hardware generation from UML the buffer fill level of the playout buffer, ܴص to denote the
models without explicit UML specifications of stream pro- input stream of this buffer, ¼ represent the initial decoding
cessing. Another recent work [10] mainly studied the model delay, and denote the consumption rate of the real time
driven architecture approach via SystemC using UML 1.x. client assuming the initial buffer fill level is ¼. Then the
In this paper, we explore the suitability of UML 2.0 for constraint on the playout buffer underflowing is stated as:
system-level designs of stream processors. For this pur-
pose, we establish a design workflow that starts with UML ܴص ´ µ Ø ¼ Ø ¼ (1)
2.0, then SystemC as an intermediate language. Using this
workflow, we specify stream processors and applications in Similarly to the above limit on the minimum amount of
UML at an abstract level with Rhapsody. From the UML the stored data, there is constraint on the maximum amount
specifications, a stream processor simulator in SystemC is to avoid overflow.
generated. Here are the distinct features of our work: (a) to UML 2.0 Notations Used: To address the needs of abstract
ensure the maximum reusability and compatibility, we sim- representations of stream processors in UML, we resort to
ply use existing UML 2.0 notations without introducing any a few new notations introduced in UML 2.0, namely flow,
new ones; (b) in our UML specification, we explicitly de- composite classes, port, structural diagram and hierarchi-
scribe real time stream application features; (c) due to the cal statechart.
asynchronous nature in video and audio stream processing,
data packets are processed at various rates by multiple pro- media_src processing playout
cessing elements. Our SystemC simulator generated from token_out <<flow>> token_in
token_out
<<flow>>
token_in
UML designs supports the behavior of asynchronous flows.
This is in contrast to a recent study [4].
In the rest of the paper, we will discuss the UML model
stream_storage
of system level stream processing, describe the design
workflow, present the translator which can produce Sys-
temC code from restricted Rhapsody designs, and illustrate
the workflow with a case study. Some concluding remarks Figure 1. Functional Block Modelling of a
will follow the discussions. Stream Processor
3 Requirements of Real Time Stream Models In Fig. 1, a functional block model of a stream proces-
& UML 2.0 Notations Needed sor is shown. The model illustrates the exchange of infor-
mation “flow”s at the highest abstract level. Streams are
We view stream applications as operations on flows. represented in tokens which flow into and out of process-
Flows of stream packets undergo processing at different ing elements. The blocks in the functional block model are
stages of calculation. Representations of flow are manda- “composite classes” which decompose hierarchically into
tory in stream modelling. standard classes. The concept of composite class is similar
Modelling Requirements: Flows require entrances and ex- to the definition of “Metaclass” proposed by the UML for
its at processing elements. These gateways are also to be SoC forum. We expect these two notations will be merged
represented in abstraction with distinct attributes. in the final version of UML 2.0.
There is also a need to hierarchically specify the compu- The notation of “port” is new in UML 2.0. It is used
tation complexity inside processing elements. Since video in defining complicated incoming and outgoing interfaces.
and audio stream protocols have become very sophisticated, In Rhapsody’s terminology, the interface for incoming mes-
the complexity of calculation grows so hard that a non- sages is called a “provided interface”, similarly the interface
hierarchical representation would be not manageable. for outgoing messages is termed a “required interface”.
3. To decompose hard computation complexities, “hierar- stream application parameters in UML 2.0. The UML mod-
chical statecharts” are needed. Nested statecharts are al- els can be executed as early verifications.
lowed to represent sub-machines as part of the parent chart. The UML specifications are exported to XMI format files
The “structural diagram” is usually a detailed description which are translated by our translator to SystemC simulator
of functional block models. It emphasizes the structure of models in TLM and RTL styles. The simulator code under
the objects in a system, including types, relationships, at- proper coding constraints [13] can be compiled by the Syn-
tributes and operations. We will show an example in Fig. 5. opsys CoCentric SystemC compiler into gate level netlists
A stream processor needs stream traces to drive its ex- in Verilog, which are synthesizable into programmable ar-
ecution. The relationship is shown as a dependency from chitecture implementations. The coding constraints such
processing blocks to the stream storage package in Fig. 1. as using static memory instead of dynamic memory, struct
In the stream storage package, a trace manager manages rather than union, and call by value instead of call by refer-
stored trace files and delivers necessary stream attributes to ence, are imposed by the synthesizable subset of SystemC.
the processing blocks. The description of the stream storage In the meantime, verifications are carried out at multiple
package is an abstraction of memory management mecha- levels, i.e., UML specification, TLM style translation, RTL
nisms. The memory can be either physically centralized style translation and SystemC simulation.
RAM blocks or logically assembled cache lines associated
with each processing element. s e n
<
s
s
<
e
i
i
n
t
n
s
i
p
i
A constraint is a condition or restriction expressed in
# i f n } d e f F
# } d ; e f i n e F
Parser Template S C
S C
M
v
O
o
C
D
i
T
U
d
O
L
R
E
e
(
S C T H R
text. It is generally a Boolean expression that must be true TLM code
XMI
for an associated model element for the model to be con- doc Rhapsody
XM ITool i t
Ab stract
Syntax
s e n
<
s
s
<
e
i
i
n
t
n
s
i
p
i
sidered well-formed. To check the validity of a design in
# i f n } d e f F
# } d ; e f i n e F
tree S C
S C
M
v
O
o
C
D
i
T
U
d
O
L
R
E
e
(
S C T H R
simulation of the model of the design, a constraint is an as- B ehavioral code
sertion rather than an executable mechanism. It does not Synthesizable #
# }
i
d
s
;
f
e
e
n
f
en
<
s
} d
i
ts
<
e
e
n
i
i
n
f
e
t
n
s
exist in the final description for hardware synthesis.
S C M O D U L
v o i d
S C C T O R
S C T H
UML models in Rhapsody
RTL code
Processor Stream P ara.
Text D esc. Extract.
UML S pec. UML Exe c .
Figure 3. The Translation Process
XMI Data
TLM S
Tran
tyle
slation
Beha v or
l
i
Sty e Code 5 The UML2Code Translator
RTL S tyle RTL Style
Translation Cod e
SystemC
UML 2.0 is closer to SystemC than its predecessor since
Simulation
some of the new concepts have direct counterparts in Sys-
SystemC
Comp iler temC. For example, a meta-class corresponds to a mod-
Synthesis
ule in SystemC. During the code generation, we apply the
following mapping rules: (a) all components in the struc-
tural diagram, which are meta-classes, are translated into a
Figure 2. A UML 2.0 Based Design Workflow “sc module”; (b) the port type is determined by the nam-
ing convention of the port; (c) the statechart in each ac-
tive object is translated into a process whose method name
is “entry”. In this method, we map each statechart into
4 A UML 2.0 Based Design Workflow an unclocked “sc thread” for TLM style translation. For
RTL style translation, the mapping is a clocked process
We propose and implement a design workflow based “sc method”, which will be synthesizable; (d) the defini-
on UML 2.0 with SystemC as its intermediate language in tions of message structures are encapsulated in flow whose
Fig. 2. In this design workflow, our own efforts include counterpart is sc interface.
the steps of UML specification, transaction level modelling Besides the above general rules, the translator also adds
(TLM) style translation, register transfer level (RTL) style platform dependant hardware details such as considerations
translation and SystemC simulation. of reset, clock, and variable types. Additional constraints
The translator is based on the XML Metedata Inter- such as cache and memory configurations can be added to
change (XMI) format of UML representations made with make the translator generate more hardware features.
Rhapsody. From XMI representations, the translator gener- Figure 3 shows the translation workflow of UML2Code.
ates SystemC code in both TLM and RTL style. We start with a UML 2.0 model in Rhapsody. The design
To use the workflow, designers usually work with the model is accepted by Rhapsody’s XMITookit to generate
UML specifications only as the rest steps of the workflow corresponding XMI documents as inputs to our translator.
are automated. The major work of the designers is to vi- XMITookit preserves all the model information, and it is
sually specify the processor architecture parameters and a textual representation of the UML model. The generator
4. M PEG2 audi o representations in XML Metadata Interchange (XMI) for-
stream PB1 pl ayback
PE1 PE2
mat which is not supported by Rose RT.
M P3 UML Specifications: To detail the descriptions of “flow”
stream vi deo
PB2 driven activities in Fig. 2, we use a structural diagram in
pl ayback
Fig. 5 which describes the activities of instances of objects
whose realistic roles are shown in Fig. 4.
Figure 4. An Abstract Stream Processing SoC In Fig. 5, the ports belonging to object instances form the
communication channels for streams. The video and audio
streams are tokenized into token flows. Token IDs are ini-
tiated from video source or audio source, then pass through
parses the XMI documents and builds the internal represen-
processing elements to reach the video sink or audio sink.
tation of the model. The syntax tree is further processed to
Each processing element queries the trace manager for de-
compute and store some relations. The syntax tree holds all
tailed attributes of tokens. The processing elements take the
the data required to build different levels of code. By using
proper actions in accordance to the attributes of tokens.
different templates, the same model can be used to generate
code at different levels: TLM, Behavioral and RTL level. In UML 2.0, there is no need to inherit explicitly the
Behavioral and RTL code can be further synthesized into interface definitions, as was the case in UML 1.x, for the
gate-level netlists in Verilog/VHDL. ports where token IDs go through. The interface definitions
are built into the ports in UML 2.0.
The abstract operations in Fig. 5 represent a typical de-
6 A Case Study sign in stream processing. Some streams consist of large
packets of data. Each processing element does not need all
Video and audio decoders are typical streaming applica- the data in a packet. It is hence inefficient in hardware to
tions. Examples include the MPEG2 video decoder [9] and transfer complete packets through the processing elements.
MPEG Audio Layer 3 (MP3) decoder [8]. As a case study, In our example, only token IDs are passed through process-
we shall map these applications into an abstract SoC archi- ing elements, and each processing element only fetches nec-
tecture, then implement it using our design workflow. essary data for its processing from the trace manager. The
Experimental Setup: The process to decode MPEG2 video hardware costs will be reduced by this means.
streams consists of 4 major steps, namely variable length
decoding (VLD), inverse quantization (IQ), inverse discrete
cosine transition (IDCT) and motion compensation (MC).
We map VLD and IQ to the first processing element in the
SoC, IDCT and MC to the second element.
To play back MP3 audio streams, we usually need 8
steps, namely (1) synchronous and error checking, (2) Huff-
man decoding, (3) re-quantization, (4) reordering, (5) alias
reduction, (6) Inverse Modified Discrete Cosine Transform,
(7) frequency inversion, and (8) synthesis polyphase filter.
We assign the earlier 4 steps to the first processing element
in the SoC, and the rest 4 steps to the second element.
Another important design factor, scheduling, is also con-
sidered in our model. In our case study, we implemented the
TDMA scheduling policy as the scheduler. We summarize
the above settings as the abstract architecture in Fig. 4.
To obtain the requirements of execution cycles at differ-
ent stages, we use one of SimpleScalar’s [1] tools, “sim- Figure 6. A Stream SoC’s Class Diagram
profile” configured to the default values, to run reference
implementations of MPEG2 decoder and MP3 decoder sep- In Fig. 6, we use a traditional class diagram to specify
arately without scheduling. For each macroblock, processor the inheritances and association among the components of
cycles at different execution stages are captured and stored the SoC and management of stream traces. These entities
into trace files. For each video or audio stream, there are are classes which inherit or aggregate attributes from other
a set of trace files consisting of records for stream tokens. classes or interfaces.
Each record contains a token index number and token at- UML 2.0 supports hierarchical and concurrent state-
tributes such as the execution cycles. charts. We use traditional or single-layer statecharts to
To support real time applications, I-Logix Rhapsody is specify simply calculation logic flows inside each object.
preferred to Rational Rose Real Time (RT) since the lat- To describe complicated tasks, we use these new features
est Rhapsody provides more support for UML 2.0 notations to describe hierarchical states and concurrent calculations.
than Rose RT such as functional block modelling, flow and For example, a hierarchical state containing concurrent sub-
concurrent state charts. Moreover, Rhapsody can produce machines in the “trace manager” is shown in Fig. 7.
5. Figure 5. A Structural Diagram of a Stream Processing SoC
H ier ar c hic alS at
t e
r eady For Quer y r eady For Quer y
quer y _s end_pe1 quer y _s end_pe2
r ec v Pe1Quer y > r ec v Pe2Quer y . .
.
Figure 7. A Hierarchical State in an Object
Figure 8. A Constraint Anchored to an Object
Similar to assertions, constraints have to be checked con-
stantly during processing of the streams. A constraint ex-
ample is shown in Fig. 8 for illustration. The constraint has
a dependency relationship with the object. A violation of Figure 9. Communications among Modules
the constraint incurs a pause in the playback client, conse-
quently, users observe breaks in the playback video or audio
clips. The number of constraint violations is recorded as a port”; incoming ports have names beginning with “inport”;
metric of quality of service. bi-directional ports are identified as “inoutport*” in Fig. 5.
As shown in the example, designers only need to deal Regarding the code efficiency, for the settings in the ex-
with structural diagrams, class diagrams and statecharts for ample, the size of the generated SystemC code is around
specifications in UML. It is straight forward to reuse the 3100 lines. The code generation time for both RTL style
specifications and quickly modify designs in UML 2.0. and TLM style is less than 10 seconds. It is also interesting
UML Execution: UML models are executable in the Rhap- to note that the RTL style code may have a smaller size than
TLM style code, but always a longer execution time.
sody runtime environment. This feature allows designers to
verify their designs at very early stage of design workflow. To illustrate the mapping results, we take the RTL style
declaration part of the SystemC of the first processing ele-
UML 2.0 visualizes the communication with a new fea-
ment “pe stage1” as the example.
ture message sequence chart(MSC). Fig. 9 is the screen shot
of a MSC generated during the execution of UML models. SC_MODULE( pe_stage1) {
In this MSC, tokens trigger events which are represented as //define default ports
messages passed among SoC modules. We can trace the ex- sc_in_clk CLK;
ecution of video tokens 3, 5 and audio tokens 12, 14. The sc_in<bool> reset;
example shows another clear benefit of UML 2.0 for system //define the outgoing ports
level design of stream processing SoC. sc_out<bool>
To achieve a faster execution, we can also disable the trace_manager_query_send_pe1;
MSC generation during execution. The option is observed sc_out<int >
trace_manager_query_send_pe1_qTokenNum;
to save the execution time by about 30%. sc_out<bool>
SystemC Code Generation: To facilitate the translation pe_stage2_in_token_pe2;
synthesis, we apply an intuitive naming conventions to the sc_out<int >
port names. The names of outgoing ports start with “out- pe_stage2_in_token_pe2_tokenNum;
6. //define incoming ports the spirit of stream applications by emulating the processing
sc_inout<bool> in_video_pe1; of tokenized streams. A case study shows SystemC imple-
sc_in<int > in_video_pe1_vTokenNum; mentation is also synthesizable with Synopsys tools. As the
sc_inout<bool> query_reply_pe1; future work, we will extend our work by modelling addi-
sc_in<int > query_reply_pe1_execTime; tional hardware features of stream applications in UML 2.0
//token attributes
public: to enable generation of full-fledged processor designs using
int vTokenNum; our framework.
public:
int vExecTime; ......
//processing status References
public:
int bufLevel;
private: [1] T. Austin, D. Burger, G. Sohi, M. Franklin, S. Breach, and
int state; ...... K. Skadron. The simplescalar architectural research tool set.
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//define the clocked thread models. In The 6th European SystemC users Group Meeting,
SC_METHOD(entry); 2002.
sensitive_pos<<CLK; [3] P. Green and M. Edwards. The modelling of embedded sys-
} ... tems using hasoc. In Proceedings of Design, Automation and
} Test in Europe Conference and Exhibition, 2002, pages 752–
To represent the semantics of assertions, we propose 759, March 2002.
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[5] I-LOGIX. Rhapsody in c++. In Available on-
//AFTER(t>itsVideo_sink.D) line, http://www.ilogix.com/rhapsody/rhapsody c plus.cfm.
// ALWAYS(itsVideo_sink.B>0) I-Logix Incorporation, 2004.
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