1. Dishanth
Akshaya house opposite Kulal bhavan
Thadambail,Surathkal
D.K. Dist, Karnataka State
India
Mobile No: 9845538403
OBJECTIVES:
To work in a challenging dynamic environment to keep adding value to myself and
simultaneously contribute to the growth and success of organization.
Educational qualification :
Examination Specialization Institution Board/Univer
sity
Month and
year
Percentage
(%)
BE E&C St Joseph
Engineering VTU June 2016 79.455
College,
Mangalore
Sharada PU Pre-University
P.U.C. PCMS College, education, March- 92.0000
Kodialbail Bangalore 2012
Mangalore
S.S.L.C. S.S.L.C. Holy Family Karnataka
SSLC
April-2000 88.32
English Medium Board
school.
Surathkal.
Project:
1.
Project name Switched DC power supply design
Project description This projects mainly concentrates on design of supply using
bridge rectifiers .It consists of 3 output terminals which is
designed for the output voltage of 12v, 5v and 3.3v.
2.
Project name A Classroom mic system
Project description mic system is made using simple components so that its cost
is cheap and good quality.

2. 3
Project name Two bit magnitude Comparator using GDI technique
Project description In this the circuits of Conventional two bit magnitude
comparator and GDI based magnitude comparator is
simulated using cadence tool. And proved that GDI technique
reduces the area and power, increases the speed than the
conventional two bit .
Tool and technology used Cadence : NC launch , simvision at 45 nm technology.
4.
Project name Design of Turbo encoder
Project description This project mainly concentrates on the design and
verification of turbo encoder .
Language Verilog
Tools used Cadence : Nc launch ,simvision
Technology 45 nm
5.
Project name Cloth line drier system
Project description This is the system design project in which system is
designed ,verified and layout is done.
Tools used LT Spice for simulations and magic for layout
Technology 0.8 um technologys
6.
Project name Verification of Cache system.
Project description This project mainly concentrates on the verification of
cache by building environment like driver ,monitor
,transactions, scoreboard and mailbox.
Language System verilog
Tools used Cadence :IRUN tool
Training :
1. Undergone trainning in System design in KarMic .
2. Hands on experience on ASIC design tools in Cadence
Compiler NC Launch
Simulator Simvision
Synthesis Encounter RTL ComplierNC Launch
3. Undergoing trainning in verification feild since 6 months in KarMic .

3. Language Verilog System Verilog
Tools used Cadence,smash,modelsim
, smash
Cadence : IRUN and IMC
Methodology Universal verification methodology (UVM)
Tools used Cadence ,EDA Playground
4. Trainned in Standard cell layouts and digital circuits layout in KarMic .
Tools used Magic
Technology .8 um ,45 nm
Experience:
1. Worked as a part time tuition teacher in “ Akshaya tutorials” from 2014-2016 .
2. From past 6 months working in KarMic designs Privte LTD. Manipal
Computer Skills:
Programming
language
C , C++ , verilog , VHDL ,8051 micro controller ,8086 micro
processor
Software Multisim , Fritzing , Smash , modelsim ,Ltspice, Magic , Matlab ,
Xilinx ISE .
PERSONAL PROFILE
Date of Birth 18.05.1994
Age 22
Gender Male
Name of Father Late Naveen K
Nationality Indian
Languages Known English, Kannada and Tulu.