8051 address map

1. Pari vallal Kannan
Center for Integrated Circuits and Systems
University of Texas at Dallas
8051 Interfacing: Address Map
Generation
EE4380 Fall02
Class 6

2. 12-Sep-02 2
8051 Interfacing
l Address Mapping
– Use address bus and data bus
– Interfaced device show up as memory locations from the
processor
– They use up some of the address space
– Memories, displays etc
l I/O Mapping
– Connect the devices to the I/O Ports of the processor
– Don’t use up address space
– Sensors, pushbuttons, LCDs, motors, LEDs etc

3. 12-Sep-02 3
8051 – Address Generator
l Address Generator is a piece
of hardware that produces
unique addresses to each
interfaced device
l Each Interfaced Device can
use up 1 or more locations
from the address space of the
processor
– Memories typically use up in
Kilobytes (2K, 4K, 8K etc)
– Other devices typically use a
few (<16) addresses
l Addresses of devices should
not overlap
8051
A[15:0]
Addr. Gen
Device 1
Device 2
Device 3
CE
CE
CE
f1
f2
f3
D[7:0]
D[7:0]
D[7:0]
D[7:0]
A[15:0]
A[15:0]
A[15:0]

4. 12-Sep-02 4
What is needed ?
l Need to know the
following for all the
devices before address
generator can be
designed
– Base address of each
device
l Where it starts in the
address map
– Size of the device
l How much of the address
space it uses up
Code Memory Data Memory
0x0000
0x4000
0x1000
0x5000
RAM1 32K
0x0000
0x8000
0xF000
LCD 8b
LEd 2b
Code RAM 4K
Code ROM1 4K

5. 12-Sep-02 5
Example –1 : 2K Memory at 0x0000
l Pins : address - A10 to A0, Data – D7 to D0,
_RD, _WR, _CE
l Base address = 0x0000
l Size = 2k (2 *1024 = 2048 bytes = 0x0800)
l Address Map occupancy
– 0x0000 to 0x07FF that is,
– 0000 - 0000 - 0000 - 0000 binary to
– 0000 - 0111 - 1111 - 1111 binary
l 11 lowest address bits A10 to A0 have to be
connected to the address pins on the memory

6. 12-Sep-02 6
Example –1 : (contd.)
l Unused address bits are
– A15 to A11
l Base address is 0x0000
l CE has to be generated
if all the unused address
bits are logic-0
– CE is active low
l _CE = A15 + A14 + A13
+ A12 + A11
l Then connect _RD and
_WR
0
1
1
1
1
1
0
1
X
X
X
X
0
X
1
X
X
X
0
X
X
1
X
X
0
X
X
X
1
X
0
X
X
X
X
1
_CEA11A12A13A14A15
Truth-Table for CE

7. 12-Sep-02 7
Ex-2: Same Memory at 0x4000
l Base address is 0x4000
– 0100 0000 0000 0000
l Size is 2K
l Unused address bits
– A15 to A11
l CE has to be generated
as per the truth-table
l Expression is
1
0
1
1
1
1
1
1
1
X
0
0
1
0
1
X
0
X
X
1
1
X
0
X
X
X
X
on
0
1
1
1
1
1
so
X
0
X
X
X
X
and
_CEA11A12A13A14A15
1112131415_ AAAAACE ••••=

8. 12-Sep-02 8
(In)Complete Addressing
l Complete addressing:
– Use all unused address bits to generate CE
l Incomplete addressing
– Use a sub-set of the unused address bits
– Used to reduce the address generator complexity
– Produces address aliases (same device at multiple addresses)
l Example
– 2K memory at 0x0000, we used A15 to A11
– Instead just connect A11 to _CE
– Same 2K memory device will then be aliased for all values of
A15 to A12
l 0x0000, 0x1000, 0x2000, 0x3000, …. , 0xF000
– Address generator became very simple, but we lost a lot of
address space

9. 12-Sep-02 9
74138 Decoder for Address Gen.
l 3 to 8 decoder, available in a single
DIP package.
l Takes 3 address lines and
generates complete addressing
among those
l Example
– Connect A15, A14, A13 to the
decoder inputs
– Decoder outputs give base
addresses for
l 0x0000, 0x2000, 0x4000, 0x6000,
0x8000, 0xA000, 0xC000, 0xE000
l For more complicated address
decoding use programmable
devices like PALs, PLDs or FPGAs
C
B
A
G2
G1
Y0
Y1
Y2
Y7
74LS138
A15
A14
A13
GND
Vcc

10. 12-Sep-02 10
External (pure) Code Memory
l Could be RAM or ROM
l Address generation as per standard procedure
l Connect _PSEN to the _OE of the memory
device
l _RD and _WR are ignored
– Don’t connect these 8051 pins to the memory
device
l Connect Data bits D7-D0 of the memory and
the 8051

11. 12-Sep-02 11
External (pure) Data Memory
l Could be RAM or ROM
l Address generation as per standard procedure
l Connect _RD from the 8051 to OE of the
memory
l Connect _WR from the 8051 to WR of the
memory
l Ignore _PSEN
l Connect Data bits D7-D0 of the memory and
the 8051

12. 12-Sep-02 12
External Code + Data Memory
l Could be RAM or ROM
l Address generation as per standard procedure
l Logically AND _PSEN and _RD and then
connect to the OE of the memory
l Connect _WR from the 8051 to WR of the
memory
l Connect Data bits D7-D0 of the memory and
the 8051

13. 12-Sep-02 13
External Non-Memory Devices
l Same procedure as for interfacing memory
l Only difference is that these devices have
smaller sizes and use lesser portions of the
address space
l Example:
– 8 LEDS connected to a 8bit latch. The latch is
address mapped to 0xF000. Size is 1byte
– 8255 I/O device memory mapped at 0xD000. Size is
4 bytes

14. 12-Sep-02 14
Case Study - Sample 8051 System

15. 12-Sep-02 15
Case study – Sample 8051 System
l 8031 based
– No on-chip ROM, 128 bytes on-chip RAM, 18.432MHz oscillator,
74HC373 based ADBUS demuxer
– 8Kx8 external code memory in 28C64 EEPROM
– Code memory at 0x0000
– 32Kx8 external code+data overlapped in 62256 SRAM.
– SRAM mapped at 0x8000
l SRAM and EEPROM share code memory space. So
decoding needed.
– A15 line is used for the purpose
– A15 = 0 è EEPROM is selected (hence 0x0000)
– A15 = 1 è SRAM is selected (hence 0x8000)
l RS232 serial interface available for PC communication
l Monitor programs available

16. 12-Sep-02 16
Reverse Engineering
l Given a system with little or no docs, determine
the function, schematic, etc
l Vendors provide poor support.
l Reverse Engineering is fun !
l Usually No schematics are available
l Software is also undocumented !
l On-chip code could be copy protected !!

17. 12-Sep-02 17
Next Class
l 8051 I/O Mapped interfacing
l 8051 and the 8255 I/O device
l Example – Interfacing a character LCD