1. System-on-Chip Design
UML Profiles
Pierre Boulet – DaRT project-team
Télécom Lille 1 – Septembre 2011
2. Profils UML pour l’embarqué
Trends Towards Modeling
UML for Embedded Systems
SysML
Electronic System Level
MARTE
3. Profils UML pour l’embarqué
Trends Towards Modeling
UML for Embedded Systems
SysML
Electronic System Level
MARTE
4. Reuse
IP
IP = Intellectual Property
HW or SW block
designed for reuse
need of standards (VSIA, IP-Xact)
platform based SoC design
organized method
to reduce cost and risk
by heavy reuse of HW and SW IPs
steps in reuse
block → IP → integration architecture
5. Raising the Abstraction Level
ESL (Electronic System Level)
from RTL to TLM or higher
from VHDL to SystemC to UML
HW/SW co-design
need new tools
consider the whole system
large optimization potential
combination of formal, semi-formal and non
formal techniques
6. Separation of concerns
by metamodeling
metamodel = domain specific language
one metamodel for one goal
hide the unneeded details for the task at hand
allows reuse
unavoidable considering the required
productivity
at the heart of platform based design
design team management
each team member has its own view
on shared models
rely on a common language to ease
communication
7. Automation
handling the complexity
habit of the semiconductor industry
capitalize the knowledge in the tool
through model transformations
separation of buisness logic from technology
automatic verification
tool integration
simulation / test / analysis
automatic code generation
8. Profils UML pour l’embarqué
Trends Towards Modeling
UML for Embedded Systems
SysML
Electronic System Level
MARTE
9. UML 2.0
http://www.uml.org/
adopted in 2005
superstructure (definition of the diagrams)
infrastrucutre (base classes of UML 2.0 and
MOF 2.0), OCL, diagram exchange format
new features with respect to UML 1.x
more abstraction
clear separation of structure (static) and
behavior (dynamic)
new diagrams: composite structure, activity +
action language
more automation
more precise semantics
diagram exchange format (XMI 2.0)
10. Profiles for SoC Modeling
System level
SysML
MARTE
Electronic System Level
UML for SoC
UML for SystemC
others (YAML, UMLSC, ...)
11. Profils UML pour l’embarqué
Trends Towards Modeling
UML for Embedded Systems
SysML
Electronic System Level
MARTE
12. SysML
system engineering modeling language
domain specific (SysML) vs general purpose
(UML)
remove the software bias from UML
remove part of UML
add system specific constructs
as a UML profile
13. corresponding specification of the UML extensions is described in Parts II - IV of th
A describes generalized features of diagrams, such as their frames and headings.
SysML Diagrams (1/2)
SysM L
D ia gr a m
Behavior Re quir e m e nt
D ia gr a m Diagram
Activity Sequence State Machine Use Case Block Definitio
Diagram Diagram Diagram Diagram Diagram
Same as UML 2
Modified from UML 2
New diagram type
Figure 4.4 - SysML Diagram Taxonomy
14. xtensions is described in Parts II - IV of this specification. The Diagram Annex
ms, such as their frames and headings.
SysML Diagrams (2/2)
SysM L
D ia gr a m
Re quir e m e nt Structure
Diagram D ia gr a m
e Machine Use Case Block Definition Internal Block
Package Diagram
iagram Diagram Diagram Diagram
L2 Parametric
Diagram
UML 2
type
15. Profils UML pour l’embarqué
Trends Towards Modeling
UML for Embedded Systems
SysML
Electronic System Level
MARTE
16. UML for SoC
concepts very close to SystemC
allow automatic SystemC skeleton code
generation
abstraction level
from transactional level modeling (TLM)
to register transfer level (RTL)
mainly uses the composite structure diagram
20. Example: Communication by FIFO
Structure Diagram
2004/10/26 20:52
port name : in
port name : out
interface direction : input initialization parameter : 0 interface direction : output
protocol interface name : sc_ in_
fifo_ if<data1>
protocol interface name : sc_ out_
fifo_ if<data3>
class name : parent
process function :
fifo:sc_fifo<data2>
class name : child1
instance name : func1
process function : entry
port name : out class name : child2 port name : in
interface direction : out instance name : func2 interface direction : in
protocol interface name : sc_ out_
fifo_ if<data2> process function : entry protocol interface name : sc_ in_
fifo_ if<data2>
Fig. 17 Structure diagram and attribute of each object, tagged value
The channel is described in the UML diagram as shown below. Here the FIFO channel of SystemC
(sc_fifo) is used as a channel with buffer size = 16 (default value of sc_fifo class). The buffer size is given
as an initialization parameter at the instantiation of the channel. (In the figure below, attributes, and/o
template arguments of buffer size are not shown.)
22. Example: Shift Register
Structure
0/26 20:52 Diagram
(a) N : int
ShiftReg (d)
I I O O
M : reg[N]
C : sc_fifo<int> [N- 1] (c)
(b)
inv: N > 1
inv: M[0].I.sc_ in_
fifo_ if<int>- >exists(I) - - (a)
inv: Sequence{ 1..N- 1 }- >forAll(n | M[n].I.sc_ fifo<int>- >exists(C[n])) - - (b)
inv: Sequence{ 0..N- 2 }- >forAll(n | M[n].O.sc_ fifo<int>- >exists(C[n]) - - (c)
inv: M[N- 1].O.sc_ out_
fifo_ if<int>- >exists(O) - - (d)
Fig.24 Example of template module
23. UML for SystemC
allow to generate complete SystemC code
expose all SystemC concepts in the UML profile
structure (similar to UML for SoC profile)
behaviour (actions in state machines)
tool specific implementation
takes advantage of the tool’s code generation
capacity
24. Profils UML pour l’embarqué
Trends Towards Modeling
UML for Embedded Systems
SysML
Electronic System Level
MARTE
25. Modeling and Analysis of Real-Time
and Embedded systems
Request for Proposal
http://www.omg.org/cgi-bin/
doc?realtime/2005-2-6
published February 2005
Current status
Version 1.0 available since November 2009
http://www.omg.org/spec/MARTE/
26. Requirements
Scheduling, Performance and Time profile
evolution
designed for UML 1.x
influence of the QoS and Fault Tolerance profile
Real-Time and Embedded System modeling
embedded system programming
limited resources, subject to constraints,
heterogeneity, distributed
reactivity
cyclic behaviour, modes of operation
control/command
intensive data flow
systematic signal processing
intensive data processing
27. RTES Specific Needs
standard language
to ease communication in the design team
common paradigm for hardware and software
modeling
Y-model approach (application, hardware
architecture, allocation)
Model Driven Engineering
time modeling
asynchronous/causal
synchronous/clocked
real/continuous
28. Schedulability and Performance
Analysis
rich set of measures
response time, delays, resource utilisation,
demand
statistical measures or bounds
schedulability analysis
WCET, ACET, BCET
need for variables and expression
manipulation (see SPT)
29. Current Version
See the official tutorial
(http://www.omgmarte.org/Tutorial.htm).
30. Conclusion
SoC modeling: an active research area
several proposals
at different abstraction levels
basic constructs
composite structure diagram
hierarchical
component based
profiles
