1. POLITECNICO DI MILANO
SiLLis: A Simplified Language
For Monitoring and Debugging
FPGA-based Systems
Paolo Roberto Grassi
Relatore: Prof. Donatella Sciuto
Correlatore: Ing. Marco Domenico Santambrogio
2. Outline
Introduction
Thesis Goals
State of Art
Problem Definition
Listener: General Structure
SiLLis
Grammar
Paths and Guardians
Translation
Case Studies
Reconfiguration Monitor
Performance Monitor
Concluding Remarks
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3. Introduction
The process where a system is exercised and its
resulting response is analyzed to ascertain whether it
behaved correctly or not is called testing.
Debugging is a methodical process of finding and
reducing the number of bugs, or defects, in a
computer program or a piece of electronic hardware
thus making it behave as expected
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4. Thesis Goals
Definition of a high level language for the convenient
description of hardware components for monitoring of
communication lines on FPGAs
The project aims at overcoming the following limits
that affect commercial and non-commercial tools :
Debugging Invasivity
Limited Debugging Period
Quality of Gathered Data
The project is focused on on-line, self, system-level,
at-speed, compact, in-circuit testing
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5. State of Art
Lots of solutions were proposed to solve the problem
of FPGA-debugging:
External devices connected to the I/O pins of the FPGA
Internal components with TAP (Test Access Port)
interface
Clock Gating [*]
[*] J.N. Tombs, et al. “The implementation of a FPGA hardware debugger system with
minimal system overhead”, in FPL, 2004, pg. 1062-1066
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6. State of Art – Commercial Solutions
Xilinx® ChipScope Pro™
ChipScope inserts logic analyzer, bus analyzer and virtual I/O
low-profile software cores directly in the system, allowing the
possibility to view any internal signal or node, including
embedded hard or soft processors
Synplicity® Identify®
It allows you to navigate your design graphically and mark
signals directly in RTL as probes or sample triggers
SignalTap® II by Altera®
Provides a solution that allows you to examine the behavior of
internal signals, without using extra I/O pins, while the design
is running at full speed on an FPGA device
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7. Problem Definition
Blind-Monitor: It captures the data every clock cycle,
store it in memory or transfer it directly to an external
application
Monitoring Time Memory Requirement
M0
t M t0 ( f n Tr )
f n Tr
Listener: It read the data, filter that and, eventually,
recognize and understand if something happens
Monitoring Time Memory Requirement
M0
t M t0 ( f n Tr )
f n Tr
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8. Listener: General Structure
In order to have a feasible, non-stopping, debugging
activity, the following relation must be satisfied:
nH 1 nO 1
h ( k , i ) f SYS e ( k , i ) f OUT
i 0 k 0 i 0 k 0
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9. SiLLis: Simplified Language for Listeners
parameter
LOW_TRIGGER = 3;
Every listener is composed of: HIGH_TRIGGER = 9;
end parameter;
Parameter Definition (optional)
interface
Interface Definition (required) input : in STD_LOGIC_VECTOR(0 to 8);
increment : in STD_LOGIC_VECTOR(0 to 8);
Internal Variable Definition end interface;
(opt.) internal_variables
data : STD_LOGIC_VECTOR(0 to 8);
end internal_variables;
External Variable Definition
(opt.) external_variables
reset_data : STD_LOGIC_VECTOR(0 to 8);
end external_variables;
Paths (optional)
path (increment>0) is
Guardians (optional) data = reset_data;
sleep(1);
It provides some Special if input < LOW_TRIGGER then
flush(data);
(predefined) functions: else
loop_until input > HIGH_TRIGGER then
data = data + increment;
sleep(n) flush(data)
end loop_until;
wait(A) end if;
end path;
reset guardian (input>HIGH_TRIGGER) is
flush(A) wait(input<LOW_TRIGGER);
reset;
end guardian;
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10. SiLLis: Paths and Guardians
Paths and guardians contain the code related to the filtering logic
Each guardian can contain a set of paths, but paths cannot
contain guardians
The effect of the activation is different for paths and guardians:
When a path is activated, it inhibits the activation of other
paths
When a guardian is activated, it inhibits the activation of both
paths and guardians. If a path is activated, its execution is
temporary frozen
Condition Current State Effect
Path False Not important Nothing
Path True No guardians or paths activated Path activated, other paths inhibited
Path True One guardian or path activated Nothing (path inhibited)
Guardian False Not important Nothing
Guardian True No guardians activated Guardian activated, everything inhibited
Guardian True No guardians activated, path activated Guardian activated, path frozen
Guardian True One guardian activated Nothing (guardian inhibited)
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11. SiLLis State Machine Manager
Paths State Machine
The Guardians State Machine controls
the output of the two state machines
It is activated by triggers at runtime
It blocks the Paths State Machine in
order to manage the event
Guardians State Machine
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12. SiLLis Translator
The SiLLis description is translated into synthesizable
VHDL in order to be integrated into the system
To easily perform the VHDL composition, SiLLis uses
vMagic, a Java API that allows to write VHDL from Java
Class definitions
Listener State
SiLLis Machine
Description VHDL
SiLLis vMagic Input/Output
Parser
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13. First Case Study: Reconfiguration Monitor
The first case study used to prove the usability of SiLLis is a
runtime monitor for dynamic reconfigurability
The system contains a controller for the pendulum that is
reconfigured at runtime
A SiLLis component catches the partial bitstream that goes to the
reconfiguration controller filtering all the other unuseful data
Reconfiguration Pendulum
SDRAM
Controller Controller
BUS
Processor SiLLis Listener
M E1 E2
Motor
Encoders
Visualization
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14. First Case Study: Reconfiguration Monitor
SDRAM Pendulum Controller
Reconfiguration
BUS
Controller
Processor
SiLLis Listener
M E1 E2
Motor
Encoders
Visualization
1. Processor Request
2. Reconfiguration Controller SDRAM Access
3. Bitstream Transfer
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15. First Case Study: Experimental Results
Blind-Monitor Area Occupation
Logic Utilization Used Available (VP30) Utilization (VP30)
Number of Slices 132 27.392 1%
Number of Slice Flip-Flops 131 27.392 1%
Number of 4 input LUTs 193 13.696 1%
SiLLis Reconfiguration Listener Area Occupation
Logic Utilization Used Available (VP30) Utilization (VP30)
Number of Slices 134 27.392 1%
Number of Slice Flip-Flops 133 27.392 1%
Number of 4 input LUTs 234 13.696 1%
Throughput comparison
Logic Utilization Data Size Available (VP30) Utilization (VP30)
Blind-Monitor 64 bit 100 MHz 800 MB/sec
SiLLis Listener 200 KB 10 Hz 2 MB/sec
(64-bit PLB bus running at 100 MHz)
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16. Second Case Study: Performance Monitor
SiLLis listener are integrated
into the GigaNoC system
During the process of data
gathering performed by the
listeners (L), additional
information is added to the
data
The information contains the
timestamp of the current
clock cycle and the
indentifier of the signal
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17. Second Case Study: Experimental Results
FPGA-resource requirements on a Xilinx Virtex-II 8000
Component Slices Flip Flops LUTs BRAMs
Processing Element (PE) 15.362 8.719 22.233 80
Switch Box (SB) 14.133 13.340 16.383 -
Listeners (L1,L2) 171 110 267 -
Delay Statistics of
GigaNoC traffic
load experiments
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18. Concluding Remarks
The state of art presents a set of commercial and non-commercial
solutions
In order to solve problems of blind-monitors, listeners were
proposed
Pre-defined structure of a listener permits the definition of
languages for its convenient description
SiLLis combines an easy grammar and a powerful set of
instructions
The power of SiLLis has been shown in the areas of network-on-
chip and reconfigurable architectures
Future Works:
Additional functions can be integrated, which will be useful to
describe the desired behavior more confortably
Different application fields: Parallel Computing, Multi-
Procesor Systems, Multi-FPGA Systems, Adaptive Systems
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