1. National Institute of Technology Andhra Pradesh
Department of Electronics and Communication Engineering
FPGA Design
Course no.:EC463
A report on Xilinx Zynq -7010
By:
R.V.S. Nivas kumar
611663
IV B.Tech
3. INTRODUCTION:
In June 2010, Xilinx introduced the Xilinx 7 series: the Virtex-7, Kintex-7, and Artix-7
families, promising improvements in system power, performance, capacity, and price. These
new FPGA families are manufactured using TSMC's 28 nm HKMG process. The 28 nm
series 7 devices feature a 50 percent power reduction compared to the company's 40 nm
devices and offer capacity of up to 2 million logic cells. In the very next year, Xilinx
introduced the Zynq-7000 family, which integrates a complete ARM Cortex-A9 MPCore
processor-based system on a 28 nm FPGA for system architects and embedded software
developers.
The Zynq-7000 family of SoCs addresses high-end embedded-system applications, such as
video surveillance, automotive-driver assistance, next-generation wireless, and factory
automation. Zynq-7000 integrate a complete ARM Cortex-A9 MPCore-processor-based
28 nm system. The Zynq architecture differs from previous marriages of programmable logic
and embedded processors by moving from an FPGA-centric platform to a processor-centric
model. For software developers, Zynq-7010 appear the same as a standard, fully featured
ARM processor-based system-on-chip (SOC), booting immediately at power-up and capable
of running a variety of operating systems independently of the programmable logic. In 2013,
Xilinx introduced the Zynq-7100, which integrates digital signal processing (DSP) to meet
emerging programmable systems integration requirements of wireless, broadcast, medical
and military applications.
The new Zynq-7000 product family posed a key challenge for system designers, because
Xilinx ISE design software had not been developed to handle the capacity and complexity of
designing with an FPGA with an ARM core. Xilinx's new Vivado Design Suite addressed
this issue, because the software was developed for higher capacity FPGAs, and it
included high level synthesis (HLS) functionality that allows engineers to compile the co-
processors from a C-based description.
The AXIOM, the world's first digital cinema camera that is open source hardware, contains a
Zynq-7010.
The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing
performance, power, and ease of use typically associated with ASIC and ASSPs. The range
of devices in the Zynq-7000 family allows designers to target cost-sensitive as well as high-
performance applications from a single platform using industry-standard tools. While each
device in the Zynq-7000 family contains the same processing system(PS), the programmable
logic (PL) and I/O resources vary between the devices.
4. FEATURES:
• Dual- or Single-core ARM Cortex-A9 with CoreSight Technology
➢ Unmatched performance-per-watt
➢ ARM Cortex-A9 processor chosen for optimal performance-per-watt
ratio in popular applications
➢ Single and double-precision floating point support
➢ Up to 1GHz operation
• Largest and Highest-Performance Memory System
➢ 512KB L2 Cache
➢ 256KB On-Chip Memory fits an entire real-time operating system
➢ Integrated memory controllers support up to DDR3-1866
• Integrated Memory Mapped Peripherals
➢ 2x USB 2.0 (OTG) w/DMA
➢ 2x Tri-mode Gigabit Ethernet w/DMA
➢ 2x SD/SDIO w/DMA
➢ 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 32b GPIO
• All Programmable Power Management
➢ Flexible, tunable power envelope for adjustable processor, interconnect,
and memory speeds
➢ ARM low power modes
➢ Partial reconfiguration to reduce programmable logic requirement
• AMBA Open Standard Interconnect Ports
➢ 64-bit AXI ACP port for enhanced hardware acceleration and cache
coherency for additional soft processors
➢ Up to 100Gb/s bandwidth between PS and PL
• Massive Parallel Signal Processing
➢ Dedicated, full custom, low-power DSP slices
➢ Up to 2,020 DSP blocks delivering over 2,662 GMACs
• Advanced Security, Safety & Reliability
➢ Processor-first boot using on-chip-memory with secure ROM code
➢ Anti-Tamper (AT) technology can ‘zeroize’ the device if tampering is
sensed
➢ Secure system boot with RSA-based authentication, AES-256 decryption,
and SHA-256 data authentication
Full ARM TrustZone support
5. Table 1:An overview of features in Zynq-7010
Device Name Z-7010
Part Number XC7010
ProcessingSystem(PS)
Processor core Dual -Core ARM Cortex-A9 MP Core
Processor extensions NEON™ SIMD Engine and Single/Double Precision Floating Point
Unit per processor
Max Frequency 866MHz
L1 Cache 32KB Instruction, 32KB Data per processor
L2 Cache 512KB
On-Chip Memory 256KB
External Memory Support DDR3, DDR3L, DDR2, LPDDR2
External Static Memory Support 2x Quad-SPI, NAND, NOR
DMA Channels 8 (4 dedicated to PL)
Peripherals 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
Peripherals w/built in DMA 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
Security RSA Authentication of First Stage Boot Loader,
AES and SHA 256b Decryption and Authentication for Secure Boot
Processing System to
Programmable Logic Interface Ports
(Primary Interfaces & Interrupts Only)
2x AXI 32b Master, 2x AXI 32b
4x AXI 64b/32b Memory
AXI 64b ACP
16 Interrupts
ProgrammableLogic(PL)
7 Series PL Equivalent Artix-7
Logic Cells 28K
Look-Up Tables(LUTs) 17,600
Flip-Flops 35,200
Total Block RAM 2.1Mb
(#36KB Blocks) (60)
DSP Slices 80
Analog Mixed Signal(AMS)/XADC 2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
Security AES & SHA 256b Decryption & Authentication for Secure
Programmable Logic Config
Speed Grades
Commercial -1
Extended -2,-3
Industrial -1,-2,-1L
Approximate ASIC Gates ~430K (30k LC)
Extensible Block RAM 240KB
Peak DSP Performance (Symmetric
FIR)
58 GMACS
6. BLOCK DIAGRAM AND ARCHITECTURE:
Fig 1:Block diagram of Zynq-7010
The Zynq-7010 architecture enables implementation of custom logic in the PL and custom
software in the PS. It allows for the realization of unique and differentiated system functions.
The integration of the PS with the PL allows levels of performance that two-chip solutions
(e.g., an ASSP with an FPGA) cannot match due to their limited I/O bandwidth, latency, and
power budgets.
Xilinx offers a large number of soft IP for the Zynq-7000 family. Stand-alone and Linux
device drivers are available for the peripherals in the PS and the PL. The Vivado Design
Suite development environment enables a rapid product development for software, hardware,
and systems engineers. Adoption of the ARM-based PS also brings a broad range of third-
party tools and IP providers in combination with Xilinx’s existing PL ecosystem.
7. The inclusion of an application processor enables high-level operating system support, e.g.,
Linux. Other standard operating systems used with the Cortex-A9 processor are also
available for the Zynq-7010.
The PS and the PL are on separate power domains, enabling the user of these devices to
power down the PL for power management if required. The processors in the PS always boot
first, allowing a software centric approach for PL configuration. PL configuration is managed
by software running on the CPU, so it boots similar to an ASSP.
Fig 2:Architectural overview of Zynq-7010
8. PROCESSOR SYSTEM(PS)
Dual Core Cortex ARM A9
– NEON, 512 KB L2 cache
– 256 KB On-Chip-Memory (OCM)
DDR Interface – DDR3 Performance
– High BW utilization
Config & Legacy Memory I/F
– Quad-SPI, NOR, NAND
System Level Peripherals
– Clock generation, Counter Timers
– 8 Channel DMA controller
– Coresight Debugging
Standard Peripherals – GigE …
– Available to PS IO or to Programmable Logic
PROGRAMMABLE LOGIC(PL)
Programmable Logic Resources
– 30K – 235 K Logic Cells
– Dedicated 36 K-bit BRAMs, DSP, CMT
– XADC dual channel 12-bit ADC
– Up to 12 GTs with PCIe hard core
– Up to 300 Select IOs
Programmable Logic System Interfaces
– Interrupts, DMA control
– Debug
Programmable Logic AXI Interfaces
– Multiple 32/64 bit AXI interfaces to PL
– Accelerator Coherency Port (ACP) with access to caches
High Performance PL Configuration
– Security Decryption Engine
– Under 200 ms configuration time from flash
– Debugging interfaces
Zynq -7010 EPP
Fig 3:Internal view of processing system
Fig 4:Internal view of programmable logic
Zynq-7010 epp
9. CUSTOMIZING ZYNQ
(Tools for the Programmable Logic System Builder)
Clocking
– Flexible clock sources (PS or PL)
– Simple clock interfaces
Memory and Peripheral access
– PL access to all memory: Caches, OCM, DDR
– 2 dedicated DDR ports ensure bandwidth
– PL access to all peripherals in PS
Debug and Misc
– Bidirectional cross-triggers (Coresight and Chipscope)
– 16 general purpose interrupts from PL to PS
ADVANTAGES:
• The Zynq-7010 integrates the software programmability of an ARM-based processor
with the hardware programmability of an FPGA, enabling key analytics and hardware
acceleration while integrating CPU, DSP, ASSP, and mixed signal functionality on a
single device.
• Consisting of dual-core the Zynq-7010 is the best price to performance-per-watt, fully
scalable SoC platform for your unique application requirements.
APPLICATIONS:
There are many applications of Zynq -7010.Some of them are as follows:
• Z-Turn board,a low-cost linux-ready Single Board Computer
• Automotive driver assistance, driver information, and infotainment
• Medical Endoscope
• Small Cell Baseband
• Professional Cameras ,Broadcast Cameras
• Industrial motor control, industrial networking, and Machine Vision
• Carrier Ethernet Backhaul
• Multi-function Printers
• Driver resistance
• IP and Smart camera
• LTE radio and baseband
• Factory automation
• Video and night vision equipment
• Medical diagnostics, imaging and networking
Fig 5:Clock Interfaces