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1. Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Input Vector Monitoring Concurrent BIST
Architecture Using SRAM Cells
Abstract—Input vector monitoring concurrent built-in self test (BIST) schemes
perform testing during the normal operation of the circuit without imposing a need
to set the circuit offline to perform the test. These schemes are evaluated based on
the hardware overhead and the concurrent test latency (CTL), i.e., the time
required for the test to complete, whereas the circuit operates normally. In this
brief, we present a novel input vector monitoring concurrent BIST scheme, which
is based on the idea of monitoring a set (called window) of vectors reaching the
circuit inputs during normal operation, and the use of a static-RAMlike structure to
store the relative locations of the vectors that reach the circuit inputs in the
examined window; the proposed scheme is shown to perform significantly better
than previously proposed schemes with respect to the hardware overhead and CTL
tradeoff.

2. SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com