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The LEGaTO project has received funding from the European Union’s Horizon 2020
research and innovation programme under the grant agreement No 780681. www.legato-project.eu
The LEGaTO Software Toolchain
Low Energy Toolset for Heterogeneous
Computing
LEGaTO Project Goals
OmpSs-centric 
Programming Model
Nanos + XiTAO based
runtime targeting
heterogeneous clusters
+
One order of magnitude
improvement in energy-
efficiency for heterogeneous
hardware through the use of
the energy-optimized
programming model and
runtime.
5× decrease in
Mean Time to
Failure through
energy-efficient
software-based
fault tolerance.
Size reduction
of the trusted
computing base
by at least an
order of
magnitude.
5× increase in FPGA
designer productivity
through the design of
novel features for
hardware design using
dataflow languages.
from task-groups to
to dataflow blocks
MULTI
CORE
LEGaTO
HARDWARE
PLATFORM
kernel
identification
OmpSs + Annotations
for Locality, Security,
Fault Tolerance
GPU FPGA
INTERCONNECT
FAULT TOLERANT + SECURE + LOCALITY-AWARE
ADAPTIVE SCHEDULING
LEGaTO APPLICATION
DFiant
HDL
LEGaTO
RUNTIME
PLATFORM
LEGaTO
PROGRAMMING
MODEL
CUDA
kernels
MAXJ
External
kernels
Source Code
XiTAO
OmpSs
Master
FPGA
Bitstream
XiTAO
Nanos
CUDA
XiTAO
autoVivado
offload
PERFORMANCE MONITORING

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ACACES 2019

  • 1. The LEGaTO project has received funding from the European Union’s Horizon 2020 research and innovation programme under the grant agreement No 780681. www.legato-project.eu The LEGaTO Software Toolchain Low Energy Toolset for Heterogeneous Computing LEGaTO Project Goals OmpSs-centric  Programming Model Nanos + XiTAO based runtime targeting heterogeneous clusters + One order of magnitude improvement in energy- efficiency for heterogeneous hardware through the use of the energy-optimized programming model and runtime. 5× decrease in Mean Time to Failure through energy-efficient software-based fault tolerance. Size reduction of the trusted computing base by at least an order of magnitude. 5× increase in FPGA designer productivity through the design of novel features for hardware design using dataflow languages. from task-groups to to dataflow blocks MULTI CORE LEGaTO HARDWARE PLATFORM kernel identification OmpSs + Annotations for Locality, Security, Fault Tolerance GPU FPGA INTERCONNECT FAULT TOLERANT + SECURE + LOCALITY-AWARE ADAPTIVE SCHEDULING LEGaTO APPLICATION DFiant HDL LEGaTO RUNTIME PLATFORM LEGaTO PROGRAMMING MODEL CUDA kernels MAXJ External kernels Source Code XiTAO OmpSs Master FPGA Bitstream XiTAO Nanos CUDA XiTAO autoVivado offload PERFORMANCE MONITORING