Machine Purpose

1-1 Chapter 1—The General Purpose Machine Chapter 1: The General Purpose Machine Topics 1.1 The General Purpose Machine 1.2 The User’s View 1.3 The Machine/Assembly Language Programmer’s View 1.4 The Computer Architect’s View 1.5 The Computer System Logic Designer’s View 1.6 Historical Perspective 1.7 Trends and Research 1.8 Approach of the TextComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-2 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 2 Explores the nature of machines and machine languages • Relationship of machines and languages • Generic 32-bit Simple RISC Computer—SRC • Register transfer notation—RTN • The main function of the CPU is the Register Transfer • RTN provides a formal specification of machine structure and function • Maps directly to hardware • RTN and SRC will be used for examples in subsequent chapters • Provides a general discussion of addressing modes • Presents a view of logic design aimed at implementing registers and register transfersComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-3 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 3 • Treats 2 real machines of different types—CISC and RISC—in some depth • Discusses general machine characteristics and performance • Differences in design philosophies of • CISC (Complex Instruction Set Computer) and • RISC (Reduced Instruction Set Computer) architectures • CISC machine—Motorola MC68000 • Applies RTN to the description of real machines • RISC machine—SPARCComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-4 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 4 This keystone chapter describes processor design at the logic gate level • Describes the connection between the instruction set and the hardware • Develops alternative 1-, 2-, and 3-bus designs of SRC at the gate level • RTN provides description of structure and function at low and high levels • Shows how to design the control unit that makes it all run • Describes two additional machine features: • implementation of exceptions (interrupts) • machine reset capabilityComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-5 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 5 Important advanced topics in CPU design • General discussion of pipelining—having more than one instruction executing simultaneously • requirements on the instruction set • how instruction classes influence design • pipeline hazards: detection & management • Design of a pipelined version of SRC • Instruction-level parallelism—issuing more than one instruction simultaneously • Superscalar and VLIW designs • Microcoding as a way to implement controlComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-6 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 6 The arithmetic and logic unit: ALU • Impact on system performance • Digital number systems and arithmetic in an arbitrary radix • number systems and radix conversion • integer add, subtract, multiply, and divide • Time/space trade-offs: fast parallel arithmetic • Floating point representations and operations • Branching and the ALU • Logic operations • ALU hardware designComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-7 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 7 The memory subsystem of the computer • Structure of 1-bit RAM and ROM cells • RAM chips, boards, and modules • Concept of a memory hierarchy • nature of different levels • interaction of adjacent levels • Virtual memory • Cache design: matching cache & main memory • Memory as a complete systemComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-8 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 8 Computer input and output: I/O • Kinds of system buses, signals and timing • Serial and parallel interfaces • Interrupts and the I/O system • Direct memory access—DMA • DMA, interrupts, and the I/O system • The hardware/software interface: device driversComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-9 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 9 Structure, function, and performance of peripheral devices • Disk drives • Organization • Static and dynamic properties • Video display terminals • Memory-mapped video • Printers • Mouse and keyboard • Interfacing to the analog worldComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-10 Chapter 1—The General Purpose Machine Looking Ahead—Chapter 10 Computer communications, networking, and the Internet • Communications protocols; layered networks • The OSI layer model • Point to point communication: RS-232 and ASCII • Local area networks—LANs • Example: Ethernet • Internetworking and the Internet • TCP/IP protocol stack • Packet routing and routers • IP addresses: assignment and use • Nets and subnets: subnet masks • Internet applications and futuresComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-11 Chapter 1—The General Purpose Machine Chapter 1—A Perspective • Alan Turing showed that an abstract computer, a Turing machine, can compute any function that is computable by any means • A general purpose computer with enough memory is equivalent to a Turing machine • Over 50 years, computers have evolved • from memory size of 1 kiloword (1024 words) clock periods of 1 millisecond (0.001 s) • to memory size of a terabyte (240 bytes) and clock periods of 1 ns (10-9 s) • More speed and capacity is needed for many applications, such as real-time 3D animationComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-12 Chapter 1—The General Purpose Machine Scales, Units, and Conventions Term Normal Usage As a power of 2 K (kilo-) 103 210 = 1,024 M (mega-) 106 220 = 1,048,576 G (giga-) 109 230 = 1,073,741,824 T (tera-) 1012 240 = 1,099,511,627,776 Term Usage Note the m (milli-) 10-3 differences µ (micro-) 10-6 between usages. n (nano-) You should commit 10-9 the powers of 2 and p (pico-) 10-12 10 to memory. Units: Bit (b), Byte (B), Nibble, Word (w), Double Word, Long Word, Second (s), Hertz (Hz)Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-13 Chapter 1—The General Purpose Machine Fig 1.1 The User’s View of a Computer 1.10 Looking Ahead comes from viewing The intellectual synthesis that the three perspectives a computer system from each design. It , effective computer leads to an efficient e functions tand how a machin is when you unders hitecture level and the system arc at the gate, ISA, chine . Whether derstand the ma that you fully un ience, is in Computer Sc yo ur career objective aspect of gineering, or some other Computer En this book st hope that is our sincere nding. computers it that understa u by providing will serve yo The user sees software, speed, storage capacity, and peripheral device functionality.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-14 Chapter 1—The General Purpose Machine Machine/Assembly Language Programmer’s View • Machine language: • Set of fundamental instructions the machine can execute • Expressed as a pattern of 1’s and 0’s • Assembly language: • Alphanumeric equivalent of machine language • Mnemonics more human-oriented than 1’s and 0’s • Assembler: • Computer program that transliterates (one-to-one mapping) assembly to machine language • Computer’s native language is machine/assembly language • “Programmer,” as used in this course, means machine/ assembly language programmerComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-15 Chapter 1—The General Purpose Machine Machine and Assembly Language• The assembler converts assembly language to machine language. You must also know how to do this. Op code Data reg. #5 Data reg. #4 MC68000 Assembly Language Machine Language MOVE.W D4, D5 0011 101 000 000 100 ADDI.W #9, D2 0000 000 010 111 100 0000 0000 0000 1001 Tbl 1.2 Two Motorola MC68000 InstructionsComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-16 Chapter 1—The General Purpose Machine The Stored Program Concept The stored program concept says that the program is stored with data in the computer’s memory. The computer is able to manipulate it as data—for example, to load it from disk, move it in memory, and store it back on disk. • It is the basic operating principle for every computer. • It is so common that it is taken for granted. • Without it, every instruction would have to be initiated manually.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-17 Chapter 1—The General Purpose Machine Fig 1.2 The Fetch-Execute Process MC68000 CPU Main memory 31 0 0 Various CPU registers 0011 101 000 000 100 4000 15 0 PC 4000 15 0 IR 0011 101 000 000 100 231 – 1 15 0 Control signals The control unitComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-18 Chapter 1—The General Purpose Machine Programmer’s Model: Instruction Set Architecture (ISA) • Instruction set: the collection of all machine operations. • Programmer sees set of instructions, along with the machine resources manipulated by them. • ISA includes • Instruction set, • Memory, and • Programmer-accessible registers of the system. • There may be temporary or scratch-pad memory used to implement some function is not part of ISA. • Not Programmer Accessible.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-19 Chapter 1—The General Purpose Machine Fig 1.3 Programmer’s Models of 4 Commercial Machines M6800 I8086 VAX11 PPC601 (introduced 1975) (introduced 1979) (introduced 1981) (introduced 1993) 7 0 15 87 0 31 0 0 63 A AX R0 0 32 15 B Data BX 12 general 64-bit registers purpose floating point 6 special IX CX R11 registers registers purpose SP DX AP 31 registers PC FP 0 31 SP Status Address SP 0 and BP 32 32-bit PC general count SI registers purpose DI registers PSW 31 CS Memory 0 31 0 segment DS 232 bytes 0 216 bytes of main registers SS of main More than 50 memory ES memory 32-bit special capacity capacity purpose 216 – 1 232 – 1 registers IP Status More than 300 Fewer instructions than 100 instructions 0 252 bytes 0 220 bytes of main of main memory memory capacity capacity 220 – 1 252 – 1 More than 120 More than 250 instructions instructionsComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-20 Chapter 1—The General Purpose Machine Machine, Processor, and Memory State • The Machine State: contents of all registers in system, accessible to programmer or not • The Processor State: registers internal to the CPU • The Memory State: contents of registers in the memory system • “State” is used in the formal finite state machine sense • Maintaining or restoring the machine and processor state is important to many operations, especially procedure calls and interruptsComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-21 Chapter 1—The General Purpose Machine Data Type: HLL Versus Machine Language • HLLs provide type checking • Verifies proper use of variables at compile time • Allows compiler to determine memory requirements • Helps detect bad programming practices • Most machines have no type checking • The machine sees only strings of bits • Instructions interpret the strings as a type: usually limited to signed or unsigned integers and FP numbers • A given 32-bit word might be an instruction, an integer, a FP number, or 4 ASCII charactersComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-22 Chapter 1—The General Purpose Machine Tbl 1.3 Instruction Classes Inst ruct ion Class C VAX Assembly Language Dat a Movement a = b MOV b, a b = c + d*e MPY d, e, b Arit hmet ic/ logic ADD c, b, b Cont rol flow goto LBL BR LBL • This compiler: • Maps C integers to 32-bit VAX integers • Maps C assign, *, and + to VAX MOV, MPY, and ADD • Maps C goto to VAX BR instruction • The compiler writer must develop this mapping for each language-machine pairComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-23 Chapter 1—The General Purpose Machine Tools of the Assembly Language Programmer’s Trade • The assembler • The linker • The debugger or monitor • The development systemComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-24 Chapter 1—The General Purpose Machine Who Uses Assembly Language • The machine designer • Must implement and trade off instruction functionality • The compiler writer • Must generate machine language from a HLL • The writer of time or space critical code • Performance goals may force program-specific optimizations of the assembly language • Special purpose or imbedded processor programmers • Special functions and heavy dependence on unique I/O devices can make HLLs uselessComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-25 Chapter 1—The General Purpose Machine The Computer Architect’s View • Architect is concerned with design & performance • Designs the ISA for optimum programming utility and optimum performance of implementation • Designs the hardware for best implementation of the instructions • Uses performance measurement tools, such as benchmark programs, to see that goals are met • Balances performance of building blocks such as CPU, memory, I/O devices, and interconnections • Meets performance goals at lowest costComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-26 Chapter 1—The General Purpose Machine Buses as Multiplexers • Interconnections are very important to computer • Most connections are shared • A bus is a time-shared connection or multiplexer • A bus provides a data path and control • Buses may be serial, parallel, or a combination • Serial buses transmit one bit at a time • Parallel buses transmit many bits simultaneously on many wiresComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-27 Chapter 1—The General Purpose Machine Fig 1.4 Simple One- and Two-Bus Architectures Memory Memory Memory bus CPU CPU I/O bus Input/ Input/ output output subsystem subsystem n n-bit system bus Input/output Input/output devices devices (a) One bus (b) Two busesComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-28 Chapter 1—The General Purpose Machine Fig 1.5 The Apple Quadra 950 Bus System (Simplified) LocalTalk LocalTalk bus Printers, other interface computers ADB ADB bus Keyboard, transceiver mouse, bit pads System SCSI SCSI bus Disk drives, bus interface CD ROM drives NuBus NuBus Video and special interface purpose cards CPU Ethernet Ethernet Other computers transceiver MemoryComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-29 Chapter 1—The General Purpose Machine Fig 1.6 The Memory Hierarchy • Modern computers have a hierarchy of memories • Allows tradeoffs of speed/cost/volatility/size, etc. • CPU sees common view of levels of the hierarchy. CPU Cache Tape Memory Main Memory Disk Memory MemoryComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-30 Chapter 1—The General Purpose Machine Tools of the Architect’s Trade • Software models, simulators and emulators • Performance benchmark programs • Specialized measurement programs • Data flow and bottleneck analysis • Subsystem balance analysis • Parts, manufacturing, and testing cost analysisComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-31 Chapter 1—The General Purpose Machine Logic Designer’s View • Designs the machine at the logic gate level • The design determines whether the architect meets cost and performance goals • Architect and logic designer may be a single person or teamComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-32 Chapter 1—The General Purpose Machine Implementation Domains An implementation domain is the collection of devices, logic levels, etc. which the designer uses. Possible implementation domains: • VLSI on silicon • TTL or ECL chips • Gallium arsenide chips • PLAs or sea-of-gates arrays • Fluidic logic or optical switchesComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-33 Chapter 1—The General Purpose Machine Fig 1.7 Three Implementation Domains for the 2-1 Multiplexer • 2-1 multiplexer in three different implementation domains • Generic logic gates (abstract domain) • National Semiconductor FAST Advanced Schottky TTL (VLSI on Si) • Fiber optic directional coupler switch (optical signals in LiNbO3) U6 15 /G S1 /A/B 2 1A 3 1Y 4 1B 5 2A 6 2Y 7 S 2B I0 O 11 3A I1 I0 10 3Y 9 O 3B I0 14 4A 4Y 12 O S I1 I1 13 4B 74F257N (a) Abstract view of (b) TTL implementation (c) Optical switch Boolean logic domain implementationComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-34 Chapter 1—The General Purpose Machine The Distinction Between Classical Logic Design and Computer Logic Design • The entire computer is too complex for traditional FSM design techniques • FSM techniques can be used “in the small” • There is a natural separation between data and control • Data path: storage cells, arithmetic, and their connections • Control path: logic that manages data path information flow • Well defined logic blocks are used repeatedly • Multiplexers, decoders, adders, etc.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-35 Chapter 1—The General Purpose Machine Two Views of the CPU PC Register 31 0 Programmer: PC 32 32 B Bus D Q A Bus PC Logic Designer PCout (Fig 1.8): CK PCinComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-36 Chapter 1—The General Purpose Machine Tools of the Logic Designer’s Trade • Computer-aided design tools • Logic design and simulation packages • Printed circuit layout tools • IC (integrated circuit) design and layout tools • Logic analyzers and oscilloscopes • Hardware development systemComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-37 Chapter 1—The General Purpose Machine Historical Generations • 1st Generation: 1946–59, vacuum tubes, relays, mercury delay lines • 2nd generation: 1959–64, discrete transistors and magnetic cores • 3rd generation: 1964–75, small- and medium-scale integrated circuits • 4th generation: 1975–present, single-chip microcomputer • Integration scale: components per chip • Small: 10–100 • Medium: 100–1,000 • Large: 1000–10,000 • Very large: greater than 10,000Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

1-38 Chapter 1—The General Purpose Machine Chapter 1 Summary • Three different views of machine structure and function • Machine/assembly language view: registers, memory cells, instructions • PC, IR • Fetch-execute cycle • Programs can be manipulated as data • No, or almost no, data typing at machine level • Architect views the entire system • Concerned with price/performance, system balance • Logic designer sees system as collection of functional logic blocks • Must consider implementation domain • Tradeoffs: speed, power, gate fan-in, fan-outComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-1 Chapter 2—Machines, Machine Languages, and Digital Logic Chapter 2: Machines, Machine Languages, and Digital Logic Topics 2.1 Classification of Computers and Their Instructions 2.2 Computer Instruction Sets 2.3 Informal Description of the Simple RISC Computer, SRC 2.4 Formal Description of SRC Using Register Transfer Notation, RTN 2.5 Describing Addressing Modes with RTN 2.6 Register Transfers and Logic Circuits: From Behavior to HardwareComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-2 Chapter 2—Machines, Machine Languages, and Digital Logic What Are the Components of an ISA?• Sometimes known as The Programmer’s Model of the machine• Storage cells • General and special purpose registers in the CPU • Many general purpose cells of same size in memory • Storage associated with I/O devices• The machine instruction set • The instruction set is the entire repertoire of machine operations • Makes use of storage cells, formats, and results of the fetch/ execute cycle • i.e., register transfers• The instruction format • Size and meaning of fields within the instruction• The nature of the fetch-execute cycle • Things that are done before the operation code is knownComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-3 Chapter 2—Machines, Machine Languages, and Digital Logic Fig. 2.1 Programmer’s Models of Various Machines We saw in Chap. 1 a variation in number and type of storage cells M6800 I8086 VAX11 PPC601 (introduced 1975) (introduced 1979) (introduced 1981) (introduced 1993) 7 0 15 87 0 31 0 0 63 A AX R0 0 32 15 B Data BX 12 general 64-bit registers purpose floating point 6 special IX CX R11 registers registers purpose SP DX AP 31 registers PC FP 0 31 SP Status Address SP 0 and BP 32 32-bit PC general count SI registers purpose DI registers PSW 31 CS Memory 0 31 0 segment DS 232 bytes 0 216 bytes of main registers SS of main More than 50 memory ES memory 32-bit special capacity capacity purpose 216 –1 232 – 1 registers IP Status More than 300 Fewer instructions than 100 instructions 0 252 bytes 0 220 bytes of main of main memory memory capacity capacity 220 – 1 252 – 1 More than 120 More than 250 instructions instructionsComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-4 Chapter 2—Machines, Machine Languages, and Digital Logic What Must an Instruction Specify? Data Flow• Which operation to perform add r0, r1, r3 • Ans: Op code: add, load, branch, etc.• Where to find the operand or operands add r0, r1, r3 • In CPU registers, memory cells, I/O locations, or part of instruction• Place to store result add r0, r1, r3 • Again CPU register or memory cell• Location of next instruction add r0, r1, r3 br endloop • Almost always memory cell pointed to by program counter—PC• Sometimes there is no operand, or no result, or no next instruction. Can you think of examples?Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-5 Chapter 2—Machines, Machine Languages, and Digital Logic Instructions Can Be Divided into 3 Classes • Data movement instructions • Move data from a memory location or register to another memory location or register without changing its form • Load—source is memory and destination is register • Store—source is register and destination is memory • Arithmetic and logic (ALU) instructions • Change the form of one or more operands to produce a result stored in another location • Add, Sub, Shift, etc. • Branch instructions (control flow instructions) • Alter the normal flow of control from executing the next instruction in sequence • Br Loc, Brz Loc2,—unconditional or conditional branchesComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-6 Chapter 2—Machines, Machine Languages, and Digital Logic Tbl 2.1 Examples of Data Movement InstructionsInstruction Meaning MachineMOV A, B Move 16 bits from memory location A to VAX11 Location BLDA A, Addr Load accumulator A with the byte at memory M6800 location Addrlwz R3, A Move 32-bit data from memory location A to PPC601 register R3li $3, 455 Load the 32-bit integer 455 into register $3 MIPS R3000mov R4, dout Move 16-bit data from R4 to output port dout DEC PDP11IN, AL, KBD Load a byte from in port KBD to accumulator Intel PentiumLEA.L (A0), A2 Load the address pointed to by A0 into A2 M6800 • Lots of variation, even with one instruction typeComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-7 Chapter 2—Machines, Machine Languages, and Digital Logic Tbl 2.2 Examples of ALU InstructionsInstruction Meaning MachineMULF A, B, C multiply the 32-bit floating point values at VAX11 mem loc’ns. A and B, store at Cnabs r3, r1 Store abs value of r1 in r3 PPC601ori $2, $1, 255 Store logical OR of reg $ 1 with 255 into reg $2 MIPS R3000DEC R2 Decrement the 16-bit value stored in reg R2 DEC PDP11SHL AX, 4 Shift the 16-bit value in reg AX left by 4 bit pos’ns. Intel 8086 • Notice again the complete dissimilarity of both syntax and semantics. Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-8 Chapter 2—Machines, Machine Languages, and Digital Logic Tbl 2.3 Examples of Branch InstructionsInstruction Meaning MachineBLSS A, Tgt Branch to address Tgt if the least significant VAX11 bit of mem loc’n. A is set (i.e. = 1)bun r2 Branch to location in R2 if result of previous PPC601 floating point computation was Not a Number (NAN)beq $2, $1, 32 Branch to location (PC + 4 + 32) if contents MIPS R3000 of $1 and $2 are equalSOB R4, Loop Decrement R4 and branch to Loop if R4 ≠ 0 DEC PDP11JCXZ Addr Jump to Addr if contents of register CX ≠ 0. Intel 8086 Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-9 Chapter 2—Machines, Machine Languages, and Digital Logic CPU Registers Associated with Flow of Control—Branch Instructions • Program counter usually locates next instruction • Condition codes may control branch • Branch targets may be separate registers Processor State C N V Z Program Counter Condition Codes • • • Branch TargetsComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-10 Chapter 2—Machines, Machine Languages, and Digital Logic HLL Conditionals Implemented by Control Flow Change • Conditions are computed by arithmetic instructions • Program counter is changed to execute only instructions associated with true conditions C language Assembly language CMP.W #5, NUM ;the comparisonif NUM==5 then SET=7 BNE L1 ;conditional branch MOV.W #7, SET ;action if true L1 ... ;action if falseComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-11 Chapter 2—Machines, Machine Languages, and Digital Logic CPU Registers May Have a “Personality” • Architecture classes are often based on how where the operands and result are located and how they are specified by the instruction. • They can be in CPU registers or main memory: Stack Arithmetic Address General Purpose Registers Registers Registers Push Pop Top Second • • • • • • • • • • • • Stack Machine Accumulat or Machine General Regist er MachineComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-12 Chapter 2—Machines, Machine Languages, and Digital Logic 3-, 2-, 1-, & 0-Address ISAs • The classification is based on arithmetic instructions that have two operands and one result • The key issue is “how many of these are specified by memory addresses, as opposed to being specified implicitly” • A 3-address instruction specifies memory addresses for both operands and the result R ← Op1 op Op2 • A 2-address instruction overwrites one operand in memory with the result Op2 ← Op1 op Op2 • A 1-address instruction has a processor, called the accumulator register, to hold one operand & the result (no addr. needed) Acc ← Acc op Op1 • A 0-address + uses a CPU register stack to hold both operands and the result TOS ← TOS op SOS (where TOS is Top Of Stack, SOS is Second On Stack) • The 4-address instruction, hardly ever seen, also allows the address of the next instruction to specified explicitlyComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-13 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.2 The 4-Address Machine and Instruction Format Memory CPU add, Res, Op1, Op2, Nexti (Res ← Op1 + Op2) Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res NextiAddr: Nexti Instruction format Bits: 8 24 24 24 24 add ResAddr Op1Addr Op2Addr NextiAddr Which Where to Where to find operation put result Where to find operands next instruction• Explicit addresses for operands, result, & next instruction• Example assumes 24-bit addresses • Discuss: size of instruction in bytesComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-14 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.3 The 3-Address Machine and Instruction Format Memory CPU add, Res, Op1, Op2 (Res ← Op2 + Op1) Op1Addr: Op1 Op2Addr: Op2 ResAddr: Res Program NextiAddr: Nexti 24 counter Where to find next instruction Instruction format Bits: 8 24 24 24 add ResAddr Op1Addr Op2Addr Which Where to operation put result Where to find operands • Address of next instruction kept in processor state register— the PC (except for explicit branches/jumps) • Rest of addresses in instruction • Discuss: savings in instruction word sizeComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-15 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.4 The 2-Address Machine and Instruction Format Memory CPU add Op2, Op1 (Op2 ← Op2 + Op1) Op1Addr: Op1 Op2Addr: Op2,Res Program NextiAddr: Nexti counter 24 Where to find next instruction Instruction format Bits: 8 24 24 add Op2Addr Op1Addr Which Where to find operands operation Where to put result • Result overwrites Operand 2 • Needs only 2 addresses in instruction but less choice in placing dataComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-16 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.5 1-Address Machine and Instruction Format Memory CPU add Op1 (Acc ← Acc + Op1) Op1Addr: Op1 Where to find operand2, and where to put result Accumulator Program NextiAddr: Nexti counter 24 Where to find next instruction Need instructions to load Instruction format and store operands: Bits: 8 24 LDA OpAddr add Op1Addr STA OpAddr Which Where to find• Special CPU register, the accumulator, operation operand1 supplies 1 operand and stores result• One memory address used for other operandComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-17 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.6 The 0-Address, or Stack, Machine and Instruction Format Instruction formats Memory CPU push Op1 (TOS ← Op1) Bits: 8 24 Op1Addr: Op1 Format push Op1Addr TOS Operation Result SOS etc. add (TOS ← TOS + SOS) Bits: 8 Stack Program Format add NextiAddr: Nexti 24 counter Which operation Where to find Where to find operands, next instruction and where to put result (on the stack)• Uses a push-down stack in CPU• Arithmetic uses stack for both operands and the result• Computer must have a 1-address instruction to push and pop operands to and from the stackComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-18 Chapter 2—Machines, Machine Languages, and Digital Logic Example 2.1 Expression Evaluation for 3-, 2-, 1-, and 0-Address Machines Evaluat e a = (b+c)*d - e 3 - ad d r e s s 2 - ad d r e s s 1 - ad d r e ss St ac k add a, b, c load a, b load b push b mpy a, a, d add a, c add c push c sub a, a, e mpy a, d mpy d add sub a, e sub e push d store a mpy push e sub pop a • Number of instructions & number of addresses both vary • Discuss as examples: size of code in each caseComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-19 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.7 General Register Machine and Instruction Formats CPU Registers Instruction formats Memory load load R8, Op1 (R8 ← Op1) Op1Addr: Op1 R8 load R8 Op1Addr R6 R4 add R2, R4, R6 (R2 ← R4 + R6) add R2 R4 R6 R2 Nexti Program counter• It is the most common choice in today’s general-purpose computers• Which register is specified by small “address” (3 to 6 bits for 8 to 64 registers)• Load and store have one long & one short address: 1-1/2 addresses• Arithmetic instruction has 3 “half” addressesComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-20 Chapter 2—Machines, Machine Languages, and Digital Logic Real Machines Are Not So Simple • Most real machines have a mixture of 3, 2, 1, 0, and 1-1/2 address instructions • A distinction can be made on whether arithmetic instructions use data from memory • If ALU instructions only use registers for operands and result, machine type is load-store • Only load and store instructions reference memory • Other machines have a mix of register-memory and memory-memory instructionsComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-21 Chapter 2—Machines, Machine Languages, and Digital Logic Addressing Modes • An addressing mode is hardware support for a useful way of determining a memory address • Different addressing modes solve different HLL problems • Some addresses may be known at compile time, e.g., global variables • Others may not be known until run time, e.g., pointers • Addresses may have to be computed. Examples include: • Record (struct) components: • variable base (full address) + constant (small) • Array components: • constant base (full address) + index variable (small) • Possible to store constant values w/o using another memory cell by storing them with or adjacent to the instruction itselfComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-22 Chapter 2—Machines, Machine Languages, and Digital Logic HLL Examples of Structured Addresses• C language: rec → count Count • rec is a pointer to a record: full address variable • count is a field name: fixed byte offset, say 24 Rec →• C language: v[i] • v is fixed base address of array: full address constant V[i] • i is name of variable index: no larger than array size V→• Variables must be contained in registers or memory cells• Small constants can be contained in the instruction• Result: need for “address arithmetic.” • E.g., Address of Rec → Count is address of Rec + offset of count.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-23 Chapter 2—Machines, Machine Languages, and Digital Logic Fig 2.8 Common Addressing Modes a) Immediate Addressing b) Direct Addressing (Instruction contains the operand.) (Instruction contains Memory address of operand) Instr Opn 3 Instr Opn Addr of A LOAD #3, .... Operand LOAD A, ... c) Indirect Addressing d) Register Indirect Addressing (Instruction contains Memory (register contains address of operand) address of address of operand) Memory Operand Instr Opn R2 . . . Instr Opn Operand Addr R2 Operand Addr. LOAD (A), ... Operand LOAD [R2], ... Address of address of A e) Displacement (Based) (Indexed) Addressing f) Relative Addressing (address of operand = register +constant) (Address of operand = PC+constant) Memory Memory Instr Opn R2 4 Instr Opn 4 + + Operand Operand R2 PC LOAD 4[R2], ... Operand Addr. LOADRel 4[PC], ... Operand Addr.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-24 Chapter 2—Machines, Machine Languages, and Digital Logic Example: Computer, SRC Simple RISC Computer • 32 general purpose registers of 32 bits • 32-bit program counter, PC, and instruction register, IR • 232 bytes of memory address space The SRC CPU Main memory 31 0 7 0 R0 32 32-bit 0 general 32 2 purpose bytes registers of R31 main R[7] means contents memory of register 7 PC M[32] means contents IR 232 – 1 of memory location 32Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-25 Chapter 2—Machines, Machine Languages, and Digital Logic SRC Characteristics • Load-store design: only way to access memory is through load and store instructions • Only a few addressing modes are supported • ALU instructions are 3-register type • Branch instructions can branch unconditionally or conditionally on whether the value in a specified register is = 0, <> 0, >= 0, or < 0 • Branch and link instructions are similar, but leave the value of current PC in any register, useful for subroutine return • All instructions are 32 bits (1 word) longComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-26 Chapter 2—Machines, Machine Languages, and Digital Logic SRC Basic Instruction Formats • There are three basic instruction format types • The number of register specifier fields and length of the constant field vary • Other formats result from unused fields or parts • Details of formats on next slide 31 27 26 22 21 0 op ra c1 Type 1 31 27 26 22 21 17 16 0 op ra rb c2 Type 2 31 27 26 22 21 17 16 12 11 0 op ra rb rc c3 Type 3Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-27 Chapter 2—Machines, Machine Languages, and Digital Logic Instruction formats Example Fig 2.9 1. Id, st, la, 31 27 26 22 21 17 16 0 Id r3, A (R[3] = M[A]) Id r3, 4(r5) (R[3] = M[R[5] + 4]) (Partial) addi, andi, ori Op ra rb c2 addi r2, r4, #1 (R[2] = R[4] +1) Total of 7 31 2726 22 21 0 Idr r5, 8 (R[5] = M[PC + 8]) Detailed 2. Idr, str, lar Op ra c1 Iar r6, 45 (R[6] = PC + 45) Formats 31 27 26 22 21 17 16 0 3. neg, not Op ra rc unused neg r7, r9 (R[7] = – R[9]) unused 31 27 26 22 21 17 16 12 11 2 0 brzr r4, r0 4. br Op rb rc (c3) unused Cond (branch to R[4] if R[0] == 0) unused 31 27 26 22 21 17 16 12 11 2 0 brlnz r6, r4, r0 5. brl Op ra rb rc (c3) unused Cond (R[6] = PC; branch to R[4] if R[0] ≠ 0) 31 27 26 22 21 17 16 12 11 0 6. add, sub, Op ra rb rc unused add r0, r2, r4 (R[0] = R[2] + R[4]) and, or 31 27 26 22 21 17 4 2 0 shr r0, r1, #4 7a Op ra rb (c3) unused Count (R[0] = R[1] shifted right by 4 bits 7. shr, shra shl, shic 31 27 26 22 21 17 16 12 4 0 shl r2, r4, r6 7b Op ra rb rc (c3) unused 00000 (R[2] = R[4] shifted left by count in R[6]) 31 27 26 0 8. nop, stop Op unused stopComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-28 Chapter 2—Machines, Machine Languages, and Digital Logic Tbl 2.4 Example SRC Load and Store Instructions • Address can be constant, constant + register, or constant + PC • Memory contents or address itself can be loaded Instruction op ra rb c1 Meaning Addressing Mode ld r1, 32 1 1 0 32 R[1] ← M[32] Direct ld r22, 24(r4) 1 22 4 24 R[22] ← M[24+R[4]] Displacement st r4, 0(r9) 3 4 9 0 M[R[9]] ← R[4] Register indirect la r7, 32 5 7 0 32 R[7] ← 32 Immediate ldr r12, -48 2 12 – -48 R[12] ← M[PC -48] Relative lar r3, 0 6 3 – 0 R[3] ← PC Register (!) (note use of la to load a constant)Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-29 Chapter 2—Machines, Machine Languages, and Digital Logic Assembly Language Forms of Arithmetic and Logic Instructions Format Example Meaning neg ra, rc neg r1, r2 ;Negate (r1 = -r2) not ra, rc not r2, r3 ;Not (r2 = r3´ ) add ra, rb, rc add r2, r3, r4 ;2’s complement addition sub ra, rb, rc ;2’s complement subtraction and ra, rb, rc ;Logical and or ra, rb, rc ;Logical or addi ra, rb, c2 addi r1, r3, #1 ;Immediate 2’s complement add andi ra, rb, c2 ;Immediate logical and ori ra, rb, c2 ;Immediate logical or• Immediate subtract not needed since constant in addi may be negativeComputer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-30 Chapter 2—Machines, Machine Languages, and Digital Logic Branch Instruction Format There are actually only two branch instructions: br rb, rc, c3<2..0> ; branch to R[rb] if R[rc] meets ; the condition defined by c3<2..0> brl ra, rb, rc, c3<2..0> ; R[ra] ← PC; branch as above • It is c3<2..0>, the 3 lsbs of c3, that governs what the branch condition is: lsbs condition Assy language form Example 000 never brlnv brlnv r6 001 always br, brl br r5, brl r5 010 if rc = 0 brzr, brlzr brzr r2, r4, r5 011 if rc ≠ 0 brnz, brlnz 100 if rc ≥ 0 brpl, brlpl 101 if rc < 0 brmi, brlmi • Note that branch target address is always in register R[rb]. •It must be placed there explicitly by a previous instruction.Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-31 Chapter 2—Machines, Machine Languages, and Digital Logic Tbl 2.6 Forms and Formats of the br and brl Instructions Ass’y Example instr. Meaning op ra rb rcc3 Branch lang. 〈2..0〉 Cond’n. brlnv brlnv r6 R[6] ← PC 9 6 — — 000 never br br r4 PC ← R[4] 8 — 4 — 001 always brl brl r6,r4 R[6] ← PC; 9 6 4 — 001 always PC ← R[4] brzr brzr r5,r1 if (R[1]=0) 8 — 5 1 010 zero PC ← R[5] brlzr brlzr r7,r5,r1 R[7] ← PC; 9 7 5 1 010 zero brnz brnz r1, r0 if (R[0]≠0) PC← R[1] 8 — 1 0 011 nonzero brlnz brlnz r2,r1,r0 R[2] ← PC; 9 2 1 0 011 nonzero if (R[0]≠0) PC← R[1] brpl brpl r3, r2 if (R[2]≥0) PC← R[3] 8 — 3 2 100 plus brlpl brlpl r4,r3,r2 R[4] ← PC; 9 4 3 2 plus if (R[2]≥0) PC← R[3] brmi brmi r0, r1 if (R[1]<0) PC← R[0] 8 — 0 1 101 minus brlmi brlmi r3,r0,r1 R[3] ← PC; 9 3 0 1 minus if (r1<0) PC← R[0]Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

2-32 Chapter 2—Machines, Machine Languages, and Digital Logic Branch Instructions—Example C: goto Label3 SRC: lar r0, Label3 ; put branch target address into tgt reg. br r0 ; and branch • • • Label3 •••Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan http://krimo666.mylivepage.com/

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