Unit 2.1. cpu

contents
• CPU Structure and function
• Arithmetic and logic unit
• Instruction formats
• Addressing modes
• Data transfer and manipulation
• Instruction types: data transfer, manipulation, arithmetic, logical, shift and
bit
• RISC and CISC
• 64-bit processor
5/10/2021 2021@ Kathford (Kiran Bagale) 2

Introduction
• The part of the computer that performs
the bulk of data-processing operations
is called the central processing unit and
is referred to as the CPU.
• The CPU is made up of three major
parts; ALU, CU and Register sets.
The register set stores intermediate
data used during the execution of the
instructions.
The arithmetic logic unit (ALU)
performs the required microoperations
for executing the instructions.
The control unit supervises the transfer
of information among the registers and
instructs the ALU as to which
operation to perform.
Fig1: Major components of CPU
Controlunit
Register set
Arithmetic Logic
unit ALU)

Processor Unit
• The processor unit consists of arithmetic unit, logic unit, a number of
registers and internal buses.
• Bus provides data path for transfer of information between register and
arithmetic logic unit.
• All registers are connected to two multiplexers (MUXA and MUXB) that
select the registers for bus A and bus B.
• Bus A and B act as the inputs for ALU.
• Registers selected by multiplexers are sent to ALU.
• Another selector (OPR) connected to ALU selects the operation for the
ALU.
• Output produced by CPU is stored in some register and the destination
register for storing the result is activated by the destination decoder
(SELD).

Fig2: Processor Unit

• For example, to perform the operation,
• R1  R2 + R3
• MUX A selector (SELA): BUS A  R2
• MUX B selector (SELB): BUS B  R3
• ALU operation selector (OPR): ALU to ADD
• Decoder destination selector (SELD): R1Out Bus
• Why do we need CPU registers?

Control unit
• Heart of CPU.
• Consists of program counter (PC), instruction register (IR), timing and
control logic.
• The control logic, two types:
i. hardwired and
ii. microprogrammed
i. Hardwired CU:
• Register decodes and a set of gates are connected to provide the logic that
determines the action required to execute various instructions.
ii. Microprogrammed CU:
• uses a control memory to store micro instructions and a sequence to determine
the order by which the instructions are read from control memory.

Control word
• Combination of all selection bits of a unit is called control word.
• There are 14 binary selection inputs in the unit, and their combined
value specifies a control word.
• Control Word for above CPU is as below:
• It consists of four fields.
• Three fields contain three bits each, and one field has five bits.
• The three bits of SELA and SELB select a register for the A and B
input of the ALU respectively.
SELA SELB SELD OPR
3 3 3 5

Control word (cont.)
• The three bits of SELD select a destination register using the decoder
and its seven load outputs.
• The five bits of OPR select one of the operations in the ALU.
• The 14-bit control word when applied to the selection inputs specify a
particular microoperation.
• Encoding of the register selection fields and ALU operations is given
below:
Example: R1  R2 - R3
This microoperation specifies R2 for A input of the ALU, R3 for the B input of
the ALU, R1 for the destination register and ALU operation to subtract A-B.
Binary control word for this microoperation statement is:

Field: SELA SELB SELD OPR
Symbol: R2 R3 R1 SUB
Control Word: 010 011 001 00101

Fig: Control Unit
Q. Differentiate between hardwired and micro-programmed control unit.

• The control unit decides what the instructions mean and directs the
necessary data to be moved from memory to ALU.
• Control unit must communicate with both ALU and main memory and
coordinates all activities of processor unit, peripheral devices and
storage devices.
• It can be characterized on the basis of design and implementation by:
• Defining basic elements of the processor
• Describing the micro-operation that processor performs
• Determining the function that the control unit must perform to cause the
micro-operations to be performed.
• Control unit must have inputs that allow determining the state of
system and outputs that allow controlling the behaviour of system.

The input to control unit are:
• Flag: Flags are needed to determine the status of processor and
outcome of previous ALU operation.
• Clock: All micro-operations are performed within each clock pulse.
This clock pulse is also called as processor cycle time or clock cycle
time.
• Instruction Register: The op-code of instruction determines which
micro-operation to perform during execution cycle.
• Control signal from control bus: The control bus portion of system
bus provides interrupt, acknowledgement signals to control unit.

The outputs from control unit are:
• Control signal within processor:
These signals causes data transfer between registers, activate ALU functions.
• Control signal to control bus:
These are signals to memory and I/O module.
All these control signals are applied directly as binary inputs to individual
logic gate.

1. CPU Structure and Function
• Processor Organization
• Things a CPU must do:
• Fetch Instructions
• InterpretInstructions
• Fetch Data
• ProcessData
• WriteData
Fig: The CPU with the System Bus

• A small amount of internal memory,
called the registers, is needed by the
CPU to full fill these requirements.
• Components of the CPU
1. Arithmetic and Logic Unit (ALU):
does the actual computation or
processing of data.
2. Control Unit (CU): controls the
movement of data and instructions into
and out of the CPU and controls the
operation of the ALU.
Fig: Internal Structure of the CPU

Register organization
• Registers are at top of the memory hierarchy. They serve two
functions:
1. User-Visible Registers - enable the machine- or assembly-language
programmer to minimize main-memory references by optimizing
use of registers.
2. Control and Status Registers - used by the control unit to control
the operation of the CPU and by privileged, OS programs to control
the execution of programs.

• User-Visible Registers
• Categories of Use
General Purpose registers - for variety of functions
Data registers - hold data
Address registers - hold address information
Segment pointers - hold base address of the segment in use
Index registers - used for indexed addressing and may be auto indexed
Stack Pointer - a dedicated register that points to top of a stack. Push, pop, and other
stack instructionsneed not contain an explicit stack operand.
Flags

Design Issues
1. Completely general-purpose registers or specialized use?
• Specialized registers save bits in instructions because their use can be implicit
• General-purpose registers are more flexible
• Trend is toward use of specialized registers
2. Number of registers provided?
• More registers require more operand specifier bits in instructions
• 8 to 32 registers appears optimum (RISC systems use hundreds, but are a completely
different approach)
3. Register Length?
• Address registers must be long enough to hold the largest address
• Data registers should be able to hold values of most data types
• Some machines allow two contiguous registers for double-length values
4. Automatic or manual save of condition codes?
• Condition restore is usually automatic upon call return
• Saving condition code registers may be automatic upon call instruction, or may be
manual

Control and Status Registers
• Essential to instruction execution
• Program Counter (PC)
• Instruction Register (IR)
• Memory Address Register (MAR) - usually connected directly to address lines of bus
• Memory Buffer Register (MBR) - usually connected directly to data lines of bus
• Program Status Word (PSW) - also essential, common fields or flags
contained
• include:
• Sign - sign bit of last arithmetic operation
• Zero - sets when result of last arithmetic operation is 0
• Carry - sets if last operation resulted in a carry out or borrow in of a high-order bit
• Equal - sets if a logical compare result is equality
• Overflow - sets when last arithmetic operation caused overflow
• Interrupt Enable/Disable - used to enable or disable interrupts
• Supervisor - indicates if privileged operations can be used

• Other optional registers
 Pointer to a block of memory containing additional status info (like
process control blocks)
 An interrupt vector
 A system stack pointer
 A page table pointer
 I/O registers
• Design issues
 Operating system support in CPU
 How to divide allocation of control information between CPU
registers and first part of main memory (usual trade-offs apply)

Fig: Example Microprocessor Register Organization

Instruction cycle
• Basic instruction cycle contains the following sub-cycles.
• Fetch - read next instruction from memory into CPU
• Execute - Interpret the opcode and perform the indicated operation
• Interrupt - if interrupts are enabled and one has occurred, save the current
process state and service the interrupt
Fig: Instruction Cycles

Fig: Instruction Cycle State Diagram

The Indirect Cycle
• Think of as another instruction sub-cycle
• May require just another fetch (based upon last fetch)
• Might also require arithmetic, like indexing
Fig: Instruction Cycle with Indirect

Data Flow
 Exact sequence dependson CPU design
 General sequence use of:
 a memory address register (MAR)
 a memory buffer register (MBR)
 a program counter(PC)
 an instructionregister (IR)
Fetch cycle data flow
 PC contains address of next instruction to be fetched
 This address is moved to MAR and placed on address bus
 Controlunit requests a memory read
 Result is
 placed on data bus
 result copied to MBR
 then moved to IR
 Meanwhile, PC is incremented

Fig: Data flow, Fetch Cycle
t1: MAR  (PC)
t2: MBR  Memory
PC  PC + 1
t3: IR(Address)  (MBR(Address))

Indirect cycle data flow
• Decodes the instruction
• After fetch, control unit examines IR to see if indirect addressing is
being used. If so:
Rightmost n bits of MBR (the memory reference) are transferred to MAR
• Control unit requests a memory read, to get the desired operand
address into the MBR.

t1: MAR  (IR(Address))
t2: MBR  Memory
t3: IR(Address)  (MBR(Address))
Fig: Data Flow, Indirect Cycle

Execute cycle data flow
• Not simple and predictable, like other cycles
• Takes many forms, since form depends on which of the various
machine instructions is in the IR.
• May involve
• transferring data among registers
• read or write from memory or I/O
• invocation of the ALU
• For example: ADD R, X
t1: MAR ←(IR(Address))
t2: MBR ← Memory
t3: R1←(R1) + (MBR)

Interrupt cycle data flow
• Current contents of PC must be saved (for resume after interrupt), so
PC is transferred to MBR to be written to memory.
• Save location’s address (such as a stack ptr) is loaded into MAR from
the control unit.
• PC is loaded with address of interrupt routine (so next instruction
cycle will begin by fetching appropriate instruction)
t1: MBR ← (PC)
t2: MAR ← save_address
PC ← Routine_address
t3: Memory ← (MBR)

Fig: Data Flow, Interrupt Cycle

2. Arithmetic and Logic Unit
• Combinational circuit.
• Performs arithmetic and logical operations on data.
• All of the other elements of computer system- control unit, registers,
memory, I/O are their mainly to bring data into the ALU for it to
process and then to take the result back out.

• Data are presented to ALU in register and the result of operation is stored
in register.
• Registers are temporary storage within the processor that are connected by signal
path to the ALU.
• The ALU may also set flags as the result of an operation.
• The flags values are also stored in registers within the processor.
• The control unit provides signals that control the operation of ALU and the movement of
data into an out of ALU.

Design of ALU
• Has 3-sections:
1. Design the arithmetic section
2. Design the logical section
3. Combine these 2 sections to form the ALU

1. Design the arithmetic section

2. Design the logical section
Fig: Block diagram of Logic Unit
• The basic componentsof logical circuit are AND, OR, XOR and NOT gate circuits
connectedaccordingly.
• It consists of four gates and a multiplexer.
• Each of four logic operations is generated through
a gate that performs the required logic.
• The two selection input S1 and S0 choose one of
the data inputs of the multiplexer and directs its
value to the output.
• Functional table lists the logic operations.

3. Combine these 2 sections to form the ALU
• n data input from A are combined with n data input from B to generate the
result of an operation at the F output line.
Fig: Block diagram of ALU

• S0,S1 two selection line to choose different ALU operation.
• Mode select line S2 differentiate between arithmetic and logical
operations.
• When S2 = 0, arithmetic operation
= 1, logical operation

3. Instruction Formats
• The computer can be used to perform a specific task, only by
specifying the necessary steps to complete the task.
• The collection of such ordered steps forms a ‘program’ of a computer.
• Ordered steps are the ‘instructions’.
• Computer instructions are stored in central memory locations and are
executed sequentially one at a time.
• The control reads an instruction from a specific address in memory
and executes it.
• It then continues by reading the next instruction in sequence and
executes it until the completion of the program.

Opcode Address
n-1 m-1 k-1 0
AddressingMode
I
Fig: InstructionFormat
• A computer usually has a variety of Instruction Code Formats.
• An n bit instruction that has k bits of address field and m bits of operation
code field can addressed 2^K location directly and specify 2^m different
operation.
• The bits of the instruction are divided into groups called fields.
 The most common fields in instruction formats are:
 An Operation code field that specifies the operation to be performed.
 An Address field that designates a memory address or a processor register.
 A Mode field that specifies the way the operand or the effective address is determined.
• Operands residing in memory are specified by their memory address.
• Operands residing in processor register are specified with a register address.

Processor organization
• Computers may have instructions of several different lengths
containing varying number of addresses.
• The number of address fields in the instruction format of a computer
depends on the internal organization of its registers.
• Most computers fall into one of 3 types of CPU organizations:
1. Single register (Accumulator) organization
• Basic Computer is a good example
• Accumulator is the only general purpose register
• Uses implied accumulator register for all operations
e.g.
ADD X // AC  AC + M[X]
LDA Y // AC  M[Y]

2. General register organization
• Used by most modern computer processors
• Any of the registers can be used as the source or destination for computer
operations
e.g.
ADD R1, R2, R3 // R1  R2 + R3
ADD R1, R2 // R1 R1 + R2
MOV R1, R2 // R1  R2
ADD R1, X // R1  R1 + M[X]
3. Stack organization
• All operations are done with the stack
• For example, an OR instruction will pop the two top elements from the stack,
do a logical OR on them, and push the result on the stack
e.g.
PUSH X // TOS  M[X]
ADD // TOS=TOP(S)+ TOP(S)

Types of instruction
• Computers may have instructions of several different lengths
containing varying number of addresses.
• On the basis of no. of address field, we can categorize the instruction
as below:
1. Three-Address Instructions
• Program to evaluate X = (A + B) * (C + D):
ADD R1, A, B // R1  M [A] + M [B]
ADD R2, C, D // R2  M[C] + M [D]
MUL X, R1, R2 // M[X]  R1 * R2
• Merit: Results in short programs
• Demerit: Instruction becomes long (many bits)

2. Two-Address Instructions
• Program to evaluate X = (A + B) * (C + D) :
MOV R1, A // R1  M [A]
ADD R1, B // R1  R1 + M [B]
MOV R2, C // R2  M[C]
ADD R2, D // R2  R2 + M [D]
MUL R1, R2 // R1  R1 * R2
MOV X, R1 // M[X]  R1
• Merit: Tries to minimize the size of instruction
• Demerit: Size of program is relative larger.

3. One-Address Instructions
• Use an implied AC register for all data manipulation
Program to evaluate X = (A + B) * (C + D):
LOAD A // AC M [A]
ADD B // AC  AC + M [B]
STORE T // M [T]  AC
LOAD C // AC  M[C]
ADD D // AC  AC + M [D]
MUL T // AC  AC * M [T]
STORE X // M[X]  AC
• Memory access is only limited to load and store
• Large program size

4. Zero-Address Instructions
•Can be found in a stack-organized computer
Program to evaluate X = (A + B) * (C + D):
PUSH A // TOS  A
PUSH B // TOS  B
ADD // TOS  (A + B)
PUSH C // TOS  C
PUSH D // TOS  D
ADD // TOS  (C + D)
MUL // TOS  (C + D) * (A + B)
POP X // M[X]  TOS
• The name “zero-address” is given to this type of computer because of the
absence of an address field in the computational instructions.

4. Addressing Modes
• Specifies a rule for interpreting or modifying the address field of the instruction before
the operand is actually referenced.
• We use variety of addressing modes:
• To give programming flexibility to the user
• To use the bits in the address field of the instruction efficiently
• Types of addressing modes:
i. Implied Mode
ii. Immediate Mode
iii. Register Addressing Mode
iv. Register Indirect Mode
v. Auto-increment or Auto-decrement Mode
vi. Direct Address Mode
vii. Indirect Addressing Mode
viii. Relative Addressing Modes
ix. Displacement Addressing Mode
x. Indexed Addressing Mode
xi. Stack Addressing Mode

Fig:AddressingModes

Basic Addressing Modes
• A = contents of an address field in the instruction
• R = contents of an address field in the instruction that refers to a
register
• EA = actual (effective) address of the location containing the
referenced operand
• (X) = contents of memory location X or register X

Table:BasicAddressingModes

Relative Addressing Modes
• The Address fields of an instruction specifies the part of the address which can be
used along with a designated register to calculate the address of the operand.
• Address field of the instruction is short
• Large physical memory can be accessed with a small number of address bits
• 3 different Relative Addressing Modes:
1.PC Relative Addressing Mode
• EA = PC + IR(address)
2.Indexed Addressing Mode
• EA = IX + IR(address){IX is index register}
3.Base Register Addressing Mode
• EA = BAR + IR(address)
• Effective address (EA):
• The effective address is defined to be the memory address obtained from the computation
dictated by the given addressing mode.
• The effective address is the address of the operand in a computational-typeinstruction.

Addressing Mode EffectiveAddress Content of AC
Direct Addressing 500 800
Immediate operand 201 500
Indirect address 800 300
Relative address PC+2+IR=702 325
Indexed address 500+100=600 900
Register - 400
Register indirect 400 700
Autoincrment 400 700
Autodecrement 399 450
Fig: Tabular list of Numerical example

5. Data Transfer and Manipulation
• Extensive set of instructions to give the user the flexibility to carryout
various computational tasks.
• Actual operations in the instruction set are not very different from one
computer to another.
• Can be classified into 3 categories, on the basis of type of operation
performed.
1. Data transfer instructions
2. Data manipulation instructions
3. Program Control Instructions

1. Data transfer instructions
Load LD Transfers data from memory to CPU
Store ST Transfers data from CPU to memory
Move MOV Transfers data from memory to memory
Input IN transfers data from input device to register
• Used for transferring data:
i. From memory to register,
ii. Register to memory,
iii. Register to register,
iv. Memory to memory,
v. Input device to register and
vi. From register to output device.

2. Data manipulation instructions
• Used for performing any type of calculations on data.
• Data manipulation instructions can be further divided into three types:
1. Arithmetic instructions
• Examples:
2. Logical and bit manipulation instructions
• Examples:
Operation Symbol
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Operation Symbol
Complement COM
AND AND
OR OR
Exclusive-OR XOR

3. Shift instructions
• Examples:
Operation symbol
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL

3. Program Control Instructions
• Used for controlling the execution flow of programs.
• Some examples:
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RTN

Program control
• Specify conditions for altering the content of the program counter,
while data transfer and manipulation instructions specify conditions
for data-processing operations.
Name Mnemonics
Branch BR
Jump JMP
Call CALL
Ret RET
Skip SKP
Test TST
Compare CMP

Status bit condition:
• Condition-code bits or flag bits.
• Supply additional information of ALU and stored data for further analysis.
• The four status bits are symbolized by c. S, Z, and V.
• The bits are set or cleared as a result of an operation performed in the ALU.
1. Bit C (carry) is set to 1 if the end carry C8 is 1, else cleared if the carry is 0.
2. Bit S (sign) is set to 1 if the highest-order bit F, is 1, else set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all O' s, else set to 0
otherwise. In other words, Z = 1 if the output is zero and Z = 0 if the output is not
zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1,
and cleared to 0 otherwise. This is the condition for an overflow when negative
numbers are in 2's complement. For the 8-bit ALU, V = 1 if the output is greater
than + 127 or less than-128.

Fig: Status register bit

Program interrupt
• Used to handle a variety of problems that arise out of normal program
sequence.
• Interrupt refers to the transfer of program control from a currently running
program to another service program as a result of an external or internal
generated request.
• Control returns to the original program after the service program is
executed.
• Quite similar to subroutine call–return procedure except for three variations:
1. The interrupt is usually initiated by an internal or external signal rather than from
the execution of an instruction (except for software interrupt as explained later);
2. The address of the interrupt service program is determined by the hardware rather
than from the address field of an instruction; and
3. An interrupt procedure usually stores all the information necessary to define the
state of the CPU rather than storing only the program counter.

• After a program has been interrupted and the service routine been
executed, the CPU must return to exactly the same state that it was
when the interrupt occurred.
• The state of the CPU at the end of the execute cycle is determined
from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions
• The collection of all status bit conditions in the CPU is sometimes
called program status word or PSW.

Types of Interrupt
• Three major types of interrupts:
1. External interrupts
2. Internal interrupts
3. Software interrupts
• External interrupts:
• come from input/output (I/0) devices,
• from a timing devices,
• from a circuit monitoring the power supply, or from any other external
source.
• Examples that causes external interrupts are I/0 device requesting transfer of
data, I/0 device finished transfer of data, elapsed time of an event, or power
failure.

Internal interrupts
• Arise from illegal or erroneous use of an instruction or data.
• Are also called traps.
• Internal interrupt is initiated by some exceptional condition caused by
the program itself rather than by an external event.
• Examples: interrupts caused by internal error conditions are register
overflow, attempt to divide by zero, an invalid operation code, stack
overflow, and protection violation.
• Are synchronous with the program while external interrupts are
asynchronous.
• If the program is rerun, the internal interrupts will occur in the same
place each time while external interrupts depend on external
conditions that are independent of the program being executed at the
time.

Software interrupts
• Initiated by executing an instruction.
• A special call instruction that behaves like an interrupt rather than a
subroutine call.
• Can be used by the programmer to initiate an interrupt procedure at
any desired point in the program.
• The most common use of software interrupt is associated with a
supervisor call instruction.
• This instruction provides means for switching from a CPU user mode
to the supervisor mode.
• This call is also called system call.

Stack Organization
• A storage device that stores information in such a manner that the item
stored last is the first item retrieved.
• The operation of a stack can be compared to a stack of trays.
• The last tray placed on top of the stack is the first to be taken off.
• A memory unit with an address register that can count only (after an
initial value is loaded into it).
• The register that holds the address for the stack is called a stack
pointer (SP) because its value always points at the top item in the
stack.

Stack Organization (cont.)
• Are always available for reading or writing.
• It is the collection of finite number of registers.
• Two operations of a stack are the insertion and deletion of items.
• The operation of insertion is called push (or push-down) and the
operation of deletion is called pop (or pop-up)
• These operations are simulated by incrementing or decrementing the
stack pointer register.

Register Stack
Fig: Block diagram of a 64-word stack
/* Initially, SP = 0, EMPTY = 1(true), FULL =
0(false)*/
Push operation Pop operation
SP  SP + 1 DR  M [SP]
M [SP]DR SP  SP + 1
If (SP = 0) then (FULL  1) If (SP = 0) then
(EMPTY  1)
EMPTY  0 FULL0

Memory Stack
• PC: used during fetch phase to
read an instruction.
• AR: used during execute phase to
read an operand.
• SP: used to push or pop items into
or from the stack.
• PUSH:
SP  SP - 1
M[SP]  DR
• POP:
DR  M[SP]
SP  SP + 1
400
400
399
399
399
300
Data
( Operands)
Program
Instructi on)
(
100
P
AR
S
Stack
Stack grows
In this direction

Unit 2.1. cpu

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to Unit 2.1. cpu

Similar to Unit 2.1. cpu (20)

Recently uploaded

Recently uploaded (20)

Unit 2.1. cpu