Ddis3010 course work_spec_slides

419 views

Published on

Course work specification for DDIS3010 2012/13.

Published in: Education
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total views
419
On SlideShare
0
From Embeds
0
Number of Embeds
4
Actions
Shares
0
Downloads
2
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Ddis3010 course work_spec_slides

  1. 1. An FPGA-Based IEEE1149.1 BST ControllerHiBu | DDIS3010 | josemmf@hibu.no Digitale Systemer 2012/13 [ November 2012 ]
  2. 2. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 2 / 12Outline of this presentation● What is the deliverable of this work?● Main functional features● Processor architecture and instruction set● Test workflow● Main challenges● Can we go further?● How do I start?
  3. 3. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 3 / 12Envisaged deliverableOverall block diagram:
  4. 4. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 4 / 12Main functional features● Support at least one Test Access Port (TAP)● Accept "SVF-like" commands● Receive the test code serially via RS-232C● One "Run test" push button● One "Pass" led, one "Fail" led
  5. 5. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 5 / 12 Test processor block diagram[ you can choose the values of CLmax and TVmax bits ]
  6. 6. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 6 / 12Source codeMinimum set of "SVF-like" commands: Command Description RESET Sets the boundary-scan logic (TAP controller FSM) in Test-Logic-Reset TMS 0 / 1 Sets TMS to 0 / 1 and applies one clock pulse to TCK SHF N X Shifts an N-bit sequence (X) into the [instruction | selected data] register SHFCP N X,Y,Z Shifts an N-bit sequence (X) into the [instruction | selected data] register and compares the output sequence with its expected response (Y) using the given mask information (Z) RUNTEST N Sets TMS to 0 and applies N [16-bit value] clock pulses to TCK EOP End-of-program (not a real command; marks the end of the object code)
  7. 7. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 7 / 12Source code > Object codeUse the TASM shareware cross-assembler togenerate the object code: MNEM. ARGS. OPCODE BYTES MODOP. CLASS ----------------------------------------------- RESET "" A1 01 NOTOUCH 1 TMS * A2 02 NOTOUCH 1 SHF * A3 02 NOTOUCH 1 SHFCP * A4 02 NOTOUCH 1 RUNTEST * A5 03 SWAP EOP "" 454F50 03 NOTOUCH 1(visit http://home.comcast.net/~tasm/ for +info)
  8. 8. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 8 / 12Test workflow● Produce the source code in SVF-like format● Compile to Intel Hex object code via TASM● Send the object code to the test processor memory via RS-232C● Use the "Run" button to execute the test and the leds to check the resultWrite the source ➨ Generate ➨ Send the object file (*.obj) ➨ Run the testcode (*.asm) using the object to the Avnet board via (press Run or sendnotepad++ code RS-232C command via RS- (tasm –XX 232C) name.asm)
  9. 9. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 9 / 12Challenges vs. presentations so far● Develop the VHDL model for the test processor -- recall: design of FSMD (Morten and Hakon), the Xilinx ISE tools (Gunnar and John), and ModelSim (Alex and Per)● Adapt existing models for the UART (Alex and Per) and Xilinx specific memory (Bard and Gunnar)● Integrate, verify via simulation, validate via the Avnet board (John and Bard)
  10. 10. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 10 / 12Going further● Enable a "step mode" to run the test (one command at a time)● Support two TAPs instead of just one (enabling test actions simultaneously in both BS chains?)● Support control and observation of parallel I/O pins in the edge connectors● Use the LCD to display test information (Morten and Hakon)● What else?...
  11. 11. [ josemmf@hibu.no | DDIS-3010 2012/13 ] 11 / 12How do I start? [one possible way]● Make sure that you understand how the test processor architecture works (draw the state diagrams for executing each instruction)● Sketch the hardware structures that enable the implementation of each block (e.g. how do you implement the Program Counter?)● Code and simulate each structure in VHDL● Integrate and extend validation to the whole test processor architecture● Integrate with RS-232C and memory...
  12. 12. Thanks for your attention! HiBu | DDIS3010 | josemmf@hibu.no Digitale Systemer 2012/13 [ November 2012 ]

×