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High Speed Transaction-basedHW-SW Coverification<br />Laureano Felipe Carrasco Costilla<br />May 4, 2011<br />
Traditional Emulator Deployment:In-Circuit Emulation (ICE)<br />process(clk)<br />Begin<br />	if rising_edge(clk) then<br ...
ICE: Pros and Cons<br />
Traditional Emulator Deployment:Cycle-based coverification<br />Cycle-Based<br />Test Bench<br />Communication Overhead<br...
Cycle-based coverification pros/cons<br />
Transaction-based coverification<br /><ul><li>Testbench and Emulated DUT are synchronized only when required
Test bench and DUT can run in parallel and transactions can be queued
The speed improvement over cycle-based can be orders of magnitude faster reaching tens of MHz</li></ul>Cycle-Based<br />Te...
Communication<br />Infrastructure<br />What is a transactor:Conceptual design<br />Back-end<br /><ul><li>BFM model to conv...
Compute intensive</li></ul>Front-end<br /><ul><li>C++ (SC/SV) model to send/receive high-level commands (transactions) to/...
Not compute intensive</li></ul>HDL Simulator<br />Emulator<br />PC<br />Transactor<br />HDL<br />DUT<br />HDL<br />Testben...
DUT<br />pixel_clk<br />Video <br />Processor<br />C++<br />Testbench<br />Frame<br />Generator<br />Video_In<br />Transac...
Natural integration withVirtual Platforms<br />System-on-Chip<br />CPU(s)<br />Peripheral<br />InstructionSet Simulator<br...
Creating a transactor: Acellera’s SCE-MI 2.0<br />SCE-MI 2.0 defines three types of HW/SW communication<br /><ul><li>Macro...
Function-based interface (Limited subset of the SystemVerilog DPI)
SystemVerilog compatible, transactors can be simulated
Only functions are allowed (no import/export tasks), each function call is a transaction
Pipe-base interface (fixed functions)
Transactions go through unidirectional pipes
Data is not guaranteed to be available to the consumer immediately
User has to map data to messages and insure response
Not 100% SystemVerilog compatible</li></ul>SCE-MI 2.0 is not optimized for performance<br /><ul><li>Each call in SCE-MI ge...
No DPI-based streaming or parallel communication
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Track c-High speed transaction-based hw-sw coverification -eve

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Track c-High speed transaction-based hw-sw coverification -eve

  1. 1. High Speed Transaction-basedHW-SW Coverification<br />Laureano Felipe Carrasco Costilla<br />May 4, 2011<br />
  2. 2. Traditional Emulator Deployment:In-Circuit Emulation (ICE)<br />process(clk)<br />Begin<br /> if rising_edge(clk) then<br /> Q <= not Q;<br /> end if;<br />end process; <br />The emulator, connected to a physical target system in place of a yet-to-be-built chip, either drives the target system or is driven by the target system<br />The RTL design is compiled in a workstation into a binary object<br />Emulator<br />Cables<br />PCIe Interface<br />Target System<br />The design binary is downloaded into the emulator<br />
  3. 3. ICE: Pros and Cons<br />
  4. 4. Traditional Emulator Deployment:Cycle-based coverification<br />Cycle-Based<br />Test Bench<br />Communication Overhead<br />Emulated DUT<br />process(clk)<br />Begin<br /> if rising_edge(clk) then<br /> Q <= not Q;<br /> end if;<br />end process; <br />Time<br />The RTL design is compiled in a workstation into a binary object<br />Emulator<br />PCIe Interface<br />The design binary is downloaded into the emulator<br />The emulator is driven by the cycle-based Verilog/VHDL/C/C++ testbench<br />
  5. 5. Cycle-based coverification pros/cons<br />
  6. 6. Transaction-based coverification<br /><ul><li>Testbench and Emulated DUT are synchronized only when required
  7. 7. Test bench and DUT can run in parallel and transactions can be queued
  8. 8. The speed improvement over cycle-based can be orders of magnitude faster reaching tens of MHz</li></ul>Cycle-Based<br />Test Bench<br />Communication Overhead<br />Emulated DUT<br />Time<br />Transaction-Based<br />Test Bench<br />Communication Overhead<br />Emulated DUT<br />Time<br />
  9. 9. Communication<br />Infrastructure<br />What is a transactor:Conceptual design<br />Back-end<br /><ul><li>BFM model to convert high-level commands into bit-level protocol
  10. 10. Compute intensive</li></ul>Front-end<br /><ul><li>C++ (SC/SV) model to send/receive high-level commands (transactions) to/from Testbench
  11. 11. Not compute intensive</li></ul>HDL Simulator<br />Emulator<br />PC<br />Transactor<br />HDL<br />DUT<br />HDL<br />Testbench<br />C++/SC/SV<br />Testbench<br />TX<br />Back-end<br />Verilog BFM<br />Model<br />Cycle-Level Communication<br />Front-end<br />C++/SC/SV<br />Model<br />RX<br />Hi-level Commands<br />Bit-level Protocol <br />
  12. 12. DUT<br />pixel_clk<br />Video <br />Processor<br />C++<br />Testbench<br />Frame<br />Generator<br />Video_In<br />Transactor<br />v_sync<br />h_sync<br />pixel<br />Example: Video-in transactor<br />Emulator<br />Verilog<br />Testbench<br />Frame<br />Generator<br />Video Frame<br />ONE FRAME<br />pixel_clk<br />v_sync<br />h_sync<br />pixel<br />1st row pixels<br />2nd row pixels<br />Nth row pixels<br />
  13. 13. Natural integration withVirtual Platforms<br />System-on-Chip<br />CPU(s)<br />Peripheral<br />InstructionSet Simulator<br />Peripheral<br />Memory<br />Control<br />Memory<br />TLM Bus<br />RTL<br />Device<br />SystemI/O<br />SystemI/O<br />Device<br />Emulator<br />ESL Virtual Platform<br />Cycle/Bit<br />Accurate RTL<br />Transaction<br />Level<br />TLM 2.0 Transactor<br />
  14. 14. Creating a transactor: Acellera’s SCE-MI 2.0<br />SCE-MI 2.0 defines three types of HW/SW communication<br /><ul><li>Macro-based interface (SCE-MI 1 compatibility)
  15. 15. Function-based interface (Limited subset of the SystemVerilog DPI)
  16. 16. SystemVerilog compatible, transactors can be simulated
  17. 17. Only functions are allowed (no import/export tasks), each function call is a transaction
  18. 18. Pipe-base interface (fixed functions)
  19. 19. Transactions go through unidirectional pipes
  20. 20. Data is not guaranteed to be available to the consumer immediately
  21. 21. User has to map data to messages and insure response
  22. 22. Not 100% SystemVerilog compatible</li></ul>SCE-MI 2.0 is not optimized for performance<br /><ul><li>Each call in SCE-MI generates a HW/SW synchronization point
  23. 23. No DPI-based streaming or parallel communication
  24. 24. It does not leverage emulator-specific performance improvements</li></li></ul><li>Creating a transactor: ZEMI-3<br />ZEMI-3 is EVE’s behavioral SystemVerilog compiler that:<br /><ul><li>generates RTL BFMs for the HW portion of the transactor
  25. 25. Creates DPI-based low-level communication layer between HW and SW</li></li></ul><li>Communication<br />Infrastructure<br />Transactor example<br />A transactor to write and read from a virtual memory implemented in the PC <br />Emulator<br />PC<br /> Memory Transactor<br />HDL<br />DUT<br />Mem_dout<br />read<br />HDL<br />Testbench<br />Virtual<br />Memory<br />Mem_din<br />Back-end<br />SV BFM<br />Model<br />Cycle-Level Communication<br />Mem_addr<br />Front-end<br />C++ Model<br />Mem_re<br />Mem_we<br />Write<br />
  26. 26. The virtual memory:Memory32.cc<br />#include "Memory32.hh"<br />#include <stdio.h><br />#include <string.h><br />Memory32::Memory32(unsigned int depth)<br />{<br /> _memArray = new unsigned int [depth];<br />memset(_memArray, 0, depth*sizeof(unsigned int));<br />}<br />Memory32::~Memory32()<br />{<br /> delete [] _memArray;<br />}<br />unsigned int Memory32::read(constunsigned intaddr)<br />{<br /> return _memArray[addr];<br />}<br />void Memory32::write(constunsigned intaddr, constunsigned intdin)<br />{<br /> _memArray[addr] = din;<br />}<br />
  27. 27. The transactor’s front-end: mem_xtor.cc<br />#include <stdlib.h><br />#include <stdio.h><br />#include <mem_xtor.h><br />#include "Memory32.hh"<br />extern "C" void readData(constsvBitVecValaddr[1], svBitVecValdout[1])<br />{<br />svScope s = svGetScope();<br /> Memory32 *mem = (Memory32 *)(svGetUserData(s, (void *)(readData)));<br />dout[0] = mem->read(addr[0]);<br />printf("# Read Data addr=%d, dout=%xn", addr[0], dout[0]);<br />}<br />extern "C" void writeData(constsvBitVecValaddr[1], constsvBitVecVal din[1])<br />{<br />printf("# Write Data addr=%d, din=%xn", addr[0], din[0]);<br />svScope s = svGetScope();<br /> Memory32 *mem = (Memory32 *)(svGetUserData(s, (void *)(writeData)));<br />mem->write(addr[0], din[0]);<br />}<br />…<br />…<br />extern "C" void initialize()<br />{<br />printf("# Initializing SW part of the transactorn");<br />svScope s = svGetScope();<br /> Memory32 *newMem = new Memory32(MEM_DEPTH);<br />svPutUserData(s, (void *)(read), (void *)(newMem));<br />svPutUserData(s, (void *)(write), (void *)(newMem));<br />printf("# Init donen");<br />}<br />
  28. 28. The transactor’s back-end<br />module mem_xtor(input clk, input [15:0] addr, input [31:0] din, input ce, input we, input re, output reg [31:0] dout)<br /> import "DPI-C" context function void readData(input bit [15:0] addr, output bit [31:0] dout);<br /> import "DPI-C" context function void writeData(input bit [15:0] addr, input bit [31:0] din); <br /> import "DPI-C" context function void initialize();<br /> initial begin<br />dout = 0;<br /> initialize();<br />end<br />always @(posedgeclk)<br /> begin<br /> if (we) begin<br />writeData(addr, din);<br />if (re) dout = din;<br /> end<br /> else <br /> if (re) readData(addr, dout);<br /> end<br />endmodule<br />
  29. 29. Not all has to be written!<br />Very rich and increasing portfolio of transactors and verification IP<br />
  30. 30. Using a transactor<br />…i2c_driver i2c_xtor(.sda(sda1),.scl(scl1),.sda_oe(sda_oe1),.scl_oe(scl_oe1));defparami2c_xtor1.cclock="i2c_clk";defparami2c_xtor1.debug = "yes";…<br />Design Verification Environment<br />Xtor Doc<br />int main (intargc, char *argv[]) {Board* board = 0; I2c* i2c_interface = 0; ... try { board = Board::open(ZWORK);fflush(stdout);fflush(stderr); ... i2c_interface = new I2c; ...while(!i2c_interface->runBFM(RunUntilTrnSent));...<br />Testbench.cc<br />
  31. 31. Case study: ICE wireless platform<br />Emulator @ few hundreds of kHz<br />DUT<br />DDR Memory<br />Interface<br />Flash Memory<br />Interface<br />NTSC TV<br />Interface<br />Frame<br />Grabber<br />ARM11<br />Core<br />LCD Display<br />Interface<br />Frame<br />Grabber<br />Terminal<br />Interface<br />DSP<br />Core<br />Digital Still Camera<br />Interface<br />Frame<br />Capture<br />Logic<br />Keypad<br />Interface<br />USB 2.0<br />Interface<br />HW<br />Bridge<br />Memory<br />Ethernet<br />Ethernet10/100<br />Interface<br />HW<br />Bridge<br />I2S Audio<br />Interface<br />HW<br />CODEC<br />JTAG<br />Interface<br />Lauterbach<br />Pod<br />
  32. 32. Case study: transaction-based<br />EVE’s ZeBu emulator @ 5MHz<br />PC – Software Test Environment<br />Display<br />Window<br />Display<br />Window<br />RTB<br />DUT<br />DDR Memory<br />Interface<br />Synthesizable<br />DDR Memory<br />Flash Memory<br />Interface<br />Synthesizable<br />Flash Memory<br />NTSC XTOR<br />NTSC TV<br />Interface<br />ARM11<br />Core<br />LCD Display<br />Interface<br />LCD XTOR<br />Terminal<br />Interface<br />Terminal XTOR<br />DSP<br />Core<br />Image<br />Files<br />Digital Still Camera<br />Interface<br />DSC XTOR<br />Logic<br />Keypad<br />Interface<br />Keypad XTOR<br />HDD<br />C Model<br />USB 2.0<br />Interface<br />USB Function<br />XTOR<br />Memory<br />Ethernet<br />Ethernet 10/100<br />Interface<br />Ethernet XTOR<br />Bridge<br />NIC<br />Card<br />I2S Audio<br />Interface<br />I2S XTOR<br />SW<br />CODEC<br />JTAG<br />Interface<br />JTAG XTOR<br />
  33. 33. SW Debug<br />TV - Display<br />Terminal - UART<br />Main<br />TSC2101 - SPI<br />Battery Gauge - HDQ<br />LCD - Display<br />RTC – I2C<br />GPIO <br />GPIO Expander<br />Keypad - GPIO<br />Case study: PC sample display<br />TCM8002MD – CCP Camera<br />
  34. 34. Case study: results<br />Able to boot Symbian OS in 45 seconds<br />Allowed starting of early software development and HW/SW coverification<br />
  35. 35. Transaction based coverification<br />Verification IP, <br />ZEMI-3 &<br />ESL Tools<br />
  36. 36. Thank you!<br />

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