High-Level Synthesis Skill Development Needs - IEDEC
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Presentation at the March 2013 IEDEC conference in Santa Clara, CA. Outlines the need for hardware design to move up in abstraction to SystemC and high-level synthesis, and the main barrier left preventing this - a rare combination of skills. The best place to address this skill set gap is in university curricula.
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High-Level Synthesis Skill Development Needs - IEDEC
- 1. Modern System-on-Chip Challenges Require New Skills in Electronic Engineering Graduates Jack Erickson and Mark Warren Cadence Design Systems, Inc. IEDEC March 4, 2013
- 2. The design productivity gap Productivity / Complexity Gates / cm2 Moore’s Law (59% CAGR) Design GAP Design Productivity (20-25% CAGR) 0.35 μm 0.25μm 0.18μm 0.15μm 0.13μm 0.09 μm 0.065μm 0.045μm 0.032μm Source: Semico Research Corp. 2 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 3. One solution: more IP blocks Source: IBS, Inc. 3 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 4. Another solution: more engineers per project Source: IBS, Inc. 4 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 5. Abstraction must be raised to close the gap! Why hasn’t it happened yet? Abstraction delivers designs more quickly, with less effort 10000 System-Level GAP Design Productivity (gates/per) (High Level Synthesis) 1000 RTL (Logic Synthesis) 65nm device 100 ~50M-100M gates Gates 10 (Schematic 0.5 device Capture) ~500K-1M gates Switches 1 (SPICE) 1970's 1980 1990 2000 2010 5 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 6. Cadence’s approach Synthesize and verify entire design in SystemC IEEE SystemC with transaction-level models (TLM) C-to-Silicon Compiler Embedded RTL Compiler synthesis and RTL connected design, verification, and Incisive implementation to ensure closure Metric- ECO Driven Anytime Verification Extend metric-driven verification methodology to start at TLM SoC FPGA Deliver the next quantum leap in productivity 6 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 7. Challenges in moving to higher-abstraction design and verification Robust • SystemC is now an IEEE standard Design • Modern HLS supports the full datapath-control Support spectrum Quality of • Embedded logic synthesis guides some HLS tools Results • Still work to do – physical, flow development, etc. Verification • Multi-level metric-driven verification methodology Methodology • Adoption just starting – seeing good returns • Rare combination of skills today Skills • Need to develop new breed of engineer 7 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 8. New combination of skills required SystemC Constraints Hardware architecture design Block Initial Refined Gain Hardware micro-architecture for QoR design design C++ ECC 17.637 mm2 1.035 mm2 17 X SystemC Encoder 0.160 mm2 0.065 mm2 2.46 X HLS tool operation Decoder 17.477 mm2 0.970 mm2 18 X RTL synthesis optimization concepts Source: ITRI, “Building a NAND flash controller with high-level synthesis” 8 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 9. Difficult for engineers to find time for training in the commercial sector… Source: IBS, Inc. 9 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 10. Courses and curricula available today 10 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 11. Courses and curricula available today 11 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 12. Courses and curricula available today 12 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 13. Resources available Enabling HLS course development 13 © 2013 Cadence Design Systems, Inc. All rights reserved.
- 14. 14 © 2013 Cadence Design Systems, Inc. All rights reserved.
Editor's Notes
- The advances in silicon capacity on a chip are far outpacing advances in the ability to utilize that silicon. This is extremely costly, in that teams are faced with the choice of compromising on either schedule, engineering costs, or silicon capabilities in order to meet their primary goals. Causes of this growing gap can be found in design, verification, and implementation. However one key root cause can be traced to the abstraction at which design is performed.
- This chart depicts the approximately ten-fold hardware design productivity increase per decade, from the roughly one gate-equivalent per day of the early 70's to the roughly one thousand gate-equivalent per day at the turn of the century. To continue this trajectory requires transitioning design to yet another higher level of abstraction; system-level synthesis.
- Cadence enables TLM design with its C-to-Silicon Compiler. C-to-S enables a single specification of functional intent – both control and datapath together – using industry standard TLM. It embeds RTL Compiler, production-proven global synthesis, to ensure that the optimizations it makes will hold up during synthesis and implementation. It also provides intuitive graphical feedback that utilizes this information to guide you to make better implementation decisions in order to meet the goals of your target device. Finally, because it is linked to the Cadence Silicon Realization flow, ECOs are automated throughout the entire flow.
- Design results from:“Building a NAND flash controller with high-level synthesis”http://www.eetimes.com/design/memory-design/4238287/Building-a-NAND-flash-controller-with-high-level-synthesisInitially used a software implementation of BCH code. The decoder was taking up 99% of the area because values were being stored in huge look-up tables that were implemented in hardware as arrays.Encodermanually performed unfolding for the parity calculation and shortened the path length for a sequence of XOR operations. Decoder: reduced the array size of the logarithm and anti-logarithm values of GF. Only a small part of the logarithm values were kept, dedicated arithmetic hardware for multiplication and addition operationsThe Berlekamp iterative algorithm was replaced by the Berlekamp tree algorithm with a set of formulas. For the Chien search algorithm, we skipped unnecessary attempts at the root to improve the latency of decoding operations.
- Polytechnic University of Turin in Italy.“Modeling and optimization of embedded systems,” taught by Professor LucianoLavagno. Part of their curriculum towards a degree in Electronic Engineering.Columbia University. CSEE 6868E: System-on-Chip Platforms, led by Professor Luca Carloni and Dr. Michele Petracca. Targeted toward utilizing SystemC and TLM to design SoC hardwareUniversity of Aizu in Japan. SYA08 – Electronic Design Automation for System-Level Design, led by Professor Hiroshi Saito [11]. First course offered in Japan that teaches high-level synthesis for hardware design, and the goal is to nurture the next generation of system-level engineers
- Polytechnic University of Turin in Italy.“Modeling and optimization of embedded systems,” taught by Professor LucianoLavagno. Part of their curriculum towards a degree in Electronic Engineering.Columbia University. CSEE 6868E: System-on-Chip Platforms, led by Professor Luca Carloni and Dr. Michele Petracca. Targeted toward utilizing SystemC and TLM to design SoC hardwareUniversity of Aizu in Japan. SYA08 – Electronic Design Automation for System-Level Design, led by Professor Hiroshi Saito [11]. First course offered in Japan that teaches high-level synthesis for hardware design, and the goal is to nurture the next generation of system-level engineers
- Polytechnic University of Turin in Italy.“Modeling and optimization of embedded systems,” taught by Professor LucianoLavagno. Part of their curriculum towards a degree in Electronic Engineering.Columbia University. CSEE 6868E: System-on-Chip Platforms, led by Professor Luca Carloni and Dr. Michele Petracca. Targeted toward utilizing SystemC and TLM to design SoC hardwareUniversity of Aizu in Japan. SYA08 – Electronic Design Automation for System-Level Design, led by Professor Hiroshi Saito [11]. First course offered in Japan that teaches high-level synthesis for hardware design, and the goal is to nurture the next generation of system-level engineers