Chip ex 2011 faraday

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Chip ex 2011 faraday

  1. 1. Integral System-Level Design Integration,Simulation, Verification & Implementation By jyhwang@faraday-tech.com May 4, 2011
  2. 2. Market Fact for Increasing Complex System-Level DesignPND/MID Automotive Netbook/Smartbook The product life cycle of every generation for most industrial products, is around and even less than 1 year. But, it seems twice devices are built into the same chip area per 18 months VoIP by Moore’s law. STB Digital-TV E-Book IPC PND May 4, 2011
  3. 3. Brief of Complex System-Level Design from Spec. to Be a Product Firm product spec. Get IPs from sources System-level design (SLD) integration from IPs by Product owner self, and Help from IP sources Other time/resource-consuming efforts for - Frontend simulation/ verification Backend Implementation/ Verification System-level verification, if possible Sign-off & Go-To- Manufacture Software support OS Driver (IP/ICE) Toolchain System application bring-up May 4, 2011
  4. 4. Bottleneck of Increasing Complex System- Level Design 2 months 2 months ~3 months 3 ~ 6 months 2 months SoC/ASIC SoC/ASIC Spec. Platform integration Data-in Preparation Integration ImplementationKickoff Spec Trial Data-In Formal Data-In Tape-Out Survey Market Simulation-oriented Synthesis-oriented Implementation- Backend Gate-To- Requirement integration integration oriented tasks GDSII tasks Document. (MRD) Get IPs from sources. Synthesizable target Clock/reset tree SLD physical Gather Product SLD integration from IPs. designs more than control/constraints. implementation Requirement BFM testbench creation models, such as clock Chip-level synthesis SLD physical Document. (PRD) & C models for control, reset control, design constraints. verification - Refine/Trade-off integration test. (verify real I/O and so on. Pin/Pad assignment & DRC/ERC/LVS MRD & PRD. connection, bus, and so C patterns, instead of Chip environment Verified GSDII for Early System on) BFM-only ones. constraints. Go-To- Architecture DFT integration. Iterative verification & FloorPlan constraints. Manufacture Evaluation. Iterative verification & debugging. Pre-layout design data Post-layout Get Product Brief. debugging. FPGA emulation 2. base & simulation. design data base IP Sourcing. FPGA emulation 1. Etc. ATPG creation. & simulation. Etc. Etc. Etc. Sign-off & T/O. Etc. Ordinary solutions take 12 ~ 16 months from project kickoff to tape-out for complex SoC designs. May 4, 2011
  5. 5. Fact of Increasing Complex System-Level DesignThe product life cycle of everygeneration for most industrial products,is around and even less than 1 year.But, it seems twice devices are built into the samechip area per 18 monthsby Moore’s law. Ordinary solutions take 12 ~ 16 months from project kickoff to tape-out for complex SoC designs.All of us are competing against – Design/Verification Complexity Time & our Life May 4, 2011
  6. 6. The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability – 1/5Pack and maintain each IP as an Abstract Model (SPIRIT) and basic re-useentity for accumulative knowledge data base. USB2.0 USB 1.1 PHY PHY Bus Controller MAC USB2.0 USB1.1 AHB to PCI FA526 (Arbiter, 10/100 Device Host Bridge Decoder) AHB Bus AHB to APB LCD Controller SDRAM Controller DMA Controller Static Memory Controller Input IP Model Output Bridge Interface Interface I2S/ PWM I2C GPIO INTC WDT Timer SMMC AC97 APB Bus Power ST BT FF SD/ IrDA SSP CF SSP manage UART UART UART MMC Side Band Signals SPIRIT stands for “Structure for Packaging, Integrating and Re-using IP within Tool flows”. May 4, 2011
  7. 7. The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability - 2/5Use three Microsoft Excel specification sheets that involve SPIRIT instances ofwanted IPs, to capture the whole SLD every time.Tables Description Applied Module$<design>.pin.xml Chip pin-out list table: chip Chip Construction: pin name, IO types pin module creation$<design>.dftcfg.xml DFT configuration table: Chip Construction: internal scan, mbist, VSIA, DFT module creation hard-IP test, IOLT, process monitor, debug signals$<design>.resmap.xml Resource table: IP list, Core Construction instances, Master/Slave mapping, interrupt, DMA May 4, 2011
  8. 8. The Reliable Integral SoC Methodology forAccumulative Knowledge & Re-usability - 3/5 Three Microsoft Excel specification sheets look as - May 4, 2011
  9. 9. The Reliable Integral SoC Methodology for Accumulative Knowledge & Re-usability - 4/5Then, all things can be looked like - Capturing specification Creation on demand Plugging Implementation/V erification environment creationAnd, can be done more safe, reliable & accumulative as Plug & Play methodautomatically. May 4, 2011
  10. 10. The Reliable Integral SoC Methodology forAccumulative Knowledge & Re-usability - 5/5SoCompilerTM IDEAutomatic SLD RTL design integrationRapid DFT integrationAutomatic verification environment generation (Bus, IO, DFT)Test-bench creation and pattern-reuseStatic timing analysis environment generationDesign synthesis environment generationLink to existing robust ASIC implementation flow nativelyLink to FPGA emulation platform SoFlexibleTM with FPGA netlist andconstraint May 4, 2011
  11. 11. Achievement of Reliable Integral SoC Methodology for Complex SLD Ordinary Solutions take 12 ~ 16 months from project kickoff to tape-out for complex SoC designs. 2 months 2 months ~3 months 3 ~ 6 months 2 months SoC/ASIC SoC/ASIC Spec. Platform integration Data-in Preparation Integration ImplementationKickoff Spec Trial Data-In Formal Data-In Tape-Out 2.5 w 3.5 w 1 month 1.5 months 2 months Spec Signoff Platform Delivery Trial Data-In Tape-Out Platform Platform Simulation SynthesisKickoff Formal Data-In Faraday’s reliable integral SoC methodology can take only 6 months to achieve by the accumulative knowledge and re-usability. May 4, 2011
  12. 12. Brief of Complex System-Level Design from Spec. to Be a Product (repetition) Firm product spec. Get IPs from sources System-level design (SLD) integration from IPs by Product owner self, and Help from IP sources Other time/resource-consuming efforts for - Frontend simulation/ verification Backend Implementation/ Verification System-level verification, if possible Sign-off & Go-To- Manufacture Software support OS Driver (IP/ICE) Toolchain System application bring-up May 4, 2011
  13. 13. Ordinary SoC evaluation-purpose-only platform Pre-defined system-level design (SLD), built into the chip and the evaluation platform. May include some S/W or tool kits for the evaluation. Can’t be another targeted SLD SoC chip with different system/ bus architecture, I/O address mapping, etc. Help for – IP evaluation.Overall evaluation platform Fundamental rough S/W development. May 4, 2011
  14. 14. SoFlexibleTM FPGA emulation platform EVB Integrating the targeted SLD into the FPGA emulation platform. Help for – Consistent/Solid firm IPs from soft IPs, instead of any IP modeling efforts. FPGA System-level function verification. Fundamental system architecture evaluation.Wanted passive components Further exact S/W development. May 4, 2011
  15. 15. SoDualWareTM Technology – 1/3 May 4, 2011
  16. 16. SoDualWareTM Technology – 2/3 May 4, 2011
  17. 17. SoDualWareTM Technology – 3/3 Silicon hard IPs in the realized platform, utilized to support the targeted SLD. Help for – Native IP modeling. IP evaluation. Peripheral modeling, connecting to real world. System-level verification. Further detailedRealized platform system architecture evaluation. Targeted system-level More exact S/W design development. May 4, 2011
  18. 18. Thank you Faraday distributor in Israel:Advanced Semiconductor Technology Ltd. (AST) Tel: +972-9-7744278 Email: webinfo@ast.co.il May 4, 2011

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