The document describes the key steps in the PCB manufacturing process including: 1) Generating panelized artwork and drill programs from Gerber files and checking for design rules. 2) Laminating layers together with prepreg and applying heat and pressure. 3) Drilling, electroless plating, and developing circuit patterns on inner and outer layers. 4) Electrolytic plating of copper and tin, stripping resist, and etching unwanted copper.

1. PCB Process Flow
Issue
Material
Resist Coat
Material
Oxide
Develop Etch
& Strip Resist
DrillingLamination
UV Expose
UV Expose
Electroless Copper
Deposition
Develop
Pattern
Plate (Cu,Tin)
Surface Finishing
HASL (solder),
Gold or Silver
SoldermaskStrip Tin
Strip Resist
& Etch
NC RouteSilkscreen
AOI
T-Up
Inspection
Pre-Mask
Inspection
Inspection
Electrical
Test
Final
Inspection
Resist Coat
Panel
Ship

2. Tooling
 Gerber files are panelized
– Optimum panel utilization is key
 Drill program is generated at the same time
 Panelized artwork is plotted
– Negative image: internal layers
– Positive image: external layers
 CAM design rule check
– Spacing
– Annular ring
– Soldermask clearance
 First article inspection
Drilled panel representative of production panel
– Mechanically inspected

3. Dryfilm Resist Coating
 Epoxy/Glass laminates are used
– Material thickness: .0025” - .125”
– Typical copper weights .5 oz - 2 oz
 Incoming inspection
– Thickness
– Copper weight
– Surface imperfections
Epoxy/Glass
Copper Clad

4. Inner layer Imaging
 Material is coated with dryfilm resist (A)
– Dryfilm is photo-sensitive
– Resists etching chemistry
 Artwork image is transferred onto coated panels
– Artwork is placed over panels as they go into exposure units
– Clear area on film allows for polymerization
– Emulsion area prevents polymerization
– Non-polymerized dryfilm develops away
Dryfilm
Copper
Epoxy/Glass
Dryfilm
Image
Exposed Copper
(A) (B)

5. Inner Layer Etch
 Imaged panels are etched
 Etching chemistry attacks exposed copper
 Dryfilm is stripped
Etch Process After Etch

6. Automated Optical Inspection
 AOI units inspect etched inner layers
– Program: gerber down load
– Program: artwork learned
 AOI works off reflected light
– Oxidation produces psuedo defects
– Defects are displayed on monitor and verified
 Inner layers are oxide coated after AOI

7. Lamination
 Inspected inner layers
panels are kitted
 Panels are layed up
between two stainless
steel plates
– Prepreg is used as the
bonding agent
– B-stage, semi-cured
FR4
 Heat and pressure are
applied to laminate the
panels
Layer 1
Layer 3
Layer 2
Layer 4
Layer 1
Layer 3
Layer 2
Layer 4
From 6 - 10 multilayers
Prepreg
Copper Foil
Separator Sheet:
12 mil thick
aluminum, used to
avoid panel sticking
Steel plate

8. Drilling
 NC Drill machines are used
- 4 - 6 spindels / machine
- Auto tool change
 Stack heights up to 3 panels high
- Drill size
- Board thickness
- Pad-to-hole ratio
 Electroless copper plating
- Permanganate desmear
- 80 micro-inches thick

9. Outer Layer Imaging
 Drilled / plated panels are dryfilm coated
 Panels are UV exposed
- Positive image
 Panels are developed
- Exposing circuitry and holes

10. Electrolytic Plating
 Exposed areas of panel are electrolytically
plated.
- Copper (.001 min avg)
- Tin
 Dryfilm is stripped exposing unwanted copper
 Unwanted copper is etched away
 Tin is stripped.

11. Soldermask (LPI, liquid-photoimageable)
 The entire panel is coated with LPI S/M
- Automated DP1000 screeners
– Tack dried after coating
 LPI expose and develop
– Same as with I.L & O.L imaging
 Soldermask is used to define the component holes
and pads
 Thermal cure: 1 hour @ 150 C

12. Surface Finishing
 HASL, Solder
– Soldermask defines areas which are to be coated
with solder
– Entire panel is immersed in a bath of molten solder
– Hot air knives blow off the excess solder
 Silver
 ENIG, Electroless nickel immersion gold

13. Fabrication
 Panels are silk-screened prior to fabrication
 Boards are de-panelized with NC route
machines
- 4 spindles
- Stack heights up to 4 panels high
v Thickness
v Tolerances
v Radius

14. Electrical Test
 Tested for opens & shorts
 Bed of nails
 Netlist from gerber
– Netlist compared to CAD netlist
– IPC-356 format