Design_and_Investigation_of_FRT_Schemes_for_Three-Phase_Grid-Tied_PV_System.pdf

Design and Investigation of FRT Schemes for
Three-Phase Grid-Tied PV System
Saif-ul-Islam∗, Kamran Zeb∗†, Waqar Uddin∗,
Imran Khan‡, Muhammad Ishfaq∗, Z. Ullah§, Hee Je Kim∗
∗School of Electrical Engineering, Pusan National University, Busan, South Korea
†Dept. of Electrical Engineering, National University of Sciences and Technology, Islamabad, Pakistan
‡C2N, University of Paris Sud, University of Paris Saclay, Palaiseau, France
§Electrical Engineering Department, University of Management and Technology, Sialkot, Pakistan
engr.saifulislam19@gmail.com, kami zeb@yahoo.com, waqudn@pusan.ac.kr,
imrankhan@pusan.ac.kr, engrishfaq1994@gmail.com, zahid.ullah@skt.umt.edu.pk, heeje@pusan.ac.kr
Abstract—This paper presents a newly designed fault-ride-
through (FRT) scheme i.e. bridge-type fault-current limiter
(BFCL) for Grid-Tied photovoltaic system (PVS) to optimize
unbalance fault variables. A 100 kW three-phase Grid-Tied
MATLAB/Simulink model is used to analyze the system response
during unbalance conditions. The simulation results of designed
FRT scheme are critically compared with conventionally adopted
FRT scheme i.e. crowbar circuitry. However, for inverter control
proportional integrator (PI) controller is used. Moreover, the
analysis is carried out for faults at point of common-coupling
(PCC) as well as 5-km away from PCC. The obtained simu-
lated results of PI controller with well-designed FRT scheme
authenticates stable, minimum oscillation, ripples free, robust
and fast performance for unbalance fault variables as compared
to previous work.
Index Terms—Grid-Tied PV system, PI controller, FRT
scheme, LVRT capability, BFCL scheme.
I. INTRODUCTION
The adoption of renewable energy resources (RERs) i.e.
wind and photovoltaic (PV) energy can significantly reduce
the greenhouse gas emissions [1]. The depletion of fossil fuels
has enforced the world to explore alternative resources to
meet the high demand of electrical energy. Although, many
alternative ways of energy have been discovered but solar
PV and wind are considered as main renewable resources of
electrical energy [2]. To achieve the regulated output, a control
block is employed to PV system. Solar cells give DC output
power when exposed to sun radiations, needs to be converted
into AC signal through electronic switches to deliver power to
AC utility grid [3]. Usually, voltage-source inverters (VSI) are
employed to invert PV generated DC power as it comprises
two control loops i.e. voltage and current. Moreover, VSI is
simple, reliable, stable and having fast response.
The susceptibility of electrical power system toward grid
faults is increased due to high growth in PV generated power
domain. In the result new grid requirements are introduced to
enhance the stability of system during fault conditions [4]–[7].
One of these grid requirements is low-voltage ride-through
(LVRT) capability [8], which requires insertion of reactive
current during abnormal grid conditions and stay connected
for short time. The response of Grid-Tied VSI and PV module
can be highly affected by voltage sag due to high harmonics
and ripples in electrical parameters. Until now, conventionally
adopted crowbar is used as FRT scheme to minimize fault
current at inverter although it is not following the requirements
of grid connection and utility to retain normal operation [9].
To overcome the above-mentioned problem, a navel fault-
ride-through (FRT) scheme i.e. bridge-type fault-current lim-
iter (BFCL) is designed to optimally restrain the fault param-
eters of three-phase Grid-Tied PVS under grid requirements.
II. PROPOSED MODEL
A detailed model of 3-phase Grid-Tied PVS having 100kW
power capacity is used from Matlab/Simulink examples. This
100kW PV model include some fundamental arrangements
like DC to DC boost converter and three-phase three-level
voltage source inverter (VSI) and filter to insert PV power to
110kV utility grid through 20kV distribution unit as shown
by Figure 1. A ”330 SunPower SPR-305-WHT” photovoltaic
module is used which consists 66 strings have 5 series con-
nected panels; these strings are then connected in parallel.
The inputs for PV module are sun irradiance in W/m2 and
cell temperature in °C. The maximum output voltage of PV
module is boosted to 500V from 273V with the help of
DC to DC boost converter having 5KHz frequency [?]. To
achieve maximum power point in DC to DC boost converter
the flowchart of incremental conductance is adopted [10]. To
achieve maximum power from photovoltaic array incremental
conductance flowchart updates the duty cycle of boost con-
verter for the sake of required output voltage. The VSI having
2KHz frequency is employed to convert the dc-link voltage
(500V) to alternating 260Vac. Through two loops of three-
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Fig. 1. Designed model of Grid-Tied PV
phase VSI the dc-link voltage is controlled for interconnection
with grid. The internal loop controls the real (Id) and reactive
(Iq) components of utility grid current as depicted in Figure 2.
Though, the external loop is for maintaining the dc-link
voltage to +/- 250V through two split capacitors as total
reference dc line voltage is maintained to 500V. Moreover,
the reactive current component i.e. Iq is kept equal to zero to
achieve unity power factor. The external or current controller
outputs in the d-q frame i.e. Vd and Vq are converted into
three modulated waveforms, then these modulated signals are
used by pulse width modulation (PWM) generator. The overall
parameters of the proposed model are given by Table I.
The designer given parameters of PV module used by
proposed system are voltage and current at maximum power
point (Vmp, Imp), short-circuit current (Isc), no-load voltage
(Voc) and temperature coefﬁcient. For a speciﬁc temperature
of PV cell Imp, Vmp, Isc and Voc are adjusted by changing
saturation current of diode (Isat), small resistance in series
(Rse), high resistance in parallel (Rpr) and photo-generated
current (Iph) for a single PV module while considering quality
factor (Qd) of diode for a semiconductor.
Equation (1) below gives the diode characteristics of PV
module:
Ic = Iph −

Isat

exp

V + IcRse
VT

− 1

+
V + IcRse
Rpr

(1)
Here, Ic is the Output current (A) of PV cell, Isat is the
Diode’s reverse saturation current equal to 5.261e − 09 A, Ipt
is the Insulation current = 5.956A, Rse = 0.0832 ohms, Rpr =
8191 ohms, and VT is the Thermal voltage derived by equation
(2) below:
VT =
KT
qQdNprNse
(2)
Here, K is the Boltzmann constant (1.3805 × 10−23
j/k), T
is the Absolute Temperature = 25 °C, Qd is the Quality factor
of the diode= 1.252, q is the Electronic charge (1.602×10−19
C), Npr is the Number of strings in parallel = 66, and Nse
are the cells in series/string= 5.
III. CONTROL AND FRT STRATEGY
In the recent decade, different types inverter control schemes
have been presented due the various Grid-Tied PV inverter
topologies. The control scheme block in PVS is responsible to
handle the electrical variable such as real and reactive current,
synchronism of the grid, maintain power factor to unity and
positive sequence. The newly designed strategy here is the
proportional-controller (PI) in combination with bridge-type
fault-current limiter (BFCL). The designed strategy can take
care of PVS during both normal and abnormal conditions.
A. Proportional-Controller (PI)
The control scheme i.e. PI, for grid connected VSI is
illustrated by Figure 2. The external loop gives current outputs

Fig. 2. Control scheme for the Grid-Tied VSI
as Id component and Iq component of current in synchronous
d-q frame. Due to simple control and measurements d-q
frame is used instead of natural frame. However, the external
controller‘s one output i.e. Iq is set to zero to obtain unity
power factor. Considering the internal loop which is also
known as current control loop gives output voltage in the form
of d-q as Vd and Vq. These signals are then converted in three
modulating waveforms that are further used by pulse-width-
modulation generator.
B. Fault Ride Through (FRT) Scheme
All over the world a large amount of money is being in-
vested for installation and reliable operation of power systems.
So, every possible effort is carrying out to protect the power
system during any abnormal condition. Therefore, different
FRT schemes are designed to minimize the amplitude of fault
current and enhance voltage during any abnormal situations
for the reliable and stable operation of the system. This article
presents a new and efﬁcient FRT scheme as BFCL to restrict
the LVRT capability of the PVS within grid requirements.
Additionally, the behavior of the conventionally used crow-
bar scheme is carried out under comparison to justify the
efﬁcient response of our proposed BFCL scheme.
1) Crowbar Scheme: The conventionally used crowbar cir-
cuit includes pure resistance in the path of fault current [11].
The crowbar strategy consists two power electronic switches
that operates on the basis fault detection mechanism as by
Figure 3. Only one switch will be on at a time i.e. with fault
or without fault switch depending of the system condition, is it
a fault or not? When the fault detection mechanism senses any
fault so instantly the ”with fault switch” is triggered to include
resistance the fault current and simultaneously ”without fault
switch” goes off. These two switches are electronic DIAC
switches used to conduct for both positive and negative half
cycles of AC signal.
2) Bridge-Type Fault-Current Limiters (BFCL) Scheme:
The fault variables are optimized to approximately nominal
values with minimum ripples through BFCL scheme.
Fig. 3. Crowbar Scheme
Fig. 4. BFCL Scheme

The BFCL scheme is the combination of two ways i.e. shunt
path and bridge path [12]. The bridge path is followed by
current in normal i.e. without fault condition, which is com-
prised of four bridge diodes (D1 to D4) responsible to pass the
positive and negative cycle of alternating variables. The small
dc reactor (Ldc) comes in shunt with a freewheeling diode
(Df ) are then connected in series with a semiconductor switch,
as shown by Figure 4. A negligible amount of resistance is
added in series as inheritance resistance of the inductor i.e.
(Rdc). Moreover, the shunt path is a branch of resistance (Rsh)
in series with inductance (Lsh). This path is used by the power
flow during abnormal conditions, which is the in shunt with
the normal path (bridge path) [13], [14].
IV. RESULTS AND DISCUSSION
The environment used for application of 100-kW Grid-Tied
photovoltaic system is Matlab/Simulink. The behavior of fault
variables for the PV system is simulated and investigated for
designed PI controller and BFCL as FRT scheme. The effects
of fault variables are analyzed at two different locations i.e. at
PCC and at 5-km of from PCC. Additionally, for verification
of the proposed FRT scheme, a comparative analysis is also
carried out with conventionally adopted FRT scheme i.e.
crowbar.
A. Unbalance Faults at PCC
Unbalance faults are put at 0.1s and cleared at 0.25s at
PCC. Performance of the designed scheme in comparison with
conventionally adopted schemes is elaborated below.
The dc-link voltage behavior during the single phase-to-
ground (P-G) and phase-to-phase (P-P) faults are shown by
Figure 5. The newly designed BFCL in coordination with PI
as inverter controller (PI+BFCL) gives a robust and optimized
performance throughout the fault time. The proposed strategy
gives less spikes during fault occurring and clearing time.
It also results in a minimum overshoot and undershoot as
compared to crowbar-based approaches. Although, the double
phase fault results in severe rise as compared to a single-phase
to ground fault. However, the behavior of the proposed scheme
gives robustness for the phase to phase fault. Moreover, at
the start of simulations, PI+BFCL results with low transients,
comparatively.
The inverter‘s real (Id) and reactive (Iq) current compo-
nent responses in the dc frame i.e., d-q frame is depicted
by Figure 6. During both unbalanced faults, the proposed
designed approach authenticates the minimum oscillations and
low surges in currents. This is because of the inductive effect
of proposed BFCL as compared to the pure resistance-based
crowbar. Although, during phase-phase fault proposed scheme
shows an optimum response as, it is a severe fault compared
to P-G fault. Moreover, as mentioned before, the reactive (Iq)
component is kept at zero for the sake of unity power factor
achievement. However, the distortions in Iq component of
current with proposed PI+BFCL, which shows little spikes for
both P-G and P-P faults, as by in Figure (c) and (f).
(a)
(b)
Fig. 5. DC-link voltage behavior for P-G (a) and P-P (b) at PCC.
B. Unbalance Faults at 5-km Distance
The simulated variables at distance of 5-km from PCC are
less more affected than the fault type. The little variations with
respect to distance are because of the inclusion of 5-km extra
line resistance. A negligible rise in voltage and a decrease in
currents are resulted even though the overall behavior is the
same as in PCC. However, for convenience, Dc-link voltage
and reactive current behavior during the P-G and P-P faults
at the 5-km from PCC is given by Figure 7. Which give
negligible variations during fault due to the line impedance.
V. CONCLUSION
This paper concentrates on the improvement of LVRT
capability of the Grid-Tied PV system, referred to the existing
grid codes. The designed BFCL in combination with PI
control (PI+BFCL) is affectively tested and compared with a
conventionally using crowbar circuitry. A prominent response
is achieved at both locations i.e. at PCC and at 5-km away
from PCC. Additionally, it is observed that the parameters of
grid connected three-phase PVS are less affected with respect
to fault distance and more with respect to fault type.
The designed scheme authenticates robust, smooth and a
fault tolerant behavior of PVS under both normal and fault
conditions. Soon, the designed strategy will be experimentally
validated by using the Delfino Texas Instrument or DSP
(TMS3200F28335) control boards.

(a) (b)
(c) (d)
(e) (f)
Fig. 6. Active (Id), reactive (Iq) currents in (a, b, c) and (d, e, f) during P-G and P-P fault, respectively.
TABLE I
MODEL PARAMETERS.
Parameters Values
Switching-frequency of inverter 2 kHz
Full -load current of grid 2.94 A
Algorithm used for MPPT Incremental conductance
Temperature 25°C
Sun irradiance for PV 1000 (W/m2)
PV power 100.6 kW
Full-Load current of PV 364 A
Operating-frequency 50 Hz
converter frequency 5 kHz
Link-voltage (Vdc) 500 V
Grid-voltage 20 KV
Choke-impedance (R, L) 2 × 10−3 ohm, 2.5 × 10−6 H
PV module output voltage 273 V (L-L, rms)
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