Apresentação da nova linha de microcontroladores Cortex-M da Microchip e o framework MCC Harmony. O principal foco será nova linha PIC32CX é voltada para aplicações de conectividade e segurança. Apresentando como implementar uma comunicação Ethernet TCP com segurança.

1. A Leading Provider of Smart, Connected and Secure Embedded Control Solutions
MicrochipPropietaryand Confidential

2. A Leading Provider of Smart, Connected and Secure Embedded Control Solutions
MCC Harmony using PIC32CX to
implement TCP/IP application
Ricardo Seiti
June 27 2023
MicrochipPropietaryand Confidential

3. 3
Class Objectives
When you walk out of this class you will be able to…
• Understand the fundamentals of TCP/IP and how applications use them to
create TCP/IP connections.
• Understanding how to use MCC Harmony Framework to implement TCP/IP
application using PIC32CX
• Learn about new PIC32CX family

4. 4
Agenda
Part 1: TCP/IP Fundamentals as a Refresher
Part 2: MPLAB® Harmony TCP/IP Stack Overview
• TCP/IP Layers and Features
• Network Interface Options
• Processor Requirements
Part 3: Using the MCC Harmony TCP/IP Stack
Part 4: PIC32CX family and new microcontrollers with Ethernet MAC

5. 5
Part 1: TCP/IP Fundamentals as a
Refresher
Five Layer Model and Applications
TCP vs UDP

6. 6
Agenda
Five Layer Model and Applications
• Five Layer Software Model
• Application Layer
• Transport Layer
• Network Layer
• Data Link Layer
• Physical Layer
• TCP vs. UDP
• TCP/IP Applications
•DNS, NBNS, SNTP, DHCP, SNMP, Telnet, SMTP, HTTP
Application Layer
Transport Layer (TCP/UDP)
Network Layer (IP)
Data Link Layer (MAC)
Physical Layer
Network
Host

7. 7
What Does Each Layer Do?
Network Layer (IP)
Application Layer
Data Link Layer (MAC)
Transport Layer (TCP/UDP)
The Data Link layer is responsible for creating the
frames that move across the network.
The Network layer is responsible for creating the
packets that move across the network.
The Transport layer establishes the connection
between applications on different hosts.
The Application layer is the group of applications
requiring network communications.
The Physical layer is the transceiver that drives
the signals on the network.
Physical Layer
Transfers packets with
virtual (IP) addresses
Transfers frames with
physical (MAC) addresses
Establishes connections
with remote host
Transmits and
receives bits
Web Server
Web
Browser
Generates the data and
requests connections
Host A Host B

8. 8
Application Layer
(Layer 5)
• Layer 5 is where TCP/IP applications live
• Your application typically interacts with
these applications
Network Host
PHY
MAC
IP
TCP
NBNS
DNS
SNTP
DHCP
Telnet
SMTP
HTTP
SNMP
TFTP
UDP

9. 9
Transport Layer
(Layer 4)
• Connects to remote hosts
using either:
• TCP (Transfer Control Protocol)
• UDP (User Datagram protocol)
• Delivers data to and from
applications
• Assigns port numbers to
processes
• running in applications
Network Host
PHY
MAC
IP
TCP
NBNS
DNS
SNTP
DHCP
Telnet
SMTP
HTTP
SNMP
TFTP
UDP

10. 10
29 June 2023 Microchip Technology Inc. and its subsidiaries
©
Network Layer
(Layer 3)
• Also known as the Internet layer
• Adds a header to the data received from the
transport layer
• contains the source and destination IP
addresses
• Creates IP Packets
Network Host
PHY
MAC
IP
TCP
NBNS
DNS
SNTP
DHCP
Telnet
SMTP
HTTP
SNMP
TFTP
UDP
An IP address is 32
bits and looks like this:
192.168.1.101

11. 11
Network Host
PHY
MAC
IP
A MAC address is 48
bits and looks like this:
F0:DE:F1:1E:E8:93
TCP
NBNS
DNS
SNTP
DHCP
Telnet
SMTP
HTTP
SNMP
TFTP
UDP
Data Link Layer
(Layer 2)
• Uses a Media Access Controller to
generate frames
• Adds a header to the packet
• Source and destination MAC addresses
• Every host has at least one MAC
address

12. 12
Network Host
PHY
MAC
IP
TCP
NBNS
DNS
SNTP
DHCP
Telnet
SMTP
HTTP
SNMP
TFTP
UDP
Physical Layer
(Layer 1)
• Sends and receives signals on the
physical wire or antenna
• Responsible for moving bits
• Found at the end of every network
interface

13. 13
Layer Name Protocol
Protocol
Data Unit
Layer #
5 Application
Transport
4
3
2
Network or
Internet
Data Link Ethernet, Wi-Fi
IP
TCP/UDP
HTTP, SMTP, etc…
Frames
Packets
Segments/
Datagrams
Messages
1 Physical 10 Base T, 802.11 Bits
Addressing
MAC Address
IP Address
Port #s
n/a
n/a
TCP/IP Protocol Stack
(Terminology Reference)

14. 14
Application Description
DHCP
DNS
NBNS
SMTP
HTTP
SNMP
Telnet
TFTP
SNTP
NetBIOS Name Service translates local host names to IP addresses
Domain Name System translates website names to IP addresses
Dynamic Host Configuration Protocol assigns IP addresses
Simple Mail Transfer Protocol sends email messages
Hypertext Transfer Protocol used to transfer web pages
Bi-directional text communication via a terminal application
Simple Network Management Protocol manages network devices
Trivial File Transfer Protocol used to transfer small amounts of data
Simple Network Time Protocol provides time of day
Common TCP/IP Applications

15. 15
Part 2: MPLAB® Harmony TCP/IP
Stack Overview
• TCP/IP Layers and Features
• Network Interface Options
• Processor Requirements

16. 16
MPLAB® Harmony
TCP/IP Stack
Provides a foundation for embedded network applications by
handling most of the interaction required between the physical
network interface and your application.
Fully Implemented and supported by Microchip Engineers.
Source code is included with the MPLAB® Harmony Distribution.
Cost: Free*
*MPLAB Harmony is only licensed for use on Microchip Microcontrollers

17. 17
Architecture
PIC32 and SAM
Microcontrollers
Ethernet Network
Interface
WiFi Network
Interface

18. 18
Application Layer – OSI Layer 5, 6 and 7
PIC32/SAM MCU running MPLAB® Harmony TCP/IP Stack

19. 20
Services and Applications – OSI Layer 5, 6 and 7
PIC32/SAM MCU running MPLAB® Harmony TCP/IP Stack

20. 22
Encryption Provider –OSI Layer 5
PIC32/SAM MCU running MPLAB® Harmony TCP/IP Stack

21. 24
Transport Layer – OSI Layer 4
PIC32/SAM MCU running MPLAB® Harmony TCP/IP Stack

22. 26
Internet Layer – OSI Layer 3
PIC32/SAM MCU running MPLAB® Harmony TCP/IP Stack

23. 29
Network Interface Layer – OSI Layers 1 and 2
PIC32/SAM MCU running MPLAB® Harmony TCP/IP Stack

24. 31
Network Interface Options
PIC32CX PIC32/SAM PIC32/SAM

25. 32
Supported Interface Devices
• Ethernet PHYs
• Only used with PIC32/SAM devices that have internal Ethernet MAC Peripheral
• PHY Only: LAN8740, KSZ8081, KSZ8061
• PHY + Switch: LAN9303, KSZ8863
• Standalone Ethernet Link Controllers
• ENC28J60
• ENCx24J600 LAN8650 (10BASE-T1S)
• Wi-Fi®
• ATWINC1500
• WFI32

26. 33
Part 3: Using the MCC Harmony TCP/IP
Stack

27. 34
MHC

28. 35

29. 36

30. 37

31. 38

32. 39

33. 40

34. 41

35. 42
New PIC32CX family

36. 43
PIC32CX SG Cortex-M4 Family
• Target Markets:
• Automotive, Industrial, IoT/Secure Connectivity
• Optional SiP with TA100 Trust Anchor as Hardware
Security Module (HSM)
• Secure boot for code authentication
• Message authentication via MAC
• Trusted firmware updates
• Key management (TLS/Root-of-Trust)
• Pin Compatible with SAMD51/E5x
• AEC Q100 Grade 1 (125C)
• SAE/ISO 21434 certification planned.
• AUTOSAR Support available.
• JIL High certification planned.
• Released
Advanced Security and Connectivity
Cortex M4 Core
FPU, DSP
120 MHz
1Mbyte Flash
256byte RAM
Advanced Crypto Engine (AES,
SHA, ECC, RSA, DSA)
Secure Boot
Tamper Protection
TA100 Trust Anchor HSM SIP
(Optional)
10/100 Ethernet MAC
FS USB (1)
CAN-FD (2)
SERCOM (8)
I2S (1), QSPI (1)
SDIO (2)
12b ADC, 1Msps, 32 Ch
12b DAC, 1Msps, 2 ch
PTC

37. 44
PIC32CXSGFamily – Overview (SG41/SG60/SG61)
• High Throughput
• Cortex-M4 with FPU
• 4kByte Instruction Cache or TCM
• Advanced Analog, Communication and Peripherals
• 2x12-bit 1Msps ADC, 12-bit 1Msps DAC
• ISO CAN FD & 10/100 Ethernet
• Up to 2x SDIO and 1x QSPI
• UP to 8 SERCOM *(I2C, USART, SPI,ISO7816,LIN,RS485)
• Security
• Crypto/Tamper as opposite
• Memory lock/debug disable
• ECC on Flash/SRAM and CRC-32
• Integrated Secure Element HSM (HSM)
• AEC-Q100 Grade 1
• 100,128 Pin TQFP ,100 Pin BGA
Features SG60/SG61 SG41
Frequency 120 MHz 120 MHz
Flash (Dual Bank w/ RWW) 1MB 1MB
SRAM 256KB 256KB
SERCOM Up to 7 Up to 8
Dual Voltage GPIO 1.8V and 3.3V 1.8V and 3.3V
QSPI / SDIO 1 / 2 1 / 2
FS USB Host & Device (with
PHY)
1 1
ISO CAN FD 2 2
10/100 Ethernet 1 1
Peripheral Touch Controller
Self, Mutual, 16 x
16 ch
Self, Mutual, 16 x
16 ch
I2S 1 1
ADC (12 bit, 1Msps) 2x16 2x16
DAC (12 bit, 1Msps) 2 2
Timer / TCC 8 / 5 8 / 5
Security/Crypto MCU
TRNG, AES256,
SHA1/244/256,
ECC 1k, RSA, DSA,
Tamper Detection
TRNG, AES256,
SHA1/244/256,
ECC 1k, RSA, DSA,
Tamper Detection
Secure Boot Yes (SG61) Yes
SIP W Integrated Secure
Element (HSM)
Yes NO
Features
PIC32CX
SG41
PIC32CX
SG60
PIC32CX
SG61
Secure Boot Through
OTP Flash
Yes No Yes
Secure Element for
Secure Key Storage
NO Yes Yes
Pkgs 128 TQFP
100,128 TQFP
120 BGA
100,128 TQFP
120 BGA
Distribution
Direct,
Disti,All
NDA ONLY NDA ONLY

38. 45
PIC32CX SG Target Applications
Automotive, IOT, Industrial
45
Automotive (EVITA Compliant Secure Systems, AUTOSAR,Secure
Key/Boot)
CAN Authentication
EV Battery Management
AVAS (Acoustic Vehicle Alert System)
IOT (Secure Update/Secure Connectivity/ Immutable Boot/Key
Storage)
Cloud Secure Applications
Secure Gateway/Nodes
Industrial/Appliance: (Firmware Validation / Secure Monitoring)
•Data Centers Remote Monitoring
•Gaming
•Industrial Monitoring/connectivity

39. 46
PIC32CX SG41(EV06X38A )/SG61 (EV09H35A)Curiosity Ultra Board
Features
• PIC32CX1025SG41128 or PIC32CX1025SG61128 microcontrollers
• Embedded debugger (PKoB4)
• – Programming and debugging
• – Virtual COM port (CDC)
• USB powered
Communication Interfaces
• Ethernet 10/100Mbps
– RMII Interface with modular PHY Header
• USB interface, Host or Device
• Two CAN interfaces with on-board transceivers
Extension Headers
• 64 Mbit Quad SPI Flash
• AT24MAC402 Serial EEPROM with EUI-48™ MAC address
• SD/SDIO card connector
• DAC Output Header
• mikroBUS header connector
• Two MCHP extension headers
• Arduino Uno header connectors
PIC32CX SG61(EV09H35A)
PIC32CX SG41(EV06X38A)

40. 47
32-Bit Microcontroller Portfolio
Ethernet Support (current)
Entry Level 32bit MCU
Performance
Mid Range Performance 32bit MCU
High Performance 32bit MCU
Features
In
Production
PIC32MX5/6/7
105 DMIPS
64-512KB / 16-128KB
USB, Ethernet, CAN
PIC32MZ EF FPU
330/415 DMIPS, FPU
512-2048KB / 512KB
HS USB, CAN,
Ethernet, Crypto
PIC32MZ DA
330 DMIPS
512K-2MB/32MB DRAM
HS USB, CAN,Ethernet,
Graphics, 12b ADC
SAMD51/E5x
180 DMIPS, M4F
1024KB/256KB/8KB EE
12b ADC/DAC, USB,
Crypto, CAN-FD, Ether
SAMS70/E70
300MHz/600 DMIPS
512KB – 2MB / 384KB
CAN-FD.HS USB,
Crypto, Ethernet
SAMV70/V71
300MHz, M7
512KB – 2MB / 384 KB
Auto, HS USB, CAN-
FD, Crypto, Ethernet
SAM4S/4E
150 DMIPS, M4
128KB-2MB / 64-160KB
USB, CAN(2), Ethernet,
12b ADC, 12B DAC

41. 48
PIC32CX SG61 (SIP)
150 DMIPS, M4F
1024KB/256KB/8KB EE
48 – 120 pins
12b ADC/DAC, USB,
TA100, SB, CAN-FD, Ether
SAMD5x/E5x and PIC32CK/CX Family
Mid Range Cortex M4F/M33 In Development
Production
Time
SAMD51/E5x
150 DMIPS, M4F
1024KB/256KB/8KB EE
48 – 120 pins
12b ADC/DAC, USB,
Crypto, CAN-FD, Ether
PIC32CK
180 DMIPS, M33
2048KB/512KB/128K HSM
64 – 144 pins
12b ADC/DAC, USB, HSM,
CAN-FD(2), Ether
Features/Memory/Performance
Secure Boot
Higher Memory, Higher
Security(HSM) with
Trustzone
PIC32CX SG41
150 DMIPS, M4F
1024KB/256KB/8KB EE
48 – 120 pins
12b ADC/DAC, USB,
Crypto, SB, CAN-FD, Ether
Secure Boot
Enhanced
Security

42. 49
Q&A
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