This paper presents a new asymmetrical singlephase multilevel inverter topology capable of producing ninelevel output voltage with reduce device counts. In order to obtain the desired output voltage, dc sources are connected in all the combination of addition and subtraction through different switches. Proposed topology results in reduction of dc source, switch counts, losses, cost and size of the inverter. Comparison between the existing topologies shows that the proposed topology yields less component counts. Proposed topology is modeled and simulated using Matlab-Simulink software in order to verify the performance and feasibility of the circuit. A low frequency switching strategy is also proposed in this work. The results show that the proposed topology is capable to produce a nine-level output voltage with less number of component counts and acceptable harmonic distortion content.

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Nine-level Asymmetrical Single Phase Multilevel
Inverter Topology with Low switching frequency and
Reduce device counts
ABSTRACT:
This paper presents a new asymmetrical singlephase multilevel inverter topology capable of
producing ninelevel output voltage with reduce device counts. In order to obtain the desired
output voltage, dc sources are connected in all the combination of addition and subtraction
through different switches. Proposed topology results in reduction of dc source, switch counts,
losses, cost and size of the inverter. Comparison between the existing topologies shows that the
proposed topology yields less component counts. Proposed topology is modeled and simulated
using Matlab-Simulink software in order to verify the performance and feasibility of the circuit.
A low frequency switching strategy is also proposed in this work. The results show that the
proposed topology is capable to produce a nine-level output voltage with less number of
component counts and acceptable harmonic distortion content.
KEYWORDS:
1. Multilevel inverter
2. Asymmetrical
3. Total Harmonic Distortion (THD)
4. Low-frequency switching
SOFTWARE: MATLAB/SIMULINK

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BLOCK DIAGRAM:
Fig. 1. Proposed nine level inverter topology.

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EXPECTED SIMULATION RESULTS:
Fig. 2. Simulation results for proposed nine level inverter topology; (a)
and (b) are switching pulses, (c) Level generator output voltage.

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Fig. 3. Simulation Output results at 50Hz fundamental frequency for R = 150ohm, L= 240, P.F = 0.9
Fig. 4. Simulation Output results at 50Hz fundamental frequency for R =150ohm, L= 240, P.F = 0.9

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CONCLUSION:
In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is
capable of producing nine-level output voltage with reduce device counts. It can be used in
medium and high power application with unequal dc sources. Different modes of operation are
discussed in detail. On the bases of device counts, the proposed topology is compared with
conventional as well as other asymmetrical nine-level inverter topologies presented in literature.
Comparative study shows that, for nine level output, the proposed topology requires lesser
component counts then the conventional and other topologies. Proposed circuit is modeled in
Matlab/Simulink environment. Results obtained shows that topology works properly. Detailed
Simulation analysis is carried out. THD obtained in the output voltage is 8.95% whereas the each
harmonic order is < 5%, satisfies harmonic Standard (IEEE-519).
REFERENCES:
[1] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A.M. Prats and M. A.
Perez, “Multilevel Converters: An Enabling Technology for High-Power Applications”, IEEE
Proceeding, Vol 97, No. 11, pp.1786 – 1817, November 2009.
[2] J. R. Espinoza, “Inverter”, Power Electronics Handbook, M. H. Rashid, Ed. New York, NY,
USA: Elsevier, 2001,pp. 225 -269.
[3] L. M. Tolbert and T. G. Habetler, “Novel multilevel inverter carrierbased PWM method”,
IEEE Transactions on Indsutrial Apllications”, Vol. 35, No. 5, pp. 1098-1107, September 1999.
[4] S. Debnath, J. Qin, B. Bahrani, M. Saeedifard and P. Barbosa, “Operation, Control and
Applications of the Modular Multilevel Converter: A Review”, IEEE Transactions on Power
Electronics, Vol. 30, No. 1, pp. 37-53, January 2015.

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[5] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. C. Portillo and M. A. M. Prats, “The
Age of Multilevel Converters Arrives”, IEEE Industrial Electronics magazine, Vol. 2, No. 2 pp.
28-39, June 2008.