dopted for both mobile phone and consumer electronics applications, Fan-Out Wafer Level Packaging (FO-WLP) is the most innovative, advanced packaging technology today. Analysing patent status is the key to understanding the business situation. ANALYSIS OF THE PATENT PORTFOLIO’S TECHNICAL CONTENT After several years of specific analysis for customers, Yole Développement has decided to publish its first analysis concerning the technical contents of patents. This first study focuses on the FO-WLP area, a new packaging technology which is changing the patent landscape for semiconductor packaging across a wide range of application spaces. Yole Développement has developed a specific methodology to conduct this analysis (described below), mixing our technical and business knowledge with classical access to the patent database... More information on that report at http://www.i-micronews.com/advanced-packaging-report/product/fowlp-patent-analysis.html

1. © 2012
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FOWLP Patent Analysis
Report Sample
July 2012

2. © 2012• 2
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Full Table of Content of the Report
•FOWLP Roadmap .....................................................................................................
3
•Methodology for patent screening and analysis ...................................................
4
•IP landscape overview .............................................................................................
13
•List of all assignees .................................................................................................
32
•Analysis of FOWLP patents filed by key players ..................................................
39
- Infineon ....................................................................................................................................................
41
- ACE ..........................................................................................................................................................
88
- Tessera ....................................................................................................................................................
104
- Samsung .................................................................................................................................................
116
- Freescale .................................................................................................................................................
119
- Statschippac ...........................................................................................................................................
137
- ASE ...........................................................................................................................................................
150
- Amkor ......................................................................................................................................................
162
- STMicroelectronics ................................................................................................................................
175
•Key patents for FOWLP ...........................................................................................
189
•Cross link analysis ...................................................................................................
223
•Conclusion ................................................................................................................
228
•Appendix ...................................................................................................................
232

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FOWLP
1st generation
WL CSP
FC BGA
WB BGA
MATURE tech
EMERGING tech
FUTURE tech
(> 2000 )
(> 2008 - 2011)
(> 2012 - 2016)
FO MCP
FOSiP & Stacked die
FO PiP
RF connectivity, PMU, Analog
RF Transceiver, Baseband
PMU
 Digital Baseband SOC
 Multi-band RF Transceiver
 RF Connectivity combos
 PMU combos
 Specific Analog IC & Sensors
Package stacking within the FOWLP package.
FO SiP and other architectures in which dies are stacked within the FO mold
Side by side integration within the package  2D integration
FO PoP
FO package stacking. The 2 packages can be tested individually. …
2nd generation FOWLP
1st generation FOWLP
FOWLP Roadmap

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Methodology for patent screening and analysis

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Methodology - Completed Steps
Step
Task
Output
Step I - Searching
Based on the expected output, a list of keywords was generated to prepare a comprehensive search strategy that covers all the aspects pertinent to the project.
Further, this search strategy was used to perform patent searches on Questel Orbit patent database. The search results obtained were reduced to one member per patent family prior to analysis.
A list of patents for screening and analysis
Step II - Detailed Patent Analysis
During this step, the patents were screened and then divided based on their key-focus areas and were marked as relevant, related and non-relevant. The final set of patents hence obtained were further screened and analyzed based on their Full Specifications and relevant information associated with each patent was captured as required.
A list of relevant and related patents categorized in to categories as required
Step III - Additional Information
For the set of relevant patents, information related to Legal Status, Indicative Expiry Dates, etc were obtained.
List of all Relevant and Related patents along with required legal status details
Step IV - Deliverable Preparation
All the data obtained was compiled MS Excel document.
Deliverable of Analysis
Methodology for patent screening and classification Phase I

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Methodology for patent screening, classification and analysis Phase I and phase II
Keywords and term-set definition
Patent screening and analysis
Related
Relevant
Non relevant
Detailled analysis
Patent classification
Taxonomy
Fine search using IPC classes
Technological segmentation
•The screening was performed for US, EP, WO, JP translated English full text, GB, DE, FR, CN+TW+KR translated English full text using English + French + German keywords.
Segmentation improvement during analysis
Phase II
Phase I

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FOWLP IP study: project assumptions
•Assumptions
–Analysis for jurisdictions such as CN, JP, KR and TW have been mostly done on the basis of Title and Abstract (unless claims were available for these cases).
–MicroPatent and Questel-Orbit FAMPAT databases were used for conducting all the keyword searches.
–The term 'Patent' has been used as a collective term for Patents and Published Applications.
–Searches were conducted on October 1, 2011 hence patents published/granted after this date will not be available in the deliverable.
–Only one member per family has been analyzed.
–Probable Expiry Date has been calculated by adding 20 years to the effective filing date. For WO applications, expiry dates were calculated by adding 31 months to the earliest priority date.
–For Legal Status of EP/WO Patents/ Published Applications EPO Register Plus has been used and for US Patents/ Published Applications USPTO PAIR has been used. For other patents, information has been captured from their respective national registers wherever available.
• Data Sources
–For Bibliographic Data (including title, abstract and English claims but excluding Legal Status):
MicroPatent
Questel-Orbit FAMPAT database
–For Legal Status
EP/WO Patents/ Published Applications: EPO Register Plus
US Patents/ Published Applications: USPTO PAIR

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Search Strategy for FOWLP IP study Keywords and Term Sets
Keyword Based Search
Term Set
Keywords
FOWLP(Fan out wafer level Packaging) Term Set
((fanout or (fan adj out) or FO) same ((wafer*) near3 (level))) or (FOWLP OR WLFO)
RCP(redistributed chip package) Term Set
(((redistribut* or (re adj distribut*)) near2 ((wafer*) near3 (level))) same (packag*)) OR (RCP and (packag*))
eWLB(embedded wafer level ball grid array) Term set
((embed*) same ((wafer*) adj2 (level))) and ((ball*) near2 (grid*) near2 (array)) OR (eWLB)
Fan out Packaging Term Set
((fanout or (fan adj out)) near4 (packag*)) same (wafer* or chip*)
Embedded Die Fan Out Area Term Set
((embedd* or encapsulat) near (die)) and ((fanout or (fan adj out)) near (area or zone))
Semiconductor/ Wafer Term Set
((semiconductor or (semi adj conduct*) or wafer* or chip*))
Packaging Term Set
(packag*)
IPC Term Set for Semi Conductor Packaging
H01L002156T or H01L002300C6B17S or H01L002331H2B or H01L002300C2H or H01L0021683T (please see appendix for IPC class definition)

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Search Strategy for FOWLP IP study
S.No.
Search Strategy
No. of Results
1
(FOWLP Term Set OR eWLB Term Set OR RCP Term Set OR Fan Out Packaging Term Set OR Embedded Die Fan Out Area Term Set) <in> Claims, Title and Abstract AND H* <in> Any Classifications
~ 90 patent families
2
(FOWLP Term Set OR eWLB Term Set OR RCP Term Set OR Fan Out Packaging Term Set OR Embedded Die Fan Out Area Term Set) <in> Full Patent Specs AND (Semiconductor/Wafer Term Set SAME Packaging Term Set) <in> Claims, Title and Abstract AND H* <in> Any Classifications
~ 630 patent families
3
(FOWLP Term Set OR eWLB Term Set OR RCP Term Set OR Fan Out Packaging Term Set OR Embedded Die Fan Out Area Term Set) <in> Full Patent Specs AND IPC Term Set for Semi Conductor Packaging <in> Any Classifications
~ 390 patent families
4
FOWLP Term Set OR eWLB Term Set OR RCP Term Set OR Fan Out Packaging Term Set OR Embedded Die Fan Out Area Term Set <in> Title, Abstract
~200 Patent families
Total
~1,050 Patent families
Glossary of Specific Search Operators Used
ADJn: Search for words in the same sentence and appearing after n words of the first word. If n is omitted, the number defaults to one.
NEARn: Search for words in the same sentence and appearing within n words of one another, but in either order. If n is omitted, the number defaults to one.
WITH: Search for words in the same sentence.
SAME: Search for words in the same paragraph.

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Overview of Patents Analyzed
•Total Patent Families Analyzed : 1026
 includes relevant, related and non-relevant patents
•Relevant Patent Families : 236
•Related Patent Families : 249
 Please see definition of relevant, related, and non related patents on next slides
 The number of relevant patents was updated between phase I and Phase II because some patents marked as relevant were not.
 Please note that all the next slides (IP landscape overview) have been updated

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Relevance Criteria (1/2)
•Relevant patents
–Patents describing eWLB, FOWLP, RCP or its modifications (in terms of structure, or chip placement, etc) which can be used for packaging purpose.
–Patents describing process of implementing eWLB, FOWLP, RCP and/or modifications in the steps thereof (e.g., method of introduction of semiconductor die, or method/ process of packaging semiconductors using eWLB, FOWLP or RCP).
–Patents describing enhancement in properties of semiconductor chips (such as conducting properties) packaged from eWLB, FOWLP, RCP or any other fan out packaging method.
–Patents belonging to the top assignees and relating to enhancement or improvements in wafer level packaging techniques.
•Related patents
–Patents describing packaged semiconductors and mentioning in one embodiment that the method using which they have been packaged could be eWLB, FOWLP, RCP or any other fan out packaging method.
–Patents describing general method/process of packaging semiconductor chips and mentioning that in one embodiment that this method can also be implemented with eWLB, FOWLP, RCP or any other fan out packaging method to optimize them further.
–For such patents main focus is not on eWLB, FOWLP, RCP or any other fan out packaging method but on semiconductor chips packaging broadly.

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Relevance Criteria (2/2)
•Non relevant patents
Patent focusing on any of the following aspects:
–Patents describing packaging techniques other than eWLB, FOWLP, RCP or any other fan out packaging method for packaging semiconductor chips.
–In nutshell, such patent do not focus on eWLB, FOWLP, RCP or any other fan out packaging method even in one embodiment and mentions eWLB, FOWLP, RCP or any other fan out packaging method in some other context and/or in background section.

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IP landscape overview
 Distribution of All Analyzed Patents
 Overall Filing Trend
 Important Assignees

14. © 2012• 14
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Top 10 patent assignees for FOWLP technologies
Yole Developpement © April 2012
•Main applications for FOWLP: baseband, RF, power management, analog…
•Top 10 assignees also includes several memory players (Samsung, Micron, Qimonda)
•There’s no memory product packaged with Fan Out technology today but it’s still a hot topic !
31
12
21
21
9
16
8
12
10
4
26
41
16
15
24
12
15
3
2
7
0
10
20
30
40
50
60
No. of Patents
Assignee
Top 10 patent assignees for FOWLP patents (relevant and related included)
Relevant
Related

15. © 2012• 15
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Recent assignees for FOWLP patents
2
4
1
1
2
2
7
1
2
1
1
1
2
2
4
1
1
2
1
2
3
2
1
Recent assignees for FOWLP patents (related and relevant included)
TSMC (TW)
STMICROELECTRONICS (FR- IT)
BROADCOM (USA)
NXP (NL)
XINTEC (TW)
ANALOG DEVICES (USA)
IMEC (B)
JCAP (CN)
MEDIATEK (TW)
2005
2006
2007
2008
2009
2010
Priority Years
•STMicroelectronics is the most active player among all the recent assignees
•Other recent assignees with only 2 families in the domain include: King Dragon International, Nepes, SMIC, Shinko, Toyota, Visera.
•All the players present here have strong activities and development in semiconductor packaging area
Yole Developpement © April 2012
Bubble size represent number of Patent Families
•List of assignees with filing only after 2004 and having at least 3 families.

16. © 2012 • 16
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Full
Process
Phase II: Company X’s patent mapping for FOWLP
2003
2004
2006
2007
2008
2010
2009
Contact pad
Die placement & carrier
Bonding/DB
RDL
Bumping
Encapsulation
Passivation
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
2005
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX

17. © 2012 • 17
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Phase II: New architectures using FOWLP technology Patent mapping
2006
2007
2008
2009
MCP
PoP
PiP
Stack
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
2001
2005
2010
US patent X
US patent X
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX
US patent XXX

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More slides from the report…

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Your contacts at Yole Développement
•To contact us
–Lionel Cadix, market analyst
cadix@yole.fr
+ 33 472 830 192
–Jérôme Baron, business unit manager
baron@yole.fr
+ 33 472 830 194
–Jean Christophe Eloy, president and CEO
eloy@yole.fr
+ 33 472 830182

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Yole Developpement Company Presentation

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Fields of research activity
•Yole Developpement is a market research and strategy consulting company, founded in 1998. We are involved in the following areas:
•Yole Développement has 25 full time analysts, with both technical and marketing/management background and operate worldwide since 1998
MEMS & Sensors
Photovoltaic
Advanced Packaging
Microfluidic
& Bio-tech
Power Electronics
LED & Compound Semi

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Patent analysis activity presentation
•Yole Développement has recently launched a brand new kind of services based on IP research
•In addition to standard patent research, our unique position in the market as well our analysts’ technical knowledge allow us today to provide powerful analysis in Advanced Packaging, LED, MEMS, Microfluidics, Power Electronics, Compound Semi and PV
•Based on a specific request in one of our field of activities, the following actions can be done:
–Patent research + statistical analysis
–Deep technological analysis
–Exploration of innovation fields free of IP (based on a unique tool developped at Yole and using CK – Concept/Knowledge – methodology)
•A clear link between existing patents, technologies, involved players and related supply chains is provided and enables our customers to fully understand their markets and accelerate innovation process

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Objectives of the IP studies
•In IP study, in-depth IP family screening as well as patented technological detail analysis and evolution of each family are performed
•Primary objectives of the studies
–Get a clear picture of patent landscape through the study of all screened IP families
–Technology analysis of patent families
–Historical evolution of patent families
•This brand new kind of study is made of 3 phases
Phase 1: Patent families identification and classification
Identify the patent families
Present the patent landscape
Present key players and top applicants
Phase 2 : Patent analysis - Analysis of all relevant patents
Technological segmentation of patents
Analysis of the leading patent applicants
Evolution of the technological solutions within patent families
Historical evolution of patent families
Key patent ranking and key claims identification
Cross linked analysis
Phase 3 : Exploration of innovation fields free of IP and disruptive innovation based on CK theory

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Global Methodology for IP studies
Phase II depends on Phase I results. Phase III depends on phase II results.

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YOLE’s research focus in the semiconductor packaging market
1970s
1980s
1990s
2000s
2010s
2020s
DIP
QFP
LCC
PGA
WL CSP
WB BGA
QFN
SOT / TSOP
FO WLP
FC BGA / CSP
SiP
PoP / PiP
2.5D interposer
3DIC
Embedded SiP
3D WLP
FO PoP
FO SiP
Heatsink
Thermal grease
Substrate
SBD
IGBT
Baseplate
MEMS Packaging
LED Packaging
Power module Packaging
Applicative
Packaging
 Moving to high performance, low cost, application driven packaging techniques
Advanced Packaging
 Moving to high- performance, high-density, low cost, collective wafer-level- packaging technique standards
Camera module Packaging

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Our Global Presence & Activity
Yole Inc.
Yole Développement Lyon (HQ).
Yole Europe
Yole Japan
30% of our activity is in North America
30% of our activity is in Asia
40% of our activity is in EU Countries
 katano@yole.fr
 perkins@yole.fr
 nyberg@yole.fr
Yole Taiwan
Yole Korea
 meiling.tsai@yole.com.tw
 yang@yole.fr