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Growth of advanced packaging - What make it so special? Presentation by Rozalia Beica Yole Developpement 2015

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SEMI conference: MEMS & packaging technologies enabling IoT - Advanced semiconductor technology conference

Rozalia Beica
Yole DeveloppementCTO
FROM TECHNOLOGIES TO MARKET

Published in: Technology
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Growth of advanced packaging - What make it so special? Presentation by Rozalia Beica Yole Developpement 2015

  1. 1. Copyrights © Yole Développement SA. All rights reserved. 1 1 YOLE DEVELOPPEMENT FROM TECHNOLOGIES TO MARKET July 30, 2015 Rozalia Beica Yole Developpement CTO beica@yole.fr COLLABORATION INNOVATION NEW PERSPECTIVES The Growth of Advanced Packaging. What Makes it So Special?
  2. 2. Copyrights © Yole Développement SA. All rights reserved. 2 2  Introduction Presentation Outline 2 Y O L E D E V E L O P P E M E N T 2 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T • Europea n Market  Market Drivers  AP Platforms  Future Growth  Conclusions
  3. 3. Copyrights © Yole Développement SA. All rights reserved. 3 3 YOLE DEVELOPPEMENT Introduction YOLE DEVELOPPEMENT FROM TECHNOLOGIES TO MARKET Founded in 1998 in Lyon, France Introduction
  4. 4. Copyrights © Yole Développement SA. All rights reserved. 4 4 Yole – A Group of Companies The company is involved in the following areas: From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Finance MEMS & Sensors Microfluidics & Bio Tech Photovoltaics LED & Compound Semi Materials Advanced Packaging Photonics Power Electronics Equipment Rev. Eng./Costing Intellectual PropertyMarket, technology & strategy consulting Manufacturing costs analysis Reverse engineering M&A operations Due diligences IP Analysis Patent Assessment Fundraising Maturation of companies IP Portfolio Management Innovation Mgmt.
  5. 5. Copyrights © Yole Développement SA. All rights reserved. 5 5 Yole – A Group of Companies From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Finance MEMS & Sensors Microfluidics & Bio Tech Photovoltaics LED & Compound Semi Materials Advanced Packaging Photonics Power Electronics Equipment Rev. Eng./Costing Intellectual PropertyMarket, technology & strategy consulting Manufacturing costs analysis Reverse engineering M&A operations Due diligences IP Analysis Patent Assessment Fundraising Maturation of companies IP Portfolio Management With Global Presence  30 full time global analysts with technical, marketing and management background  > 3500 interviews per year Yole Inc. 30% 40% 30% Yole Korea Yole KK Japan Yole Europe
  6. 6. Copyrights © Yole Développement SA. All rights reserved. 6 6 Providing:  market analysis  technology evaluation  strategic analysis  business plan  finance  …. Consultancy across multiple fields and entire value chain Serving the Entire Value Chain across Multiple Fields Non-exhaustive list of clients From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Transportation makers Mobile & consumer electronics Automotive Medical systems Industrial & defense Energy From A to Z…
  7. 7. Copyrights © Yole Développement SA. All rights reserved. 7 7 Providing:  market analysis  technology evaluation  strategic analysis  business plan  finance  …. Consultancy across multiple fields and entire value chain Serving the Entire Value Chain across Multiple Fields Non-exhaustive list of clients From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Integrators and end- users Device makers OSAT, foundries… R&D centers Financial Investores etc. Suppliers: Equipment & Materials
  8. 8. Copyrights © Yole Développement SA. All rights reserved. 8 8 Market Trends and Drivers YOLE DEVELOPPEMENT FROM TECHNOLOGIES TO MARKET
  9. 9. Copyrights © Yole Développement SA. All rights reserved. 9 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 9 Y O L E D E V E L O P P E M E N T Computing Trends Increased integration: higher performance and increased functionality, smaller form factor, lower power consumption, lower cost  Miniaturization  Functionality  Mobility
  10. 10. Copyrights © Yole Développement SA. All rights reserved. 10 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 10 Y O L E D E V E L O P P E M E N T http://ec.europa.eu/digital-agenda/en/about-mobility The Driving Forces are Changing From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Driver Mainframe computers Fixed personal computer Mobile Consumer Internet of Things and the Cloud Key success Parameters 1. Performance 2. Cost 1. Cost 2. Performance 1. Cost 2. Power 3. Performance 4. Size 1. Cost 2. Power 3. Latency 4. Bandwidth density 5. Size Adapted after Bottoms – ECS 2014, Orlando Time Wired Wireless
  11. 11. Copyrights © Yole Développement SA. All rights reserved. 11 11 Advanced Packaging Platforms and Growth YOLE DEVELOPPEMENT FROM TECHNOLOGIES TO MARKET
  12. 12. Copyrights © Yole Développement SA. All rights reserved. 12 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 12 Y O L E D E V E L O P P E M E N T Silicon / Interconnection trend 500 020406080100 Number I/O per cm² 20.000 10.000 1500 CMOS90 CMOS45 CMOS28 CMOS16 CMOS65 FinFET Technology Node CMOS [nm] Scaling of Transistor Nodes => I/Os Density Increase
  13. 13. Copyrights © Yole Développement SA. All rights reserved. 13 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 13 Y O L E D E V E L O P P E M E N T Microelectronics Packaging Evolution Surface Mount Ball grid arrays SiPs WLCSP FC BGA PoP More SiPs WLCSP Flip-Chip Fan-Out Interposers 3DIC SiP 1980 TechnologyIntroduction GapFeaturesSivsPCB Through hole Mature 1970 1990 2000 2010 DIP, PGA SOP, QFP, PLCC CSPs/BGAs Today Established Emerging Feature sizes CMOS Bridging the Gap Between Si and PCB Processing Capabilities Feature sizes of PCBs
  14. 14. Copyrights © Yole Développement SA. All rights reserved. 14 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 14 Y O L E D E V E L O P P E M E N T Microelectronics Packaging Evolution Surface Mount Ball grid arrays SiPs WLCSP FC BGA PoP More SiPs WLCSP Flip-Chip Fan-Out Interposers 3DIC SiP 1980 TechnologyIntroduction GapFeaturesSivsPCB Through hole Mature 1970 1990 2000 2010 DIP, PGA SOP, QFP, PLCC CSPs/BGAs Today Established Emerging Feature sizes CMOS Bridging the Gap Between Si and PCB Processing Capabilities Feature sizes of PCBs Mobile: High-end Multimedia Smart-phones / PMP High-density Solid State Storage & µ-Cards Computing: Notebooks / MID ‘connectivity’ devices Consumer: Gaming / Graphic application engines Industrial: HPC/ Network, Servers Consumer: High-performance Digital Video Wireless: Connectivity / Network Center Medical Military & AerospaceTransportation: Automotive, Trains, HEV/EV Renewable Energy: Photovoltains, Wind Turbines… Telecom: Power Supplies… Industrial ….across several markets
  15. 15. Copyrights © Yole Développement SA. All rights reserved. 15 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 15 Y O L E D E V E L O P P E M E N T Trends in Semiconductor Packages To meet the ever-increasing demands for higher levels of system integration, semiconductor packages have evolved from through-hole to surface mount types, and from peripheral-leaded to area array formats. Increased functionality, speed => increased I/Os Performance: Additionally, the growing and diversifying system requirements have continued to drive the development of a variety of new package styles and configurations:  Small-form-factor and lightweight technology  Low-profile technology  High-pin-count technology  High-speed technology  Lower cost Complexity: Lead-frame based Packages Wirebonded FCBGA Through Silicon Via FCCSP PoP, PiP 3D Wirebonding …. 3D SiP
  16. 16. Copyrights © Yole Développement SA. All rights reserved. 16 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 16 Y O L E D E V E L O P P E M E N T Key Requirements for Advanced Packaging WLP •Lower packaging cost •Lower test cost I/Os density •Lower pitches •No standard •Smaller dies •Higher density of I/Os Integration •IPD •SiP •3D Thermal performance •Lower power consumption •Higher package density Electrical performance •Smaller Interconnect lines •Higher frequencies •Higher ackage speed •Lower parasitics Form-factor •Smaller thickness •Lower footprint • Improve chip-to-board coupling • New materials • Batch processing • Panel capability • Lower thickness • Multiple RDL • Interconnect optimization • Smallest thickness of the market • Integration capability • Low pitch capability Cost
  17. 17. Copyrights © Yole Développement SA. All rights reserved. 17 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 17 Y O L E D E V E L O P P E M E N T Critical Aspects  Limitations of established technologies to further accommodate market requirements • Inability to achieve higher performance due to processing capabilities or high costs • Inability to enable higher integration (3D/SiP, multi-chip integration) • Cost considerations • Need for innovative solutions, materials, equipment to address these challenges • Performance vs. cost considerations  New technologies coming to the market: • High cost • Lack of standardization • Multi-sourcing is not available • Infrastructure un-readiness • Collaboration – sometimes between competitors • New business models. • …
  18. 18. Copyrights © Yole Développement SA. All rights reserved. 18 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 18 Y O L E D E V E L O P P E M E N T Advanced Packaging Platforms Leadframes QFN,QFP w/o IC substrates Fan-in Fan-out IC substrates-based BGA (organic substrate) W/B BGA Flip Chip BGA 3DIC Interposer based Embedded die (in substrate) PCB substrate Increased functionality, I/Os, integration complexity Complexity: Single die Multiple Dies FO MCP Integration:2D 3D
  19. 19. Copyrights © Yole Développement SA. All rights reserved. 19 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 19 Y O L E D E V E L O P P E M E N T Current Industry Activities in Established and Emerging Advanced Packaging Segments Leadframes QFN,QFP w/o IC substrates Fan-in Fan-out IC substrates-based BGA (organic substrate) W/B BGA Flip Chip BGA 3DIC 2.5D Interposer Embedded die (in substrate) PCB substrate Increased functionality, I/Os, integration complexity Complexity: Single die Multiple Dies FO MCP Integration:2D 3D
  20. 20. Copyrights © Yole Développement SA. All rights reserved. 20 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 20 Y O L E D E V E L O P P E M E N T Fan-In WLCSP – Mature Platform Leadframes QFN,QFP w/o IC substrates Fan-in Fan-out IC substrates-based BGA (organic substrate) W/B BGA Flip Chip BGA 3DIC Interposer based Embedded die (in substrate) PCB substrate Increased functionality, I/Os, integration complexity Complexity: Single die Multiple Dies FO MCP Integration:2D 3D
  21. 21. Copyrights © Yole Développement SA. All rights reserved. 21 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 21 Y O L E D E V E L O P P E M E N T Fan-In WLCSP Market Drivers & Activities  Fan-in WLP maintains its appeal as the package that can provide 2 unmatchable advantages: • Reduced form factor • Low cost  Demand is reaching available capacity  Technology innovation in fan-in WLP continues: • Die size increases • Bump pitch reduces  Foundry involvement is no longer a dent in fan-in WLP production  Increased activity of Chinese capital on the market  New applications are emerging while other are declining • Disruptions also expected in the MEMS and CIS domains • Internet of Things ©2015 | www.yole.fr | Fan-in WLP: Market and Industrial Trends Mobile sector is driving fan-in WLP production and growing IoT is on the horizon and is expected to have a significant impact on fan-in packages and the packaging industry as a whole Mobile
  22. 22. Copyrights © Yole Développement SA. All rights reserved. 22 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 22 Y O L E D E V E L O P P E M E N T CPU Drivers Devices packaged using ‘Fan-in’ WLP Discrete passives Devices using other packaging technologies (not ‘Fan-in’ WLP WLCSP ICs in Handsets WLCSP 27% Others 73% WLCSP 35% Others 65% WLCSP 33% Others 67% Samsung Galaxy S6 Huawei Ascend Mate 7 iPhone 6+  Avg. 30% WLCSP packages in the latest high end smartphones!
  23. 23. Copyrights © Yole Développement SA. All rights reserved. 23 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 23 Y O L E D E V E L O P P E M E N T Fan-in WLP devices Automotive radar and gas sensors are the new fan-in applications on the horizon Analog & mixed signal Wireless Connectivity MEMS & sensorsOpto WLCSP Device Categories CMOS image sensors AL sensor photonic MEMS ASIC IC IPD (ESD/EMI protection, RF filtering) Inertial (Accelerometers, Gyroscopes, combos) Magnetometers Oscillators µ-Bolometers Chemical Sensors (gas, humidity) FBAR/BAW Filters Power Amplifiers BAW & SAW filters PMU IC drivers (LED, battery, display…) Local Power (DC-DC converters, MOSFET, oscillators) Audio & Video (Codec, amplifiers…) Bluetooth + FM + WLAN combos (+other combos) WLAN single chip GPS, A-GPS single chip Misc Logic and Memory Logic gates EEPROM/DRA M/SRAM/Flash µcontrollers Automotive radar Gas sensors RF Transceivers
  24. 24. Copyrights © Yole Développement SA. All rights reserved. 24 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 24 Y O L E D E V E L O P P E M E N T Fan-in Market Size and Growth  Fan-in WLP services, including wafer level, die level and test services accounted for almost 3 B$ in 2014 and are estimated to reach ~ 4.5 B$ by 2020 with a CAGR of 8% 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 2014 2015 2016 2017 2018 2019 2020 CAGR FanInWLPServices($M) Fan-In Market Value ($M) $3B $4.5B
  25. 25. Copyrights © Yole Développement SA. All rights reserved. 25 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 25 Y O L E D E V E L O P P E M E N T Fan-in WLP Wafer Count 0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 2014 2015 2016 2017 2018 2019 2020 CAGR Fan-InWaferCount(Mil.wafers) Fan-in Market Growth by Device Analog and Mixed Signal Wireless Connectivity Misc. Logic and memory CMOS image sensors MEMS and sensors Yole Developpement © June 2015
  26. 26. Copyrights © Yole Développement SA. All rights reserved. 26 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 26 Y O L E D E V E L O P P E M E N T 2014 Fan-in WLP Wafer Production • FI WLP manufacturing continue to be dominated by OSATs. Out of 10 top manufacturers, 8 are OSATs, 1 IDM (Texas Instruments) and 1 foundry (TSMC) ASE Global 15% Siliconware Precision Industries Co. (SPIL) Global 12% STATS ChipPAC Ltd Global 9% Texas Instruments 8% Amkor Global 8% TSMC Global 8% Deca Technologies 8% TeraProbe 7% NEPES 5% Flip-Chip international 5% STMicroelectronics Global 3% NXP 2% SilTech Semiconductor (SH) Co., Ltd. (SMIC) 2% JCET 2% UNISEM Global 1% IC Interconnect 1% Rohm semiconductor Global 1% OptoPAC 1% Nani um…LB semicon 0.3%China WLCSP 0.3% others 1% Yole Developpement June 2015
  27. 27. Copyrights © Yole Développement SA. All rights reserved. 27 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 27 Y O L E D E V E L O P P E M E N T Packaging Landscape 20mm² BGA 10*10mm 2000mm² FOOTPRINT I/O64 144 500 1531 3000 3000mm² 1000mm² FCBGA 55*55mm FCBGA 40*40mm FCBGA 31*31mm PBGA 27*27mm LFBGA 17*17mm BGA 15*15mm SO QFP WLCSP 25x23mm2 1188 balls 700um BGA 800 I/O Typical 8x8mm2, extreme 10x10mm2 WLCSP Flip Chip I/O limitation Can enable higher number of I/Os
  28. 28. Copyrights © Yole Développement SA. All rights reserved. 28 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 28 Y O L E D E V E L O P P E M E N T Bumping in 2.5D/3DIC Package Bumps/Cu Pillars: 40-250µm PCB BGA Laminate 2.5D Silicon interposer X-PU Logic Die Memory stack 400-800µm µ-Bumps: 10-40µm µ-Bumps 20-80µm 1 2 3 BGA balls  broad range of bumps, from larger BGAs (connection to the substrate) to very small microbumps used in stacking the memories 4
  29. 29. Copyrights © Yole Développement SA. All rights reserved. 29 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 29 Y O L E D E V E L O P P E M E N T Evolution of Flip-Chip Bumping Needs => Copper Pillar – continue to grow and maintain its leading position as the most used technology for Flip Chip bumping Au 25% Solder 39% Cu Pillar 36% 2011 Au 20% Solder 20% Cu Pillar 60% 2020 Au 27% Solder 29% Cu Pillar 44% 2014 Capacities(12”eq.wafers) Yole Developpement 2012 Yole Developpement 2015 Yole Developpement 2015
  30. 30. Copyrights © Yole Développement SA. All rights reserved. 30 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 30 Y O L E D E V E L O P P E M E N T Total Flip-Chip Market Value Forecast by COO Segment ($M) Yole Developpement © February 2013 Substrate 36% Repassivation, RDL & bumping 17% Assembly 15% Wafer Probe test 16% Final test 16% Substrate - the most important segment impacting the flip-chip cost structure, with more than 35% of the total market value.
  31. 31. Copyrights © Yole Développement SA. All rights reserved. 31 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 31 Y O L E D E V E L O P P E M E N T Status of Substrate Processing Capabilities Ibiden FCCSP 140um bump pitch 15/15um L/S 4/4 L/S 8/8 10/10 12/126/62/2 ……….15/25 100µm 50µm Bump Pitch 150µm Current Production Capabilities Bump Pitch: 130um & above L/S 12/12 & above Shinko (DLL) 130um bump pitch 14/14um (HVM) In Development: Aggressive developmental roadmaps: Bump pitch shrinking L/S narrowing • With core – substrates • Core-less substrates
  32. 32. Copyrights © Yole Développement SA. All rights reserved. 32 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 32 Y O L E D E V E L O P P E M E N T Market Evolution 100µm 10µm 1µm 100nm 10nm PCB Design Rule Wafer Design Rule Organic Substrate GAP! Silicon/Glass Interposer ~8-> 5µm More functionalities and advanced technologies nodes OSAT / Wafer foundries Substrate Manufacturers High Cost Lower cost than Si/Glass Interposer Opportunity for organic interposers and FanOut
  33. 33. Copyrights © Yole Développement SA. All rights reserved. 33 33 Fan-Out vs. Fan-In and Flip-Chip 1 2 3 5 Package/IC size ratio* Fan-in WLCSP Fan-out WLCSP Flip Chip This limit will move to higher ratios as eWLB production moves from 300mm wafers to large panels and the cost of eWLB/fan-out moves lowers. 4 6 IC IC IC Advantages of Fan-Out vs. Fan - In • Higher board-level reliability • Bumping is not limited to the die size, fan-out area beyond chip area limitation • Built-in back-side protection (protection available for WLCSP as an option only) • Lower thermal resistance • Higher potential for SiP integration vs. FCBGA • Smaller footprint • No substrate/interposer  Shorter interconnections • Higher electrical performance • lower cost • thinner package • Lower thermal resistance • Higher potential for SiP and 3D integration
  34. 34. Copyrights © Yole Développement SA. All rights reserved. 3434 Fan-Out Applications Typical view of a smart phone board RF SiP Digital SiP Sensor SiP Mixed Signal SiP SiP Modules: BGA/PoP/QFN/TSOP DC/DC converters Drivers IPD ESD/EMI Stand-alone chips: WL-CSP, SOT, QFN, UTLP, BGA Discrete passives Blue: Devices that can be found in FOWLP packages today Discrete passives Yellow: Devices that could be found in the future in FOWLP Grey: Devices that will likelyremain on WLCSP or flip-chip package or move to 3DIC or Embedded die TODAY TOMORROW ©2015 | www.yole.fr | Sumitomo Bakelite Workshop From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Yole Developpement 2015
  35. 35. Copyrights © Yole Développement SA. All rights reserved. 35 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 35 Y O L E D E V E L O P P E M E N T First Fan-out WLP Technologies Developed  eWLB has the advantage of easier process, especially thanks to better carrier and molding technology selection • Licensed to Statschippac, Nanium, ASE  RCP seems to have better performance in die shift but despite that does not have much success in the market • Licensed to Nepes  Main differences in the two processes: RCP uses a non compressed encapsulant and have additional copper plans that helps limiting the die shift during wafer molding and provides electromagnetic shielding and more rigidity to the package (but costs more!) eWLB vs RCP eWLB RCP
  36. 36. Copyrights © Yole Développement SA. All rights reserved. 36 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 36 Y O L E D E V E L O P P E M E N T New Fan-Out Technology Other manufacturers have entered the market more recently with their own developed technology:  Deca Technologies • Using an adaptive patterning technology to address die shift problems  SPIL • TPI FO (through package interconnect fan-out) • Targeting mid to high-end – 5/5 -> 2.2um L/S  Amkor • Started originally on 200mm and transitioned to 300mm • Developed SWIFT and SLIM technologies • Using chip-last fan-out approach (eliminating die-issue problems) • Targeting mid to high-end: 8/8-> 2/2um L/S (SWIFT) and < 2/2um L/S with SLIM  ASE • Utilizes a Low Cost FC Coreless Substrate with embedded traces and pads, fine pitch capable • Panel manufacturing already available in house (flip chip lines) • Low profile packages – as low as 375um  TSMC • TSMC claims its inFO to be a significantly thinner package than what is available on the market and a much tighter RDL pitch (i.e 5/5um L/S is available and 2/2um is announced for 2015)
  37. 37. Copyrights © Yole Développement SA. All rights reserved. 37 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 37 Y O L E D E V E L O P P E M E N T FOWLP 2014 Revenues Market Share 2014 FOWLP market status shows a domination of two players 59%25% 16% Main products: - eWLB single die packages for Mobile and Wireless  BB and Wireless SoC, RF, PMIC - MCP/SiP products for Mobile (PMU), Industrial, Medical and Security applications eWLB products mainly for - Mobile and Wireless  BB and Wireless SoC - RF Transceivers - ASIC Others ©2015 | www.yole.fr | Sumitomo Bakelite Workshop
  38. 38. Copyrights © Yole Développement SA. All rights reserved. 38 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 38 Y O L E D E V E L O P P E M E N T FOWLP Activity Market Forecast $0M $100M $200M $300M $400M $500M $600M $700M 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 FOWLP activity revenues (M$) Overall evolution since eWLB technology introduction TOT FOWLP (M$) Yole Developpement © 2015 CAGR ~ 10% Intel Mobile/ Inifneon eWLB-driven Transition phase Ramp-up with fab-less wireless IC players, wide FOWLP infrastructure/supply-chain and 2nd generation of FOWLP products CAGR ~ 10%
  39. 39. Copyrights © Yole Développement SA. All rights reserved. 39 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 39 Y O L E D E V E L O P P E M E N T 650x830mm – Gen 4 LCD 650x650mm – WLP/LCD/PCB 2009 - 2014 2015 2016 2017 > 20182018 450mm FOWLP 1st-gen - single die • BB SoC • RF Transceiver • ASIC • PMIC High yield Semiconductor WLP infrastructure Fusion WLP/PCB/LCD infrastructures 204x508mm (8”x20” ) - Semi/PCB laminate substrate 500x650mm – PCB laminate 470x370mm – LCD Gen 2 FOWLP 2nd-gen - MCP/SiP/PoP • DRAM memory • NAND Flash memory • APE/BB modem • RF Tx, RF connectivity • PMU/PMIC • GPS • MOEMS 330mm ©2015 | www.yole.fr | Sumitomo Bakelite Workshop Fan-out Cost and Infrastructure Evolution
  40. 40. Copyrights © Yole Développement SA. All rights reserved. 40 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 40 Y O L E D E V E L O P P E M E N T Drivers and Trends for 2.5D & 3DIC Evolution or Revolution? 3DIC / 3D SoC “De-integrated & Re-integrated SOC” 2D SOC “All-in-One chip system integration” All functions on 28nm lithography  Chip area ↑, Cost ↑ MEMS 130 nm 200 mm Memory 45 nm 300 mm Logic 20 nm 450 mm Analog 90 nm 300 mm 3D enables integration of heterogeneous functions: • On different lithography nodes • On different wafer sizes • In different wafer fabs • By different players  Cost ↓, Performance ↑, Size ↓Market Drivers
  41. 41. Copyrights © Yole Développement SA. All rights reserved. 41 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 41 Y O L E D E V E L O P P E M E N T Photonics Others (Power, LED, RF…) Memory TSV in a nutshell Through Silicon Via TSV MEMS Logic CMOS Image Sensors
  42. 42. Copyrights © Yole Développement SA. All rights reserved. 42 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 42 Y O L E D E V E L O P P E M E N T CMOS Image Sensor Evolution FSI BSI 3D Stacked BSI 20122008 TSV Hole to replace shell case approach Wafer Level Packaging Interconnection Trench TSV BEOL Interconnection TSV BEOL and DSP Interconnection « Real 3D » TSVCross-sectionSEMTSVNeedsIntegrationScheme
  43. 43. Copyrights © Yole Développement SA. All rights reserved. 43 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 43 Y O L E D E V E L O P P E M E N T CMOS Image Sensors Phone Ref. (Year) CIS Manufacturer Resolution/ Techno Pixel size Pixel Array Area CIS Area Dies per wafer (12-inch) Motorola Razor (2011) Omnivision 8Mp/BSI 1.4µm 16mm² 43mm² 1,500 Apple iPhone 4S (2011) Sony 8Mp/BSI 1.4µm 16mm² 35.4mm² 1,816 Samsung Galaxy SII (2011) Samsung 8Mp/BSI 1.4µm 16mm² 34.2mm² 1,884 Apple iPhone 5S (2013) Sony 8Mp/BSI 1.5µm 18mm² 28.5mm² 2,268 Courtesy System Plus Consulting ~50% ~60% ~60% ~90% Increase of pixel area
  44. 44. Copyrights © Yole Développement SA. All rights reserved. 44 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 44 Y O L E D E V E L O P P E M E N T Package Size Comparison 3-Axis Accelerometer Surface: SST= 4mm² Package thickness: TST= 1mm Surface: SmCube= 4mm² Package thickness: TmCube= 0.9mm Surface: SBosch= 1.8mm² Package thickness: TBosch= 0.8mm Bosch achieved 55% in package reduction and has the thinner package (0.8mm) SST = SmCube > SBosch TST > TmCube > TBosch Thinner and smaller packages
  45. 45. Copyrights © Yole Développement SA. All rights reserved. 45 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 45 Y O L E D E V E L O P P E M E N T 2.5/3DIC Commercial announcements!  2015 Key turning year for 3D TSV technology 2014 2011 2015 2017 2016 Nvidia Pascal Graphics Module EX-800 Blade Server using HMC New second generation Xenon Phi processor “Knights Landing” using HMC Next Generation PRIMEHPC POST FX10 CPU memory board using HMC DDR4 3D Dual Inline Memory Modules (RDIMMs) First Heterogeneous 3D FPGA Virtex-7 H580T AMD R9 390X Graphics product with HBM built with 20nm technology What else?
  46. 46. Copyrights © Yole Développement SA. All rights reserved. 46 From TECHNOLOGIES to MARKET Copyright @ Yole Developpement SA.. All rights reserved Y O L E D E V E L O P P E M E N T 46 Y O L E D E V E L O P P E M E N T Conclusion  All the packaging platforms will continue to grow, Fan-out and 3DIC being the ones expected to have the highest growth rate  Fan-in – stable growth, still driven by low cost and introduction of new consumer applications requiring low cost and pin count  Flip-chip – will continue to grow, but expected to loose overall market share to platforms such as WLCSP, Fan-Out and 3DIC. Cu Pillar will continue to be the dominant flip chip metallurgy  Fan-Out – very promising platforms already established in production. Currently using wafer infrastructure, may move to panel manufacturing in the future  2.5D & 3DIC – finally in production and adoption expected to grow. Fan-out could be a disruptive technology for consumer applications and less performing needs  OSATs will continue to be a dominant players in Packaging, however, foundries are entering this market and could take market share away from OSATs and IDMs
  47. 47. Copyrights © Yole Développement SA. All rights reserved. 47 47 Thank you! YOLE DEVELOPPEMENT COLLABORATION INNOVATION NEW PERSPECTIVES For additional information visit our websites: www.yole.fr & www.i-micronews.com Online free registration to YOLE publications For additional information please contact Rozalia Beica at beica@yole.fr

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