1. Wei Wei
Address: 3243 Almansa Ct, San Jose, CA 95127 Email: weiwee2013@gmail.com Tel: 312-661-2208
Objective:
Seeking full-time positions in ASIC/Digital design, verification, RTL design, validation, hardware design
Summary:
Experience and deep understanding in ASIC design flow, including RTL design, functional simulation and verification,
static timing analysis. Cooperative team member, strong communication skills with tactical and strategic thinking
capabilities.
Education:
Illinois Institute of Technology, Armour College of Engineering – Chicago, IL (01/2014 – 12/2015)
Degree: Master of Science in Electrical Engineering Concentration: Computer and Microelectronics GPA: 3.71
Related Course: Advanced VLSI Systems Design, Hardware/Software Co-design, Microcomputers, Embedded Digital
System, RF Integrated Circuit Design, CAD Technique for VLSI Design
Beijing Information Science & Technology University – Beijing, China (09/2007 – 06/2011)
Degree: Bachelor of Science in Electrical Engineering GPA: 79.1/100
Technical Skills:
Programming Language: Verilog, Assembly Language, C/C++, Python
Tools: Modelsim, Cadence Virtuoso, Altium Designer, Eclipse, Matlab, Visual Studio
Platform: Windows, Linux
Experience:
Employment:
Beijing SDi Science & Technology Co.,Ltd. – Beijing, China (06/2012 – 12/2013)
Position: Application Engineer
Worked at the Aerial Survey Department as an application engineer. Main job duties include experimental testing of
various electrical/electronic products. Detailed job duties include:
- Tested GPS/INS devices and OEM receiver boards and configured for clients
- Supported R&D department in new product design and development
- Provided clients with demonstration and with experimental data
Internship:
Beijing Sifang Automation Co.,Ltd. – Beijing, China (01/2011 – 03/2011) Position: Intern
The Company engaged in power supply, power system security and stability control etc.
Main job duties include experimental testing of power supply and electrical distribution system products.
Enhanced experience in group collaboration and communication.
Academic Projects:
Asynchronous FIFO Design (RTL)
- Designed asynchronous FIFO with synthesizable RTL coding
- Set up testbench and performed multi-clock domain simulation
FinFET Transistor Characterization and Independent Mode Operation (Transistor Level)
- Designed and implemented 2-input NAND gate based on FinFET (SG, LP, IG, and Hybrid IG/LP mode)
- Comparatively analyzed the trade-offs between delay and power consumption of 2-input NAND gate in different
FinFET configurations based on HSPICE
Design and Synthesis of Propagation Adders
- Design 4-bit and 32-bit carry-ripple adder, carry-skip adder, carry-select adder and 16-bit multiplier
- Set up testbench to verify the functionality of each adder and multiplier
- Completed design flow including RTL design, RTL simulation, logic synthesis, place & route and equivalence
checking, analyzed area, critical path delay and power consumption
Basic AMBA System Design (RTL)
- Designed a basic AMBA System based on AHB protocol, including AHB arbiter, decoder, supporting
burst/locked transfer operation, able to deal with retry response
- Combined the AMBA System with a dummy CPU, memory and FIFO
- Set up direct testbench to verify the AMBA System
Fast Fourier Transform on NoC Architecture (System C)
- Determined utilization rates and queue sizes of a given NoC Architecture consisting of 2 PEs and 2 Routers
- Build up a 3x3 2-D mesh NoC architecture based on given NoC Architecture (9 PEs and 9 Routers)
- Performed 8-point DFT by using FFT on designed NoC model